KR100677773B1 - Method for forming a capacitor in semiconductor device - Google Patents

Abstract

The present invention is to provide a method of forming a capacitor of a semiconductor device that can improve the yield of the semiconductor device by improving the surface roughness of the insulating film present in the bottom electrode when the capacitor of the semiconductor device formed, for this purpose, Forming an interlayer insulating film having a contact plug interposed therebetween; depositing an insulating film for forming a capacitor structure on the interlayer insulating film including the contact plug; and insulating film for forming the capacitor structure on the insulating film for forming the capacitor structure; Forming a hard mask pattern formed of an insulating material having a different etching selectivity from that of the insulating material; forming a hole for exposing the contact plug by etching the insulating film for forming the capacitor structure through the hard mask pattern; An upper end of the hard mask pattern Following the etch-back process carried out in the step of depositing a lower electrode, to provide a method for forming a capacitor of a semiconductor device, comprising the step of separating the lower electrodes.

Capacitors, amorphous carbon, hard masks, insulating films, surface roughness.

Description

METHODO FOR FORMING A CAPACITOR IN SEMICONDUCTOR DEVICE

1A to 1C are cross-sectional views illustrating a process of forming a metal-insulator-metal (MIM) capacitor having a Ru bottom electrode according to the prior art;

Figure 2 is a SEM photograph showing a semiconductor device after performing a thermal process after CVD deposition of Ru for forming the lower electrode in accordance with the prior art.

Figure 3 is a SEM photograph showing a semiconductor device after the etch back process for the separation of the lower electrode in accordance with the prior art.

Figure 4 is a schematic diagram shown for explaining the problem shown in FIG.

5 is a SEM photograph showing a semiconductor device after completing the process of forming the dielectric film and the upper electrode according to the prior art.

6A to 6D are cross-sectional views illustrating a capacitor forming process of a semiconductor device in accordance with a preferred embodiment of the present invention.

7 is a schematic diagram for explaining the reason why the surface roughness characteristics of the capacitor insulating film is improved according to FIGS. 6A to 6D.

<Explanation of symbols for the main parts of the drawings>

110: semiconductor substrate

112: interlayer insulating film

113: Storage Node Contact Plug

114: ohmic contact layer

115: antioxidant film

118: etch stop

120: insulating film for capacitor structure formation

122: hard mask (or hard mask pattern)

126: lower electrode

128: dielectric film

130: upper electrode

135: MIM Capacitor

The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a method of forming a MIM capacitor of a semiconductor device having ruthenium (Ru) as a lower electrode.

As the degree of integration of semiconductor memory devices is improved, the area of a unit cell is gradually reduced, and the area of a capacitor per unit cell is also reduced, thereby reducing capacitance. Accordingly, a method of increasing the effective surface area of a capacitor by growing a hemispherical grain (HSG: HemiSpherical Grain) in a stack structure or a cylindrical structure has been proposed as one method for increasing the capacitance.

However, the process margin of forming the capacitor structure is reduced by the subsequent design rule shrinking of the semiconductor device, and the yield of the semiconductor device is reduced. Therefore, the capacitance is increased by a method other than the structure change of the capacitor as described above. For example, ONO (Silicon Oxide / Silicon Nitride / Silicon Oxide), which is used as a dielectric film of a capacitor, a Ta ₂ O ₅ having a high dielectric constant, (Ba _1-X Sr _X ) TiO ₃ (BST) ), Many studies have been made to replace high-k dielectric films such as SrTiO ₃ (STO), HfO ₂ , TiO ₂ , ZrO _2, and La ₂ O ₃ . As another example, many studies have been conducted to replace polysilicon, which was previously used as a lower electrode of a capacitor, with a metal having a large work function value.

In particular, research on the formation of a rare earth metal-based lower electrode having a high leakage barrier property and maintaining excellent interfacial properties due to less reactivity of the oxide film and the lower electrode in the deposition process of the oxide dielectric film or in the subsequent heat treatment process is being actively conducted. . Representatively, ruthenium (Ru) is applied to the formation of a capacitor of a semiconductor memory device because ruthenium (Ru) is easier to deposit using a CVD (Chemicla Vapor Deposition) method than a metal of the same series Pt, Ir, etc., and the processability of subsequent capacitor structures is good.

1A to 1C are cross-sectional views illustrating a process of forming a metal-insulator-metal (MIM) capacitor having a Ru bottom electrode according to the related art.

First, as shown in FIG. 1A, an interlayer dielectric layer 12 (ILD) is deposited on the semiconductor substrate 10 on which an isolation process, a word line, and a bit line forming process are completed.

Subsequently, the interlayer insulating layer 12 is etched to form a contact hole (not shown) that exposes a portion of the substrate 10, and polysilicon is deposited to fill the contact hole, thereby depositing a storage node contact plug 13 (hereinafter, referred to as a contact plug). Is called). Then, after recessing the contact plug 13 to a predetermined thickness, the contact plug 13 is used to reduce the contact resistance between the contact plug 13 and the lower electrode 26 to be subsequently formed (see FIG. 1C). TiSi ₂ is formed as an ohmic contact layer 14 on top.

Subsequently, TiN is deposited to prevent oxidation of TiSi ₂ that may occur in the dielectric film deposition process or the thermal process of the capacitor that is subsequently formed on the ohmic contact layer 14 so that the contact hole is filled, and then etch back Alternatively, a chemical mechanical polishing (CMP) process may be performed to form an antioxidant layer 15 embedded only in the contact hole.

Subsequently, as illustrated in FIG. 1B, a nitride film is deposited on the interlayer insulating film 12 including the antioxidant film 15 by the etch stop film 18, and then the capacitor structure is formed on the etch stop film 18. An insulating film 20 (hereinafter referred to as a capacitor insulating film) is deposited. Then, polysilicon is deposited on the capacitor insulating film 20 with a hard mask 22.

Next, the hard mask 22 is etched by performing an etching process using a predetermined photoresist pattern (not shown) formed through a photolithography process. Thereafter, a strip process is performed to remove the photoresist pattern, followed by an etching process using the etched hard mask 22 to sequentially etch the capacitor insulating film 20 and the etch stop film 18. As a result, a hole 24 exposing the antioxidant film 15 is formed.

Subsequently, as illustrated in FIG. 1C, an etching process is performed to remove the hard mask 22 made of polysilicon, and the capacitor may be disposed along the stepped portion of the capacitor insulating film 20 including the holes 24 (see FIG. 1B). Ru is deposited on the lower electrode 26. Then, the lower electrode 26 is separated by performing an etch back process to remove Ru exposed to the upper portion of the capacitor insulating film 20.

However, according to the prior art as described above, various problems such as Ru agglomeration occur.

FIG. 2 is a SEM (Scanning Electron Microscope) photograph of a semiconductor device after performing a thermal process after CVD deposition of Ru for forming the lower electrode 26 as shown in FIG. 1C. Referring to FIG. 2, it can be seen that Ru after a CVD deposition process and a thermal process has a problem in that a part of the coagulation occurs.

FIG. 3 is a SEM photograph showing a semiconductor device after an etch back process for separation of the lower electrode 26 as shown in FIG. 1C. Referring to FIG. 3, it can be seen that the capacitor insulating film 20 after the etch back process has a problem in that surface roughness (see 'A' region) characteristics are deteriorated.

FIG. 4 is a schematic diagram illustrating the problem shown in FIG. 3. Referring to FIG. 4, when an etchback process is performed on an entire structure in which a lower electrode 26 having a crystal structure is discontinuously aggregated, a portion of the capacitor insulating film 20 at the bottom of the lower electrode 26 is etched together to form a capacitor insulating film. It turns out that the surface roughness characteristic of (20) falls. As such, the phenomenon in which a portion of the capacitor insulating film 20 is etched has a low etching selectivity between the lower electrode 26 and the capacitor insulating film 20, so that the capacitor insulating film 20 in the portion exposed between the grains of the lower electrode 26 is easily etched. Because it happens.

FIG. 5 is a SEM photograph illustrating a semiconductor device after completing a subsequent dielectric film and upper electrode forming process. FIG. Referring to FIG. 5, it can be seen that a dielectric film and an upper electrode residue exist in the capacitor insulating film 20 of the etched portion as in FIG. 4. This residue causes the yield reduction of the semiconductor device, including defects in subsequent metallization processes.

Accordingly, the present invention has been made to solve the problems of the prior art, a semiconductor device that can improve the yield of the semiconductor device by improving the surface roughness characteristics of the insulating film present on the bottom of the lower electrode when forming the capacitor of the semiconductor device It is an object of the present invention to provide a method for forming a capacitor.

According to an aspect of the present invention, there is provided a method of forming an interlayer insulating film including a contact plug on a substrate, and depositing an insulating film for forming a capacitor structure on the interlayer insulating film including the contact plug. And forming a hard mask pattern made of an insulating material having an etch selectivity different from that of the capacitor structure forming insulating film on the capacitor structure forming insulating film, and etching the capacitor structure forming insulating film through the hard mask pattern. Forming a hole exposing a contact plug, depositing a lower electrode along a top surface step of the hard mask pattern including the hole, and performing an etch back process to separate the lower electrode A method of forming a capacitor of a semiconductor device is provided.

Here, the hard mask pattern is formed of amorphous carbon.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. Also, throughout the specification, the same reference numerals denote the same components.

Example

6A through 6D are cross-sectional views illustrating a capacitor forming process of a semiconductor device in accordance with a preferred embodiment of the present invention.

First, as shown in FIG. 6A, first, as shown in FIG. 1A, an interlayer insulating layer 112 is deposited on the semiconductor substrate 110 on which an isolation process, a word line, and a bit line forming process are completed. do. Here, the interlayer insulating film 112 is formed of an oxide film-based material. For example, the interlayer insulating layer 112 may include an HDP (High Density Plasma) oxide film, a Boron Phosphorus Silicate Glass (BPSG) film, a Phosphorus Silicate Glass (PSG) film, a Plasma Enhanced Tetra Ethyle Ortho Silicate (PETOS) film, and a Plasma Enhanced Chemical Vapor (PECVD) film. A single layer film or a laminate of these layers is laminated using any one of a deposition film, a USG (Un-doped Silicate Glass) film, a Fluorinated Silicate Glass (FSG) film, a Carbon Doped Oxide (CDO) film, and an Organic Silicate Glass (OSG) film. Form into a film.

Subsequently, the interlayer insulating layer 112 is etched by performing a mask process and an etching process to form a contact hole (not shown) exposing a part of the substrate 110. Then, polysilicon is deposited to fill the contact hole to form a storage node contact plug 113 (hereinafter referred to as a contact plug). In this case, polysilicon is deposited using LPCVD (Low Pressure Chemical Vapor Deposition) method using SiH ₄ as doped silicon.

Subsequently, an etch back process is performed to recess the contact plug 113 to a predetermined depth, preferably 0.05 to 0.2 μm, and then the contact plug 113 and the lower electrode 26 to be subsequently formed are referred to. TiSi ₂ is formed as an ohmic contact layer 114 on the contact plug 113 to reduce the contact resistance between the layers. At this time, TiSi ₂ is formed by depositing a titanium film (Ti) on the contact plug 113 on the entire surface with a thickness of 0.02 to 0.08 μm, and then performing heat treatment at a temperature of 600 to 750 ° C. in an N ₂ atmosphere.

Subsequently, TiN is deposited to prevent oxidation of TiSi ₂ , which may occur in the dielectric film deposition process or the thermal process of the capacitor that is subsequently formed on the ohmic contact layer 114 to fill the contact hole, and then etch back Alternatively, a chemical mechanical polishing (CMP) process may be performed to form an antioxidant film 115 embedded only in the contact hole. In this case, TiN may be deposited to a thickness of 0.05 to 0.12 μm, and TiAlN, TiSiN, or TaSiN may be used instead of TiN.

Subsequently, a nitride film is deposited on the interlayer insulating film 112 including the anti-oxidation film 115 by the etch stop film 118, and then an insulating film 120 for forming a capacitor structure is formed on the etch stop film 118. Deposition). In this case, the etch stop film 118 is deposited to a thickness of 0.05 to 0.10㎛, the capacitor insulating film 120 is deposited to a thickness of 1.0 to 2.0㎛.

Subsequently, an insulating material having a different etching selectivity from the capacitor insulating layer 120 is deposited on the capacitor insulating layer 120 to form the hard mask 122. Preferably, it is formed from amorphous carbon. At this time, amorphous carbon is deposited using PE 3 (Plasma Enhanced CVD) method using C ₃ H ₆ as a source gas and He as a carrier gas. In addition, amorphous carbon is deposited by performing a PECVD process with a RF (Radio Frequency) power of 300 to 1000W at a temperature of 400 to 600 ℃, a thickness of 0.1 to 0.5㎛.

Subsequently, as shown in FIG. 6B, after the photoresist (not shown) is coated on the hard mask 122, a photoresist pattern (not shown) is performed by performing an exposure and development process using a photomask (not shown). To form. Thereafter, an etching process using the photoresist pattern as an etching mask is performed to etch the hard mask 122 to form the hard mask pattern 122.

Subsequently, after the strip process is removed to remove the photoresist pattern, an etching process using the hard mask pattern 122 is performed to sequentially etch the capacitor insulating film 120 and the etch stop film 118. As a result, a hole 124 exposing the antioxidant film 115 is formed.

Subsequently, as shown in FIG. 6C, the lower electrode of the capacitor is formed along the step of the entire structure including the holes 124 (see FIG. 6B) while the hard mask pattern 122 made of amorphous carbon is left without being removed. Ru is deposited at 126. At this time, Ru is deposited at a thickness of 0.02 to 0.07 μm using Ru (od) ₃ as a source gas and O ₂ or O ₂ / NH ₃ gas as a reaction gas at a temperature of 250 to 400 ° C.

Here, the hard mask pattern 122 does not need to be removed because amorphous carbon is not a conductive material as in conventional polysilicon.

Subsequently, although not shown in the drawing, after the deposition of Ru to remove impurities in the lower electrode 126 or to increase the film density, the film may be 0.5 to a temperature of 450 to 500 ° C. in an NH ₃ or H ₂ atmosphere. RTP (Rapid Thermal Processing) process can be performed for 5 minutes.

Subsequently, the lower electrode 126 is separated by performing an etch back process to remove Ru exposed on the capacitor insulating layer 120. In this etchback process, a mixture of HBr / O ₂ gas is usually used.

Subsequently, as shown in FIG. 6D, the dielectric film 128 is deposited along the stepped portion of the hard mask pattern 122 including the separated lower electrode 126. Here, the dielectric film 128 is formed of a single film of Ta ₂ O ₅ , (Ba _1-X Sr _X ) TiO ₃ (BST), SrTiO ₃ (STO), HfO ₂ , TiO ₂ , ZrO _2, or La ₂ O ₃ . Or a composite film in which these are mixed.

Subsequently, the upper electrode 130 is formed along the stepped portion of the dielectric layer 128. In this case, the upper electrode 130 is formed of a single layer of Ru, Pt, Ir, or TiN, or a composite film of a mixture thereof. This completes the MIM (eg Ru / Ta ₂ O ₅ / Ru) capacitor 135.

FIG. 7 is a schematic view for explaining the reason why the surface roughness characteristic of the capacitor insulating film 120 is improved according to the preferred embodiment of the present invention. Referring to FIG. 7, even when grains are generated in the lower electrode 126 due to the aggregation of Ru, the surface of the capacitor insulating film 120 may be smoothed.

That is, in the preferred embodiment of the present invention, the lower electrode (eg, the hard mask pattern 122 made of amorphous carbon, which has an etch selectivity different from that of the capacitor insulating film 120, for example, amorphous carbon) is left on the capacitor insulating film 120. By performing an etch back process for separation of the 126, the capacitor insulating film 120 of the portion exposed between the crystal grains of the lower electrode 126 is not easily removed even during the etch back process. Therefore, the phenomenon in which the surface roughness characteristic of the capacitor insulating film 120 is lowered during the formation of the capacitor of the semiconductor device can be suppressed.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the lower electrode is separated in a state in which a hard mask pattern made of an amorphous carbon, such as amorphous carbon, is left on top of the insulating film for forming the capacitor structure with an etching selectivity different from the insulating film for forming the capacitor structure. By performing the etch back process for the purpose, the insulating film for forming the capacitor structure of the portion exposed between the crystal grains of the lower electrode is not easily removed even during the etch back process. Therefore, the phenomenon in which the surface roughness characteristic of the insulating film for capacitor structure formation falls at the time of capacitor formation of a semiconductor element can be suppressed.

Further, it is possible to suppress the defect in the metal wiring process to be subsequently performed and to increase the yield of the semiconductor element.

Claims (16)

Forming an interlayer insulating film having a contact plug interposed on the substrate; Depositing an insulating film for forming a capacitor structure on the interlayer insulating film including the contact plug; Forming a hard mask pattern on the capacitor insulation layer forming insulating layer, the hard mask pattern including an insulation material having an etching selectivity different from that of the insulation layer forming the capacitor structure; Etching the insulating film for forming the capacitor structure through the hard mask pattern to form a hole exposing the contact plug; Depositing a lower electrode along a step of an upper surface of the hard mask pattern including the hole; And Performing an etch back process to separate the lower electrode Capacitor formation method of a semiconductor device comprising a. The method of claim 1, And the hard mask pattern is formed of amorphous carbon. The method according to claim 1 or 2, The hard mask pattern is a capacitor forming method of a semiconductor device which is deposited using C ₃ H ₆ and He gas. The method according to claim 1 or 2, The hard mask pattern is a method of forming a capacitor of a semiconductor device deposited by a PECVD method to a thickness of 0.1 to 0.5㎛ at a temperature of 400 to 600 ℃ and RF power conditions of 300 to 1000W. The method of claim 1, And the lower electrode is formed of ruthenium. The method of claim 5, The ruthenium is a method of forming a capacitor of a semiconductor device formed by using Ru (od) ₃ as a source gas and O ₂ or O ₂ / NH ₃ gas as a reaction gas. The method according to claim 5 or 6, The ruthenium is a capacitor forming method of a semiconductor device which is deposited at a thickness of 0.02 to 0.07㎛ at a temperature of 250 to 400 ℃. The method of claim 1, After depositing the lower electrode, And performing a thermal process so that the density of the lower electrode is increased. The method of claim 8, The step of performing the thermal process is a capacitor forming method of a semiconductor device made in NH ₃ or H ₂ atmosphere. The method according to claim 8 or 9, The thermal process is a capacitor forming method of a semiconductor device performing a RTP process for 0.5 to 5 minutes at a temperature of 450 to 500 ℃. The method of claim 1 or 8, after forming the lower electrode, Depositing a dielectric film along a step on an upper portion of the hard mask pattern including the lower electrode; And Forming an upper electrode on the dielectric layer Capacitor forming method of a semiconductor device further comprising. The method of claim 11, The dielectric layer is formed of a single layer of Ta ₂ O ₅ , (Ba _1-X Sr _X ) TiO ₃ (BST), SrTiO ₃ (STO), HfO ₂ , TiO ₂ , ZrO _2, or La ₂ O ₃ , or a mixture thereof. A method for forming a capacitor of a semiconductor device formed of a composite film. The method of claim 11, And the upper electrode is formed of a single film of Ru, Pt, Ir, or TiN or a composite film of a mixture thereof. The method of claim 1, And forming the contact plug in a stacked structure of a polysilicon / ohmic contact layer / antioxidation layer. The method of claim 14, And the ohmic contact layer is formed of TiSi _X (wherein _X is 1 to 10). The method according to claim 14 or 15, The anti-oxidation film is a capacitor forming method of a semiconductor device formed of TiN.

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