KR20010035666A - Method of forming a capacitor with a single photolithography and etching process to define a plate electrode and a trench for a storage electrode - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor is provided to form a double plate electrode structure forming a trench for a storage electrode by using a plate electrode, and to prevent a lifting phenomenon of polysilicon in a lift-off process of a conventional sacrificial oxide layer. CONSTITUTION: The first insulating layer having a storage contact pad is formed on a semiconductor substrate(100). The second insulating layer, the first plate electrode layer and the third insulating layer for forming a trench for a storage electrode are formed on the storage contact pad and the first insulating layer. The third insulating layer, the first plate electrode layer and the second insulating layer are etched to form a trench for the storage electrode exposing the pad while the first plate electrode pattern is defined. The first capacitor dielectric layer and the first storage electrode layer are formed inside the trench and on the third insulating layer. The first dielectric layer and the first storage electrode layer are anisotropically etched to form a sidewall spacer. The second storage electrode layer is formed on the resultant structure. The fourth insulating layer is formed on the second storage electrode layer to completely fill the trench. The fourth insulating layer and the second storage electrode layer are planarization-etched until the third insulating layer is exposed. The fourth insulating layer remaining inside the trench is removed. The second dielectric layer and the second plate electrode layer(400) are formed inside the trench.

Description

METHODO OF FORMING A CAPACITOR WITH A SINGLE PHOTOLITHOGRAPHY AND ETCHING PROCESS TO DEFINE A PLATE ELECTRODE AND A TRENCH FOR A STORAGE ELECTRODE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a stacked capacitor and a method of manufacturing the same.

Recently, semiconductor devices have been highly integrated in terms of economic cost. In particular, in the case of a memory device such as DRAM (DRAM), increasing the density is an important place. As is well known, increasing the degree of integration of semiconductor devices inevitably reduces the area occupied by the various elements formed on the semiconductor substrate. However, the capacitors that make up a memory device require a minimum constant capacitance for reliable device operation. Approximately 30 fF per cell should be maintained to prevent soft errors caused by alpha-particles or errors in stored data due to noise.

Therefore, the method of integrating capacitors having the same capacitance in a small cross-sectional area is one of the important problems in DRAM due to the ultra-high integration that integrates a large number of devices in the same area or the same wafer and the reduction of the minimum line width due to the development of semiconductor processing technology. Can be.

Many methods have been proposed to achieve this, but mainly hemispherical silicon grains (HSG) have been grown to increase the capacitor area in stacked and cylindrical structures, and capacitors having the same capacitance of about 30 fF have been used.

However, due to the density of more than 1 gigabit and the continuous decrease in the minimum line width, there is a lack of process margins such as misalignment of process and spacing between capacitor storage electrodes, resulting in bridges between capacitor storage electrodes in adjacent cells. Will occur. Such a bridge is a big obstacle in implementing a highly integrated DRAM because it causes a pair of twin bit fail or a multi bit fail.

In the conventional simple box stack cell structure, increasing the distance from adjacent storage electrodes to solve the above problem reduces the surface area of the available capacitor storage electrodes and consequently reduces the capacitor capacitance.

Recently, in order to solve such a problem and increase the capacitance of a capacitor, a storage electrode-type contact is formed through a sacrificial oxide layer in a stack cell, a conductive electrode for the storage electrode is filled in a contact, and the storage electrode is separated by a cell. A method of completing the storage electrode by removing the same has been proposed. As a method of filling silicon into a contact in the form of a storage electrode, there is a method of filling all silicon into a contact and only a contact side (cylindrical capacitor).

In the above-described stack-type capacitor forming method, since the process of removing the sacrificial oxide film uses a lift off method, particles generated due to lifting of the silicon remaining in the stepped portion after the planarization process are frequently caught. Problems arise.

The present invention has been proposed to solve the above-mentioned problems, and provides a double plate electrode structure for forming a contact type storage electrode through a plate electrode instead of a sacrificial oxide film, and in and out of a cylinder and a storage electrode pad without lifting off the sacrificial oxide film. It is an object of the present invention to provide a method of forming a capacitor of a cylindrical shape that can be used as a storage electrode up to a portion thereof.

1 to 9 are cross-sectional views schematically showing a novel stacked capacitor forming method according to the present invention.

* Explanation of symbols for the main parts of the drawings

100 semiconductor substrate 120 inactive region

140: active region 160, 180: insulating film

200: storage contact pads 220, 260: trench insulating film

240: first plate electrode film 280: trench for storage node

300, 380: first and second capacitor dielectric films 320, 340: first and second storage electrode films

360: planarization insulating film 400: second plate electrode film

420: interlayer insulating film 440: metal wiring

The present invention relates to a method of forming a stacked capacitor having a plate electrode pattern and a trench for a storage electrode simultaneously in one photo process and having a double plate electrode.

(Configuration)

According to the stacked capacitor forming method of the present invention for achieving the above object, forming a first insulating film having a storage contact pad formed on a semiconductor substrate, and for the storage electrode on the storage contact pad and the first insulating film Sequentially forming a second insulating film, a first plate electrode film, and a third insulating film as a film for forming a trench, and etching the third insulating film, the first plate electrode film, and the second insulating film to expose the pad. Forming a trench for the storage electrode and simultaneously defining a first plate electrode pattern; forming a first capacitor dielectric film and a first storage electrode film inside the trench and on the third insulating film; Anisotropically etch the first storage electrode layer to leave only the sidewalls of the trench to form sidewall spacers. Forming, forming a second storage electrode film on the resultant, forming a fourth insulating film on the second storage electrode film to completely fill the trench, and until the third insulating film appears. Planarizing and etching the fourth insulating film and the second storage electrode film, removing the fourth insulating film remaining inside the trench, and forming a second dielectric film and a second plate electrode film inside the trench. This is done by including the steps.

In an embodiment, forming the sidewall spacers by anisotropically etching the first dielectric layer and the first storage electrode layer to leave only the sidewalls of the trench to increase the surface area of the storage electrode. It further comprises etching a portion.

The stacked capacitor according to the present invention for achieving the above object has a plurality of sidewalls and upper surfaces consisting of a first insulating film, a first plate electrode film and a second insulating film which are sequentially formed on the interlayer insulating film at regular intervals. A plurality of trenches for storage electrodes are defined by a first plate electrode pattern, opposite sidewalls of the adjacent first upper electrode pattern, and the interlayer insulating layer therebetween, and a first capacitor dielectric layer formed on both sidewalls of the trench; On the first storage electrode sidewall spacer formed on the first capacitor dielectric layer, the second storage electrode layer formed on the sidewall spacer for the first storage electrode and the trench bottom, on the second storage electrode layer and the second insulating layer A second capacitor dielectric film formed and the trench formed on the second capacitor dielectric film Completely filling takes place, including the second electrode plate film.

(Action)

According to the novel stacked capacitor forming method of the present invention described above, a storage electrode pattern is formed into a contact type (a trench is formed) through an insulating layer and a thick plate electrode film on the storage electrode pad, and the first contact is made through the contact. After the dielectric film and the first storage electrode are formed, the storage electrode is anisotropically etched to form spacers on the contact sidewalls. The second storage electrode and the second dielectric layer may be formed to be used as a capacitor not only inside and outside the thick plate electrode layer contact, but also as a part of the insulating layer and the storage electrode pad, thereby increasing capacitance.

According to the above method, by forming a contact for a storage electrode (trench) in the plate electrode film instead of the sacrificial oxide film, the sacrificial oxide film lift-off process is prevented primitively, thereby eliminating the lifting of silicon and the resulting particle problem caused by the conventional sacrificial oxide film lift-off. You can prevent it. In addition, the plate electrode pattern can be simultaneously formed by the trench forming process for the storage electrode, thereby reducing the photolithography process.

(Example)

The present invention relates to a stacked capacitor and a method of forming the same, wherein a storage electrode pattern is formed in a trench using a thick capacitor plate electrode film instead of a conventional sacrificial oxide film, and a dielectric film is formed through a trench defined by the plate electrode film. Storage electrodes are formed. That is, the storage electrode and the plate electrode are formed by one photo process pattern by changing the order of the storage electrode and the plate electrode process of the capacitor. In addition, without using a conventional sacrificial oxide film, both the inside and the outside of the cylindrical capacitor can be used as the storage electrode.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 9. In the presented drawings, the thickness of the film to be deposited and the region to be formed are somewhat exaggerated for clarity of explanation and simplification of the drawings.

Since the present invention relates to a method for forming a capacitor, a conventional semiconductor manufacturing process before capacitor formation will be briefly described, and not shown in the drawings presented for clarity of understanding and simplicity of the invention.

9 is a schematic cross-sectional view of a stacked capacitor according to the present invention. The stacked capacitor according to the present invention has a double plate structure composed of a first plate electrode 240a and a second plate electrode 400, as shown, so that the capacitors can be disposed both inside and outside of the cylindrical storage electrode. Can be used as Specifically, the storage electrode contact pads 200 are formed in the insulating layers 180 and 160, and the cylindrical storage electrodes 320a and 340a are formed to be electrically connected to the pads, and inside the cylindrical storage electrodes. The second dielectric layer 380 and the second plate electrode 400 are formed, and the first dielectric layer 300a and the first plate electrode 240a are formed on the outside of the cylindrical storage electrode to have a double plate electrode. Provides a stacked capacitor. The capacitor forming method shown in FIG. 9 will be described in detail below.

1 is a plan view schematically illustrating a semiconductor substrate 100 after forming a storage electrode pad 200 in forming a stacked capacitor according to the present invention. Although not shown in the figure, transistors, bit lines, and the like are formed in the insulating layers 160 and 180. Briefly, first, the semiconductor substrate 100 is prepared. The semiconductor substrate 100 is typically divided into a cell array region and a peripheral circuit region. A plurality of active regions surrounded by the device isolation region 120 and the device isolation region 120 on the semiconductor substrate 100 by a conventional device isolation process, for example, a shallow trench isolation technique. 140 is defined.

Next, an ion implantation process for adjusting the well and transistor threshold voltages is performed in a conventional manner. Then, the conventional transistor forming process proceeds. In brief, a gate oxide layer is grown, a gate electrode material and a gate capping layer are deposited, a photolithography process and an etching process are performed, and an ion implantation process for forming a junction region is performed on the active region 140 to complete a transistor. . The bit line is then formed in the usual manner. The bit line is formed in the interlayer insulating layer 160 shown in the drawing, and the transistor is electrically isolated from the transistor by an insulating layer different from the bit line. Next, another interlayer insulating layer 180 is formed on the bit line and the one interlayer insulating layer 160.

The next step is to form a storage electrode contact pad, in which an opening is formed to etch the interlayer insulating layers 180 and 160 to expose the impurity diffusion region 140 and a conductive material such as doped polysilicon is formed to fill the opening. The storage electrode contact pads 200 are formed on the interlayer insulating layer 180 to be planarized to complete the storage electrode contact pads 200 in the cell array region.

The next process is a stacked capacitor formation process. Referring to FIG. 2, a first insulating film 220, a first plate electrode film 240, and a second insulating film 260 are formed on the interlayer insulating film 180 including the contact pad 200. The first plate electrode layer 240 and the first insulating layer 220 determine the height of the storage electrode. The first insulating layer 220 may be formed of, for example, an oxide film (or a nitride film) and may have a thickness of about 1,000 Angstroms to 2,000 Angstroms. The first plate electrode layer 240 is formed of doped polysilicon and has a thickness of about 10,000 Angstroms to 20,000 Angstroms. The second insulating layer 260 is formed of a nitride film (or an oxide film) to facilitate separation of storage electrodes in a cell unit, and has a thickness of about 1,000 Angstroms to 2,000 Angstroms.

Next, referring to FIG. 3, a trench for forming a storage electrode in which the second insulating layer 260, the first plate electrode layer 240, and the first insulating layer 220 are sequentially etched to expose the contact pad 200. 280 is formed, and the first insulating layer 220a, the first plate electrode 240a, and the second insulating layer 260a defining the trench 280 that are not etched define the plate electrode pattern 270a. . That is, the storage electrode pattern and the plate electrode pattern are simultaneously formed in one photolithography process and an etching process.

A first dielectric layer 300 for storing electric charges is formed on the entire surface of the plate electrode pattern 270a formed next, that is, on the second insulating layer 260 including the bottom and sidewalls of the trench 280. ) Is deposited and a first storage electrode layer 320 for forming a storage electrode is formed on the first dielectric layer 300. The first dielectric layer 300 may be formed of, for example, tantalum oxide (Ta ₂ 0 ₅ ), nitride oxide (NO), or the like, and may have a thickness of about 50 Angstroms to 60 Angstroms. The first storage electrode layer 320 is formed of a double layer of a titanium nitride layer / polysilicon layer. In this case, the titanium nitride film has a thickness in a range of about 100 angstroms to 200 angstroms, and the polysilicon is formed at about 500 angstroms.

Next, referring to FIG. 5, a first anisotropic etching process is performed to etch the first storage electrode layer 320 and the first dielectric layer 300 to form sidewalls of the plate electrode pattern 270a, that is, the trench 280. Only the sidewalls remain to form the conductive sidewall spacers 320a and 300a for the storage electrodes. Preferably, in the anisotropic front side etching process, a portion of the contact pad 200 may be etched, thereby increasing the surface area of the storage electrode.

Next, in order to electrically connect the storage electrode pad 200 and the storage electrode, the second storage electrode layer 340 may have a sidewall spacer 320a constituting the bottom of the trench 280 and the sidewall thereof, and the plate electrode pattern. It is formed on the upper surface 260a. The second storage electrode layer 340 is formed to have a thickness of about 500 Angstroms.

A planarization insulating layer 360 is formed on the second storage electrode layer 340 to completely fill the trench 280 in a planarization process for separating storage electrodes in a subsequent cell unit. The storage electrodes are then separated cell by cell by chemical mechanical polishing (CMP) or full anisotropic etching (etch back). Then, the planarization insulating film remaining in the trench is removed by isotropic etching.

Next, as shown in FIG. 8, the second plate electrode layer 400 is formed on the second storage electrode 340a separated by the cell unit so as to form a second dielectric layer 380 and completely fill the trench. Thus, a stacked capacitor having a double plate structure is completed.

Stacked capacitors according to the present invention by forming a trench for the storage electrode using the first plate electrode film, unlike the prior art can be used as a storage electrode not only inside the capacitor but also outside the capacitor without using a sacrificial oxide film. It is also possible to further increase the surface area of the capacitor storage electrode by etching a portion of the underlying contact pad during conductive sidewall spacer formation. In addition, the plate electrode pattern and the storage electrode pattern may be simultaneously defined in one photolithography process and an etching process.

In a subsequent process, a wiring process of applying a voltage to the plate electrodes 240a and 400 is performed. First, an interlayer insulating film 420 is formed on the second plate electrode film 400, and the photolithography process and the etching process are performed to expose the first plate electrode 240a and the second plate electrode 400. After the opening is formed, the wiring material is deposited and patterned to complete the metallization 440.

Although the present invention has been described with reference to preferred embodiments, the scope of the present invention is not limited thereto. Rather, various modifications and similar arrangements are included. Therefore, the true scope and spirit of the claims of the present invention should be interpreted broadly to encompass such modifications and similar arrangements.

The stack-type capacitor forming method according to the present invention provides a double upper electrode structure for forming a trench for a storage electrode using the upper electrode instead of the conventional sacrificial oxide film, and a poly that occurs during the lift-off process of the conventional sacrificial oxide film. Lifting of the silicon can be prevented, and the capacity of the capacitor can be increased by using the inside and outside of the cylinder and a part of the storage electrode pad as the storage electrode.

Claims (3)

In forming a stacked capacitor of a semiconductor device, Forming a first insulating film having a storage contact pad formed on the semiconductor substrate; Sequentially forming a second insulating film, a first plate electrode film, and a third insulating film on the storage contact pad and the first insulating film with a film quality for forming trenches for storage electrodes; Etching the third insulating film, the first plate electrode film and the second insulating film to form a trench for the storage electrode exposing the pad, and simultaneously defining a first plate electrode pattern; Forming a first capacitor dielectric layer and a first storage electrode layer inside the trench and on the third insulating layer; Anisotropically etching the first dielectric layer and the first storage electrode layer to leave only the sidewalls of the trench to form sidewall spacers; Forming a second storage electrode film on the resultant; Forming a fourth insulating film on the second storage electrode film to completely fill the trench; Planarization etching the fourth insulating film and the second storage electrode film until the third insulating film appears; Removing the fourth insulating film remaining inside the trench; And, And forming a second dielectric film and a second plate electrode film in the trench. The method of claim 1, Anisotropically etching the first dielectric film and the first storage electrode film to leave only the trench sidewalls to form sidewall spacers, further comprising etching a portion of the exposed storage pad to increase the surface area of the storage electrode. A method of forming a capacitor of a semiconductor device. In a stacked capacitor, A plurality of first plate electrode patterns having sidewalls and upper surfaces formed of a first insulating film, a first plate electrode film, and a second insulating film sequentially formed on the interlayer insulating film at regular intervals, and both side walls of the adjacent first upper electrode pattern; And a plurality of trenches for storage electrodes defined by the interlayer insulating film therebetween; A first capacitor dielectric layer formed on both sidewalls of the trench; Sidewall spacers for first storage electrodes formed on the first capacitor dielectric layers; A second storage electrode layer formed on the first storage electrode sidewall spacer and the trench bottom; A second capacitor dielectric layer formed on the second storage electrode layer and the second insulating layer; And And a second plate electrode film which completely fills the trench formed on the second capacitor dielectric film.