JPH05291526A - Semiconductor memory - Google Patents
Semiconductor memoryInfo
- Publication number
- JPH05291526A JPH05291526A JP4094075A JP9407592A JPH05291526A JP H05291526 A JPH05291526 A JP H05291526A JP 4094075 A JP4094075 A JP 4094075A JP 9407592 A JP9407592 A JP 9407592A JP H05291526 A JPH05291526 A JP H05291526A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- semiconductor memory
- memory device
- oxide film
- bit line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、微細化が可能な半導体
記憶装置に関する。特に、高集積化に好適なな、ダイナ
ミックランダムアクセスメモリで、積層容量型セルに関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device which can be miniaturized. In particular, the present invention relates to a dynamic random access memory suitable for high integration, and relates to a stacked capacitance type cell.
【０００２】[0002]
【従来の技術】ダイナミックランダムアクセスメモリ
は、３年で４倍という集積度の向上を実現しており、既
に、４メガビットの量産体制が整い、１６メガビットの
量産に向けた開発が進行している状況にある。この高集
積化は、素子寸法を小さくすることで達成されてきた
が、微細化に伴う蓄積容量の減少により、信号対雑音比
の低下や、アルファ線の入射による信号反転等の弊害が
顕在化し、信頼性の維持が困難になってきている。そこ
で、現在は、蓄積容量を増加させることのできるメモリ
セルとして、蓄積容量の一部を、スイッチ用トランジス
タや素子分離酸化膜の上に積み上げた、積層容量型セル
や、基板に深い孔を掘り、その側壁に電荷蓄積用キャパ
シタを形成した、トレンチ型セルが、４メガビット以降
のメモリセルの主流になっている。2. Description of the Related Art A dynamic random access memory has achieved a fourfold increase in the degree of integration in three years, and a mass production system for 4 megabits has already been set up, and development for mass production of 16 megabits is in progress. There is a situation. This high degree of integration has been achieved by reducing the element size.However, due to the decrease in storage capacity due to miniaturization, the signal-to-noise ratio declines, and adverse effects such as signal inversion due to alpha ray incidence become apparent. , Maintaining reliability is becoming difficult. Therefore, at present, as a memory cell that can increase the storage capacity, a part of the storage capacity is stacked on a switching transistor or an element isolation oxide film, or a stacked capacitance type cell or a deep hole is dug in a substrate. A trench type cell having a charge storage capacitor formed on its side wall has become the mainstream of memory cells of 4 megabits or more.
【０００３】しかし、メモリセル面積がこれまでのトレ
ンドに従って、前世代の１／３で縮小し続けると、これ
らの立体化セルを使用しても、メモリ動作に必要な蓄積
容量を得ることは困難な状況にある。However, if the memory cell area continues to shrink by 1/3 of the previous generation according to the trend so far, it is difficult to obtain the storage capacity necessary for the memory operation even if these three-dimensional cells are used. There is a situation.
【０００４】図２は、従来の積層容量型セルの断面図、
特に、王冠型と呼ばれている、筒状電極（２１）の内壁
および外壁を利用した、積層容量型セルである。この構
造のメモリセルは、特開昭６２−４８０６２および特開
昭６２−１２８１６８に記述されている。この構造の特
徴は、ワード線（８）とビット線（１２）の上に蓄積電
極（２１）を設け、さらに、この蓄積電極（２１）を筒
状にして、その内壁だけでなく外壁をも利用して、キャ
パシタの有効面積を増加させている。また、特開平１−
１７９４４９に記述されている、ビット線（１２）の上
に蓄積電極（２１）を設ける構造により、蓄積電極の領
域を、最小加工寸法の範囲内で、最大限に大きくするこ
とができる。FIG. 2 is a sectional view of a conventional stacked capacitive cell,
In particular, it is a laminated capacitance type cell which is called a crown type and utilizes the inner wall and the outer wall of the cylindrical electrode (21). Memory cells of this structure are described in JP-A-62-48062 and JP-A-62-128168. The feature of this structure is that a storage electrode (21) is provided on the word line (8) and the bit line (12), and the storage electrode (21) is formed into a cylindrical shape so that not only its inner wall but also its outer wall is formed. Utilizing it to increase the effective area of the capacitor. In addition, Japanese Patent Laid-Open No. 1-
Due to the structure described in 179449 in which the storage electrode (21) is provided on the bit line (12), the area of the storage electrode can be maximized within the range of the minimum processing size.
【０００５】ここで、１は半導体基板、２は素子間分離
酸化膜、３は拡散層、７はゲート酸化膜、８はゲート電
極、９は酸化膜、１２はビット線、２１は蓄積電極、２
２はキャパシタ絶縁膜、２３はプレート電極、２４は層
間絶縁膜、２５は配線層である。Here, 1 is a semiconductor substrate, 2 is an element isolation oxide film, 3 is a diffusion layer, 7 is a gate oxide film, 8 is a gate electrode, 9 is an oxide film, 12 is a bit line, 21 is a storage electrode, Two
Reference numeral 2 is a capacitor insulating film, 23 is a plate electrode, 24 is an interlayer insulating film, and 25 is a wiring layer.
【０００６】図３には、特開昭５８−３２６０に記述さ
れている構造を基に、４メガビットへの適用を可能にし
た、トレンチキャパシタ型セルである。特に、この構造
では、トレンチの側壁を酸化膜（９）で被い、隣接トレ
ンチ間のリーク電流を防止し、また、アルファ線の耐性
を高めた構造になっている。FIG. 3 shows a trench capacitor type cell which can be applied to 4 megabits based on the structure described in JP-A-58-3260. In particular, in this structure, the side wall of the trench is covered with the oxide film (9) to prevent the leak current between the adjacent trenches and to improve the resistance to alpha rays.
【０００７】ここで、１は半導体基板、２は素子間分離
酸化膜、３は拡散層、７はゲート酸化膜、８はゲート電
極、９は酸化膜、１２はビット線、２１は蓄積電極、２
２はキャパシタ絶縁膜、２３はプレート電極、２４は層
間絶縁膜、２５は配線層である。Here, 1 is a semiconductor substrate, 2 is an element isolation oxide film, 3 is a diffusion layer, 7 is a gate oxide film, 8 is a gate electrode, 9 is an oxide film, 12 is a bit line, 21 is a storage electrode, Two
Reference numeral 2 is a capacitor insulating film, 23 is a plate electrode, 24 is an interlayer insulating film, and 25 is a wiring layer.
【０００８】[0008]
【発明が解決しようとする課題】上述したように、積層
容量型セルやトレンチ型セルの採用により、蓄積容量が
増加し、この結果、微細なセルでもメモリ動作に十分な
蓄積容量が確保できるようになった。しかし、既に述べ
たように、この立体型セルを用いても、蓄積容量の確保
は困難になりつつある。As described above, the use of the stacked capacitance type cell or the trench type cell increases the storage capacity, and as a result, it is possible to secure a sufficient storage capacity for memory operation even in a fine cell. Became. However, as described above, it is becoming difficult to secure the storage capacity even if this three-dimensional cell is used.
【０００９】図２に示した王冠型電極の積層容量型セル
は、ここでは、詳細には述べないが、この筒状蓄積電極
を得るために、複雑な工程を必要とする。すなわち、ワ
ード線（８）とビット線（１２）が形成されている基板
表面上に絶縁膜（図２には図示されていない）を堆積
し、これに穴を開けて蓄積電極（２１）を埋め込んだ後
に、この絶縁膜を除去して、蓄積電極（２１）の外壁を
露出させるという工程が必要である。しかし、下地のワ
ード線（８）やビット線（１２）を被う絶縁膜（９）に
影響を与えることなく、この絶縁膜だけを除去するのは
困難である。また、蓄積容量を増加させるために、蓄積
電極を高くすると、絶縁膜の除去が難しくなるだけでは
なく、メモリ部の段さが高くなることで、周辺回路との
電気的接続も難しくなる。また、特開平２−２２６７６
１に示されているように、筒状電極を多重構造にする
と、蓄積容量は増加するが、製造工程はさらに複雑化す
る。また、微細化に伴って、筒状電極の間隙が狭くなる
ために、キャパシタ絶縁膜やプレート電極を埋めること
ができないと言う問題が生じる。Although not described in detail here, the laminated capacitance type cell of the crown type electrode shown in FIG. 2 requires a complicated process to obtain this cylindrical storage electrode. That is, an insulating film (not shown in FIG. 2) is deposited on the surface of the substrate where the word line (8) and the bit line (12) are formed, and a hole is formed in this to form a storage electrode (21). After the burying, a step of removing the insulating film to expose the outer wall of the storage electrode (21) is required. However, it is difficult to remove only this insulating film without affecting the insulating film (9) covering the underlying word line (8) and bit line (12). Further, if the storage electrode is raised to increase the storage capacitance, it becomes difficult not only to remove the insulating film, but also to increase the step of the memory portion, which makes electrical connection to the peripheral circuit difficult. In addition, JP-A-2-22676
As shown in FIG. 1, when the cylindrical electrode has a multiple structure, the storage capacitance increases, but the manufacturing process becomes more complicated. Further, with the miniaturization, the gap between the cylindrical electrodes becomes narrower, which causes a problem that the capacitor insulating film and the plate electrode cannot be filled.
【００１０】図３に示したトレンチ型セルも、微細化に
際して大きな課題がある。このセルの特徴は、トレンチ
側壁を被う酸化膜（９）であるが、このため、基板に掘
ったトレンチが狭められ、さらに、その内側に蓄積電極
（２１）を形成するために、トレンチキャパシタとして
利用できる有効面積は、最初に基板に掘ったトレンチの
約半分にまで小さくなる。また、トレンチの形成はゲー
ト酸化膜の成長や、ゲート電極形成の前に行うため、キ
ャパシタ絶縁膜（２２）には、耐熱性の高い、ＳｉＯ2
系の膜を用いなければならない。しかし、この絶縁膜は
３ｎｍ程度の膜厚でトンネルリーク電流が顕著になるた
め、それ以上の薄膜化はできない。そのため、蓄積容量
を増加させるためには、トレンチを深く掘らなければな
らず、加工技術の負担が大きい。The trench type cell shown in FIG. 3 also has a big problem in miniaturization. The feature of this cell is the oxide film (9) covering the side wall of the trench, which narrows the trench dug in the substrate and further forms the storage electrode (21) inside the trench capacitor. Available area is reduced to about half of the trench originally drilled in the substrate. Further, since the trench is formed before the growth of the gate oxide film and the formation of the gate electrode, the capacitor insulating film (22) is formed of SiO 2 having high heat resistance.
A system membrane must be used. However, since the tunnel leak current becomes remarkable at a film thickness of about 3 nm, this insulating film cannot be further thinned. Therefore, in order to increase the storage capacity, it is necessary to dig a trench deeply, which imposes a heavy burden on the processing technique.
【００１１】また、蓄積容量の確保とともに、スイッチ
用トランジスタを安定に動作させることも難しくなって
きている。これは、設計寸法の縮小に伴って、ゲート長
が短くなり、いわゆる短チャネル効果によって、常に同
通した状態になってしまうからである。この短チャネル
効果に対して、これまでは、拡散層（３）の浅接合化や
基板濃度の上昇で対処してきたが、浅接合化にはプロセ
スで決まる限界があり、また、基板濃度の上昇はしきい
電圧の増加をもたらす。Further, it is becoming difficult to stably operate the switching transistor as well as to secure the storage capacity. This is because as the design size is reduced, the gate length becomes shorter, and the so-called short channel effect always keeps them in the same state. Up to now, the short channel effect has been dealt with by making the diffusion layer (3) into a shallow junction or increasing the substrate concentration, but there is a limit to the shallow junction formation determined by the process, and the increase in the substrate concentration. It causes an increase in the threshold voltage.
【００１２】従って、本発明の目的とするところは、微
細化を続けるメモリセルの課題のひとつである、蓄積容
量の減少を防ぎ、かつ、製造工程を簡略化することで、
ギガビットのクラスの容量を有するＤＲＡＭ型の半導体
記憶装置を提供することにある。Therefore, an object of the present invention is to prevent a decrease in storage capacity, which is one of the problems of memory cells that continue to be miniaturized, and to simplify the manufacturing process.
It is an object of the present invention to provide a DRAM type semiconductor memory device having a gigabit class capacity.
【００１３】[0013]
【課題を解決するための手段】このように、立体型セル
にも大きな課題があり、蓄積容量の増加は容易ではな
い。上述したように、現在は１６メガビットの量産化に
向けた技術開発が進められているが、さらに、６４メガ
ビット、２５６メガビットを越えて、２０００年には登
場すると考えられるギガビットメモリを実現するために
は、新たな工夫が必要である。As described above, the three-dimensional cell also has a big problem, and it is not easy to increase the storage capacity. As mentioned above, technical development for mass production of 16 megabits is currently in progress, but in order to realize a gigabit memory that is expected to appear in 2000, beyond 64 megabits and 256 megabits. Requires new innovations.
【００１４】トレンチ型セルは、トレンチの作成が最初
であるために、トレンチキャパシタの平面的な大きさに
制限がある。また、上述したような、トレンチ側壁を酸
化膜で被う構造は、キャパシタ有効面積が小さくなる欠
点がある。一方、積層容量型セルは、蓄積電極を最大限
に拡張でき、さらに、キャパシタ絶縁膜に高誘電率の絶
縁膜が使えるという特徴がある。In the trench type cell, since the trench is formed first, the planar size of the trench capacitor is limited. Further, the structure in which the sidewall of the trench is covered with the oxide film as described above has a drawback that the effective area of the capacitor is reduced. On the other hand, the laminated capacitive cell is characterized in that the storage electrode can be expanded to the maximum extent and that a high dielectric constant insulating film can be used as the capacitor insulating film.
【００１５】このような、積層容量型セルの特徴をさら
に発展させることのできるのが、図１に示した本発明の
半導体記憶装置である。このセルでは、ワード線（８）
とビット線（１２）が形成された基板上に、酸化膜を堆
積して、これにトレンチキャパシタを形成する構造にな
っている。すなわち、王冠型の蓄積電極形成とは異な
り、トレンチを掘った酸化膜を除去する工程が省略でき
る。しかも、ビット線の上部に配線（１６）を置くこと
で、ビット線と周辺回路との接続や、ワード線の選択を
行うワード母線に用いることができる。ワード母線は、
ワード線数本に対して一本でよいため、ワード線に比べ
て寸法はゆるやかである。さらに、ワード線（８）やビ
ット線（１２）を被う絶縁膜と、層間絶縁膜（１１、１
５、１７、２０）の種類を変え、エッチングの選択比の
違いで、自己整合プロセスを行う。It is the semiconductor memory device of the present invention shown in FIG. 1 that can further develop the characteristics of such a stacked capacitance type cell. In this cell, the word line (8)
An oxide film is deposited on the substrate on which the bit line (12) is formed and a trench capacitor is formed on the oxide film. That is, unlike the formation of the crown type storage electrode, the step of removing the oxide film dug in the trench can be omitted. Moreover, by arranging the wiring (16) on the bit line, it can be used as a word bus for connecting the bit line and the peripheral circuit and selecting the word line. The word bus is
Since only one word line is required for several word lines, the size is gentler than that of word lines. Furthermore, an insulating film covering the word line (8) and the bit line (12) and an interlayer insulating film (11, 1)
5, 17, 20), and the self-alignment process is performed depending on the etching selectivity.
【００１６】スイッチ用トランジスタの短チャネル化に
対しては、図１に示したように、溝型のゲート構造を採
用することで対処した。溝型の構造は、溝の深さに応じ
て、実効的にゲート長の長いトランジスタを作ることが
できる。溝型ゲートのトランジスタでは、溝の側壁を伝
わるリーク電流が懸念されるので、素子分離にはトレン
チ素子分離（２）を用いた。The shortening of the channel of the switching transistor has been dealt with by adopting a groove type gate structure as shown in FIG. The groove type structure can effectively form a transistor having a long gate length according to the depth of the groove. In the trench gate type transistor, the trench element isolation (2) was used for the element isolation because there is a concern about the leak current transmitted through the sidewall of the groove.
【００１７】[0017]
【作用】本発明のように、基板上にトレンチを掘る構造
にすると、王冠型電極と異なり、トレンチを掘った酸化
膜を除去するという、複雑な工程を削除することができ
る。また、王冠型では、この酸化膜を除去して、キャパ
シタ絶縁膜（図２の２２）、プレート電極（図２の２
３）を形成した後に、再び酸化膜（図２の２４）を堆積
させて平坦化させていた。しかし、メモリセル部と周辺
回路部の段さを、この平坦化工程だけで低減するのは困
難である。一方、本発明では、図１に示したように、ビ
ット線（１２）上の配線（１６）を形成した後で、基板
全体を絶縁膜（１９、２０）で平坦化するために、メモ
リセル部と周辺回路部との段さはほとんどない。また、
配線層（１６）が、メモリセル部ではビット線と周辺回
路との接続、周辺回路では、素子間の接続に使うことが
できるので、基板上のトレンチが深くなっても、最上部
から基板に至るまでの、深くかつ寸法の小さなコンタク
トを形成する必要がなくなる。さらには、ワード線
（８）やビット線（１２）を被う絶縁膜と、層間絶縁膜
（１１、１５、１７、２０）の種類を変えると、エッチ
ングの選択比の違いが効果的に利用できるようになるの
で、自己整合プロセスが使え、セル面積の縮小が可能と
なる。In the structure of digging a trench on a substrate as in the present invention, unlike the crown type electrode, a complicated process of removing an oxide film digging a trench can be eliminated. In the crown type, the oxide film is removed to remove the capacitor insulating film (22 in FIG. 2) and the plate electrode (2 in FIG. 2).
After forming 3), an oxide film (24 in FIG. 2) was deposited again to planarize. However, it is difficult to reduce the level of the memory cell section and the peripheral circuit section only by this flattening step. On the other hand, according to the present invention, as shown in FIG. 1, after forming the wiring (16) on the bit line (12), the memory cell is formed by planarizing the entire substrate with the insulating films (19, 20). There is almost no step between the section and the peripheral circuit section. Also,
Since the wiring layer (16) can be used for connection between the bit line and the peripheral circuit in the memory cell section and for connection between elements in the peripheral circuit, even if the trench on the substrate becomes deep, It is no longer necessary to form deep and small contacts. Furthermore, when the types of the insulating film covering the word lines (8) and the bit lines (12) and the types of the interlayer insulating films (11, 15, 17, 20) are changed, the difference in etching selection ratio is effectively used. As a result, the self-alignment process can be used and the cell area can be reduced.
【００１８】本発明のその他の目的と特徴は、以下の実
施例から明らかとなろう。Other objects and features of the present invention will be apparent from the following examples.
【００１９】[0019]
【実施例】本発明の実施例を図４乃至図１６を用いて説
明する。EXAMPLE An example of the present invention will be described with reference to FIGS.
【００２０】まず、図４に示したように、半導体基板
（１）に素子間分離酸化膜（２）を形成する。本実施例
では、上述したように、トランジスタとして溝型ゲート
構造を用いるので、公知のトレンチ素子分離法で、基板
（１）に対して垂直な酸化膜面ができるようにした。具
体的には、基板（１）に溝を掘り、これを酸化膜で埋め
戻す方法を採用した。素子間分離酸化膜（２）の膜厚
は、０．３μｍ程度に設定した。素子間分離酸化膜
（２）を形成した後に、表面全体に、予め拡散層（３）
領域を形成する。本実施例では、メモリセル領域だけに
注目しているが、周辺回路については、導電型の異なる
トランジスタを形成するので、拡散層（３）にも、種類
の異なるものが作られる。拡散層（３）の形成には、公
知のイオン打ち込み法を用いた。深さは、０．１μｍ程
度である。尚、この拡散層（３）はその後、溝で分離さ
れることによりＤＲＡＭセルのスイッチング用ＭＯＳト
ランジスタのソース・ドレイン領域を構成するものであ
る。First, as shown in FIG. 4, an element isolation oxide film (2) is formed on a semiconductor substrate (1). In the present embodiment, as described above, since the groove type gate structure is used as the transistor, a known trench element isolation method is used to form an oxide film surface perpendicular to the substrate (1). Specifically, a method of digging a groove in the substrate (1) and filling it with an oxide film was adopted. The film thickness of the element isolation oxide film (2) was set to about 0.3 μm. After forming the element isolation oxide film (2), a diffusion layer (3) is formed on the entire surface in advance.
Form an area. In this embodiment, attention is paid only to the memory cell region, but since the transistors having different conductivity types are formed in the peripheral circuit, different types of diffusion layers (3) can be made. A well-known ion implantation method was used for forming the diffusion layer (3). The depth is about 0.1 μm. The diffusion layer (3) is then separated by a groove to form the source / drain regions of the switching MOS transistor of the DRAM cell.
【００２１】次に、図５に示したように、イオン打ち込
みに伴う表面の汚染などを除去し、この表面に酸化膜
（４）を、公知の気層成長法で堆積させる。膜厚は０．
１μｍから０．３μｍである。この酸化膜に、溝型ゲー
トを掘るための穴を開ける。この穴の開口には、公知の
光リソグラフィを用いた。開口部の大きさは０．２μｍ
から０．３μｍである。開口後、さらに表面全体に０．
０５μｍの酸化膜（５）を堆積して、これを公知の異方
性エッチングで全面エッチすると、表面に堆積した酸化
膜（４）の側壁にのみ酸化膜（５）が残る。Next, as shown in FIG. 5, surface contamination and the like due to ion implantation are removed, and an oxide film (4) is deposited on this surface by a known vapor deposition method. The film thickness is 0.
It is from 1 μm to 0.3 μm. A hole is formed in this oxide film for digging the trench gate. Known optical lithography was used for the opening of this hole. The size of the opening is 0.2 μm
To 0.3 μm. After opening, 0.
When an oxide film (5) with a thickness of 05 μm is deposited and the entire surface is etched by known anisotropic etching, the oxide film (5) remains only on the side wall of the oxide film (4) deposited on the surface.
【００２２】次に、図６に示したように、この酸化膜
（４、５）をマスクにして、基板に溝（６）を掘り、こ
の溝（６）で拡散層（３）を分離する。溝の深さは、
０．２μｍとした。図５に示した側壁酸化膜（５）の役
割は、光リソグラフィできまる寸法より小さな溝を、自
己整合で開けることにある。また、図６に示したよう
に、この側壁酸化膜（５）があるために、溝と表面のコ
ーナー部がテーパー状になり、その後のゲート電極形成
が容易になる。Next, as shown in FIG. 6, the oxide film (4, 5) is used as a mask to dig a groove (6) in the substrate, and the groove (6) separates the diffusion layer (3). .. The depth of the groove is
It was 0.2 μm. The role of the sidewall oxide film (5) shown in FIG. 5 is to self-align a groove smaller than a size that can be formed by photolithography. Further, as shown in FIG. 6, since the sidewall oxide film (5) is provided, the groove and the corner portion of the surface are tapered, which facilitates the subsequent gate electrode formation.
【００２３】次に、図７に示したように、溝の表面にゲ
ート絶縁膜（７）を成長させ、さらに、ゲート電極
（８）を堆積し、このゲート電極（８）を、その上に堆
積した窒化膜（９）をマスクにしてパターニングする。
本実施例では、ゲート絶縁膜（７）として薄膜化の可能
なＴａ2Ｏ5膜を使用して、酸化膜換算で３ｎｍを得た。
また、ゲート電極には、タングステンを用いた。ゲート
電極の寸法は、０．２μｍである。タングステンは、従
来の多結晶シリコンと比べて、抵抗が１／５０以下なの
で、ゲート抵抗による性能の劣化を防ぐことができる。Next, as shown in FIG. 7, a gate insulating film (7) is grown on the surface of the groove, and a gate electrode (8) is further deposited on the gate insulating film (8). Patterning is performed using the deposited nitride film (9) as a mask.
In this example, a Ta 2 O 5 film capable of being thinned was used as the gate insulating film (7), and a thickness of 3 nm was obtained in terms of oxide film.
Further, tungsten was used for the gate electrode. The size of the gate electrode is 0.2 μm. Since tungsten has a resistance of 1/50 or less as compared with conventional polycrystalline silicon, it is possible to prevent performance deterioration due to gate resistance.
【００２４】さらに、図８に示したように、ゲート電極
（８）の表面に０．０５から０．１μｍの窒化膜（１
０）を堆積し、これを公知の異方性エッチで全面エッチ
する。その結果、ゲート電極（８）の側壁に側壁窒化膜
（１０）が残る。さらに、この窒化膜をマスクにして、
酸化膜と窒化膜の選択比を利用したエッチング法で、ワ
ード電極（８）の下にある酸化膜（４）をエッチングし
て基板の拡散層表面を露出させる。Further, as shown in FIG. 8, a 0.05 to 0.1 μm thick nitride film (1) is formed on the surface of the gate electrode (8).
0) is deposited and the whole surface is etched by a known anisotropic etching. As a result, the sidewall nitride film (10) remains on the sidewall of the gate electrode (8). Furthermore, using this nitride film as a mask,
The surface of the diffusion layer of the substrate is exposed by etching the oxide film (4) under the word electrode (8) by an etching method using the selection ratio of the oxide film and the nitride film.
【００２５】次に、図９に示したように、基板表面全体
に酸化膜を堆積して、公知のエッチバック法を用いて平
坦化する。その結果、ワード線の表面を被う窒化膜
（９）が露出するとともに、基板表面が平坦化する。Next, as shown in FIG. 9, an oxide film is deposited on the entire surface of the substrate and flattened by a known etchback method. As a result, the nitride film (9) covering the surface of the word line is exposed and the substrate surface is flattened.
【００２６】次に、図１０に示したように、隣接するワ
ード線間の酸化膜（１１）だけを除去して、ビット線
（１２）が基板の拡散層と接する領域を開口する。この
上に、ビット線（１２）となるタングステンを、公知の
スパッタ法もしくは気層成長法で堆積する。膜厚は、
０．１μｍ程度にした。タングステンのビット線（１
３）も、ワード線と同様に、表面に窒化膜（１３）を堆
積して、これをマスクに加工し、さらに、側壁窒化膜
（１４）で被う。Next, as shown in FIG. 10, only the oxide film (11) between the adjacent word lines is removed to open a region where the bit line (12) is in contact with the diffusion layer of the substrate. On this, tungsten to be the bit line (12) is deposited by a known sputtering method or vapor deposition method. The film thickness is
The thickness is about 0.1 μm. Tungsten bit line (1
Also in 3), similarly to the word line, a nitride film (13) is deposited on the surface, this is processed as a mask, and the sidewall nitride film (14) is further covered.
【００２７】さらに、図１１に示したように、基板上に
酸化膜（１５）を堆積して平坦化する。そして、ここで
は示していないが、光リソグラフィを用いて、周辺回路
のゲート電極（ワード線と同じ層で形成してある）や、
基板、およびビット線に達するコンタクトを開口する。
そして、配線（１６）を用いて接続する。さらに、その
配線の上に酸化膜（１７）を堆積して平坦化する。Further, as shown in FIG. 11, an oxide film (15) is deposited on the substrate and flattened. Although not shown here, using photolithography, the gate electrode of the peripheral circuit (formed in the same layer as the word line),
Open contacts to the substrate and bit lines.
Then, the wiring (16) is used for connection. Further, an oxide film (17) is deposited on the wiring and flattened.
【００２８】次に、図１２に示したように、基板に達す
る蓄積容量部のコンタクトを開口する。この際にも光リ
ソグラフィを用いてパターン形成を行う。この際、ワー
ド線（８）もビット線（１２）も表面は窒化膜（９、１
３）で被われているので、コンタクトが図のようにワー
ド線に掛かっても、ワード線が露出する心配はない。次
に、ここで開口したコンタクト孔に、不純物を含んだ多
結晶シリコン（１８）を埋めて、拡散層を上に持ち上げ
る。Next, as shown in FIG. 12, the contact of the storage capacitor portion reaching the substrate is opened. Also in this case, pattern formation is performed using optical lithography. At this time, the surface of both the word line (8) and the bit line (12) is nitrided (9, 1).
Since it is covered in 3), there is no concern that the word line will be exposed even if the contact hangs on the word line as shown in the figure. Next, the contact hole opened here is filled with polycrystalline silicon (18) containing impurities, and the diffusion layer is lifted up.
【００２９】次に、図１３に示したように、この表面
に、窒化膜（１９）と酸化膜（２０）を堆積して、トレ
ンチを掘る。窒化膜（１９）は酸化膜にトレンチを掘る
際の下地となり、配線層などが露出するのを防ぐ。堆積
した酸化膜（２０）は１μｍである。このトレンチの加
工で、拡散層を持ち上げた多結晶シリコン（１８）の表
面が露出する。Next, as shown in FIG. 13, a nitride film (19) and an oxide film (20) are deposited on this surface and trenches are formed. The nitride film (19) serves as a base when trenches are formed in the oxide film and prevents the wiring layer and the like from being exposed. The deposited oxide film (20) is 1 μm. By processing the trench, the surface of the polycrystalline silicon (18) with the diffusion layer lifted is exposed.
【００３０】そして次に、図１４に示したように、トレ
ンチの側壁に蓄積電極（２１）を形成する。ここではそ
の詳細は図示していないが、工程は概略次の通りであ
る。まず、蓄積電極となるタングステンを０．０５μｍ
程度堆積する。この段階ではタングステンはつながって
いるので、この表面に有機膜を塗布し、全面エッチを行
う。その結果、トレンチの内部は有機膜で埋められる
が、酸化膜（２０）の表面にあるタングステンが露出す
る。そして、露出したタングステンをエッチングする
と、蓄積電極が分離される。このタングステンの表面に
Ｔａ2Ｏ5膜を、公知の気層成長法で堆積する。膜厚は、
酸化膜換算で２ｎｍである。さらに、プレート電極（２
３）となるタングステンやＴｉＮを堆積する。本実施例
で、蓄積電極（２１）にタングステンを用いたのは、自
然酸化膜に影響されないＴａ2Ｏ5膜を形成するためであ
り、従来の多結晶シリコンでも構わないのは言うまでも
ない。しかしながら、この場合には、多結晶シリコン表
面の自然酸化膜の影響で、キャパシタ絶縁膜は酸化膜換
算で３ｎｍ程度になる。Then, as shown in FIG. 14, a storage electrode (21) is formed on the side wall of the trench. Although the details are not shown here, the steps are roughly as follows. First, the tungsten to be the storage electrode is 0.05 μm
Deposit to a degree. Since tungsten is connected at this stage, an organic film is applied to this surface and the entire surface is etched. As a result, the inside of the trench is filled with the organic film, but the tungsten on the surface of the oxide film (20) is exposed. Then, when the exposed tungsten is etched, the storage electrode is separated. A Ta 2 O 5 film is deposited on the surface of this tungsten by a known vapor deposition method. The film thickness is
It is 2 nm in terms of oxide film. In addition, the plate electrode (2
3) Tungsten and TiN, which will be 3), are deposited. In the present embodiment, tungsten is used for the storage electrode (21) in order to form a Ta 2 O 5 film that is not affected by the natural oxide film, and it goes without saying that conventional polycrystalline silicon may be used. However, in this case, due to the influence of the natural oxide film on the surface of the polycrystalline silicon, the capacitor insulating film becomes about 3 nm in terms of oxide film.
【００３１】最後に、図１５に示したように、層間酸化
膜（２４）、最上層の配線（２５）を形成して、図１に
示した本発明の半導体記憶装置が完成する。配線（２
５）アルミを用いた。Finally, as shown in FIG. 15, the interlayer oxide film (24) and the uppermost wiring (25) are formed to complete the semiconductor memory device of the present invention shown in FIG. Wiring (2
5) Aluminum was used.
【００３２】図１６には、本発明の半導体記憶装置の平
面図を示した。ワード線（３２）とビット線（３４）の
上に蓄積電極（３７）を配置するために、トランジスタ
のチャネル（溝型）や、拡散層が形成される活性領域
（３０）は、ワード線（３２）とビット線（３４）の両
方に対して傾いて配置されている。図には簡略化のため
に、２つの蓄積電極だけを示したが、このように、最小
寸法で配置することができるために、蓄積容量が増加す
る。FIG. 16 shows a plan view of the semiconductor memory device of the present invention. In order to dispose the storage electrode (37) on the word line (32) and the bit line (34), the channel (groove type) of the transistor and the active region (30) where the diffusion layer is formed are formed in the word line ( 32) and the bit line (34) are inclined. Although only two storage electrodes are shown in the figure for simplification, the storage capacity is increased because the storage electrodes can be arranged with the minimum size.
【００３３】ここで、３３はビット線と拡散層とのコン
タクト、３６は蓄積電極と拡散層とのコンタクトであ
る。３５はビット線の上にあり、かつ蓄積電極の下にあ
る配線である。Here, 33 is a contact between the bit line and the diffusion layer, and 36 is a contact between the storage electrode and the diffusion layer. Reference numeral 35 is a wiring above the bit line and below the storage electrode.
【００３４】[0034]
【発明の効果】以上述べてきたように、本発明の、基板
上にトレンチを形成した積層容量型セルを用いると、小
さなセル面積のなかで、メモリ動作に必要な蓄積容量を
確保できる。例えば、０．２μｍ以下の寸法を必要とす
る１ギガビットＤＲＡＭでは、これまでのトレンドに従
えば、セル面積は０．２μｍ2程度になるが、酸化膜換
算で２ｎｍのＴａ2Ｏ5膜を使用すると、トレンチの深さ
は０．９μｍでよい。トレンチの寸法は、短辺が０．２
５μｍ、長辺が０．５μｍになるため、平均的なアスペ
クト比は、２．５程度と小さい。さらにセル面積が縮小
されても、Ｔａ2Ｏ5膜の薄膜化によって、アスペクト比
を１０以下に保ちながら、蓄積容量が確保できる。ま
た、蓄積電極の下に配線層を設けることで、従来は高段
差のある表面上で行っていた配線の一部を簡略化でき
る。As described above, when the laminated capacitance type cell of the present invention in which the trench is formed on the substrate is used, the storage capacitance required for the memory operation can be secured in a small cell area. For example, in a 1 Gbit DRAM that requires a dimension of 0.2 μm or less, according to the trend so far, the cell area is about 0.2 μm 2 , but a Ta 2 O 5 film of 2 nm in terms of oxide film is used. Then, the depth of the trench may be 0.9 μm. The length of the trench is 0.2 on the short side.
Since the length is 5 μm and the long side is 0.5 μm, the average aspect ratio is as small as about 2.5. Even if the cell area is further reduced, the Ta 2 O 5 film can be thinned to secure the storage capacity while keeping the aspect ratio at 10 or less. Further, by providing the wiring layer under the storage electrode, it is possible to simplify a part of the wiring conventionally performed on the surface having a high step.
【００３５】このように、本発明の半導体記憶装置は、
セル面積を縮小しても十分な蓄積容量が確保でき、さら
に、製造が容易になるので、ギガビットクラスのＤＲＡ
Ｍが可能になる。As described above, the semiconductor memory device of the present invention is
Even if the cell area is reduced, a sufficient storage capacity can be secured, and manufacturing is easy.
M becomes possible.
【図１】本発明の基板上トレンチキャパシタを有する半
導体記憶装置である。FIG. 1 is a semiconductor memory device having a trench capacitor on a substrate of the present invention.
【図２】従来の王冠型キャパシタを有する半導体記憶装
置である。FIG. 2 is a semiconductor memory device having a conventional crown capacitor.
【図３】従来のトレンチ型キャパシタを有する半導体記
憶装置である。FIG. 3 is a semiconductor memory device having a conventional trench type capacitor.
【図４】本発明の一実施例の半導体記憶装置の製造工程
を示す断面図である。FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.
【図５】本発明の一実施例の半導体記憶装置の製造工程
を示す断面図である。FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.
【図６】本発明の一実施例の半導体記憶装置の製造工程
を示す断面図である。FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.
【図７】本発明の一実施例の半導体記憶装置の製造工程
を示す断面図である。FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.
【図８】本発明の一実施例の半導体記憶装置の製造工程
を示す断面図である。FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.
【図９】本発明の一実施例の半導体記憶装置の製造工程
を示す断面図である。FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.
【図１０】本発明の一実施例の半導体記憶装置の製造工
程を示す断面図である。FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.
【図１１】本発明の一実施例の半導体記憶装置の製造工
程を示す断面図である。FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.
【図１２】本発明の一実施例の半導体記憶装置の製造工
程を示す断面図である。FIG. 12 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.
【図１３】本発明の一実施例の半導体記憶装置の製造工
程を示す断面図である。FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.
【図１４】本発明の一実施例の半導体記憶装置の製造工
程を示す断面図である。FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.
【図１５】本発明の一実施例の半導体記憶装置の製造工
程を示す断面図である。FIG. 15 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the embodiment of the present invention.
【図１６】本発明の一実施例の半導体記憶装置の平面図
である。FIG. 16 is a plan view of a semiconductor memory device according to an embodiment of the present invention.
１−半導体基板、２−素子間分離酸化膜、３−拡散層、
４−酸化膜、５−側壁酸化膜、６−溝ゲート、７−ゲー
ト酸化膜、８−ゲート電極、９−窒化膜、１０−側壁窒
化膜、１１−層間酸化膜、１２−ビット線、１３−窒化
膜、１４−側壁窒化膜、１５−層間酸化膜、１６−配
線、１７−層間酸化膜、１８−多結晶シリコン、１９−
窒化膜、２０−層間酸化膜、２１−蓄積電極、２２−キ
ャパシタ絶縁膜、２３−プレート電極、２４−層間酸化
膜、２５−配線、３０−活性領域パターン、３１−溝形
成パターン、３２−ワード線パターン、３３−ビット線
コンタクトパターン、３４−ビット線、３５−配線、３
６−蓄積容量コンタクトパターン、３７−蓄積電極パタ
ーン。1-semiconductor substrate, 2-element isolation oxide film, 3-diffusion layer,
4-oxide film, 5-sidewall oxide film, 6-groove gate, 7-gate oxide film, 8-gate electrode, 9-nitride film, 10-sidewall nitride film, 11-interlayer oxide film, 12-bit line, 13 -Nitride film, 14-Sidewall nitride film, 15-Interlayer oxide film, 16-Wiring, 17-Interlayer oxide film, 18-Polycrystalline silicon, 19-
Nitride film, 20-interlayer oxide film, 21-storage electrode, 22-capacitor insulating film, 23-plate electrode, 24-interlayer oxide film, 25-wiring, 30-active region pattern, 31-groove formation pattern, 32-word Line pattern, 33-bit line contact pattern, 34-bit line, 35-wiring, 3
6-storage capacitor contact pattern, 37-storage electrode pattern.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 伊藤 清男 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 大路 譲 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所中央研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyoo Ito 1-280, Higashi-Kengokubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Yuzuru Ohji 1-280, Higashi-Kengokubo, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory
Claims (7)
荷蓄積用キャパシタより構成され、該電荷蓄積用キャパ
シタを基板上に積み上げた積層容量型に構成するととも
に筒状に構成され、該筒状キャパシタ電極がビット線の
上層に形成され、かつ該筒状キャパシタ電極の内面によ
って蓄積容量部が実質的に形成されてなることを特徴と
する、半導体記憶装置。1. A memory cell is composed of a switching transistor and a charge storage capacitor, is of a laminated capacitance type in which the charge storage capacitor is stacked on a substrate, and has a cylindrical shape, and the cylindrical capacitor electrode is A semiconductor memory device, characterized in that it is formed in an upper layer of a bit line, and that a storage capacitor portion is substantially formed by an inner surface of the cylindrical capacitor electrode.
めのワード線と、かつ、上記電荷蓄積用キャパシタに電
荷を供給するためのビット線の上層で、さらに、上記電
荷蓄積用キャパシタの一方の電極であるプレート電極の
下層に、少なくとも一層の配線が設けられていることを
特徴とする特許請求範囲第１項記載の半導体記憶装置。2. A word line for selecting the switching transistor, an upper layer of a bit line for supplying charges to the charge storage capacitor, and one electrode of the charge storage capacitor. 2. The semiconductor memory device according to claim 1, wherein at least one layer of wiring is provided below a certain plate electrode.
つ、ワード線の線幅より広く、また、ワード線の母線と
しても使用されることを特徴とする特許請求範囲第２項
記載の半導体記憶装置。3. The wiring according to claim 2, wherein the wiring is substantially parallel to the word line, wider than the width of the word line, and used as a bus line of the word line. Semiconductor memory device.
属、もしくは、金属とシリコンの化合物であるシリサイ
ドから成ることを特徴とする特許請求範囲第２項記載の
半導体記憶装置。4. The semiconductor memory device according to claim 2, wherein the wiring is made of a refractory metal such as tungsten or a silicide which is a compound of metal and silicon.
の１／２以上でも良いことを特徴とする特許請求範囲第
１項記載の半導体記憶装置。5. The semiconductor memory device according to claim 1, wherein the film thickness of the capacitor insulating film may be ½ or more of the minimum dimension.
荷の流れるチャネル領域は、半導体基板に掘った溝の側
壁に沿って形成されていることを特徴とする特許請求範
囲第１項記載の半導体記憶装置。6. The semiconductor memory device according to claim 1, wherein in the switching transistor, the channel region in which electric charges flow is formed along a side wall of a groove dug in the semiconductor substrate.
膜により被われていることを特徴とする特許請求範囲第
１項記載の半導体記憶装置。7. The semiconductor memory device according to claim 1, wherein the word line and the bit line are covered with a nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09407592A JP3222188B2 (en) | 1992-04-14 | 1992-04-14 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09407592A JP3222188B2 (en) | 1992-04-14 | 1992-04-14 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05291526A true JPH05291526A (en) | 1993-11-05 |
| JP3222188B2 JP3222188B2 (en) | 2001-10-22 |
Family
ID=14100380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP09407592A Expired - Lifetime JP3222188B2 (en) | 1992-04-14 | 1992-04-14 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3222188B2 (en) |
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|---|---|---|---|---|
| JPH0846152A (en) * | 1994-07-29 | 1996-02-16 | Nec Corp | Semiconductor memory and manufacture |
| JP2000156483A (en) * | 1998-11-18 | 2000-06-06 | Samsung Electronics Co Ltd | Fabrication of concave capacitor having junction spacer |
| KR20010059548A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | Method for manufacturing a semiconductor device |
| US6380574B1 (en) | 1998-05-25 | 2002-04-30 | Hitachi, Ltd. | Ferroelectric capacitor with a self-aligned diffusion barrier |
| US6462368B2 (en) | 2000-10-31 | 2002-10-08 | Hitachi, Ltd. | Ferroelectric capacitor with a self-aligned diffusion barrier |
| US6617205B1 (en) | 1995-11-20 | 2003-09-09 | Hitachi, Ltd. | Semiconductor storage device and process for manufacturing the same |
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| JP2008205481A (en) * | 1999-05-12 | 2008-09-04 | Lucent Technol Inc | Integrated circuit and its method |
| JP4642261B2 (en) * | 2000-06-27 | 2011-03-02 | 三星電子株式会社 | Semiconductor memory device having self-aligned contact and method of manufacturing the same |
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| KR102467506B1 (en) * | 2020-11-19 | 2022-11-15 | 주식회사 아이두젠 | Customized medical staff search method and server implementing thereof |
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Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0846152A (en) * | 1994-07-29 | 1996-02-16 | Nec Corp | Semiconductor memory and manufacture |
| US6617205B1 (en) | 1995-11-20 | 2003-09-09 | Hitachi, Ltd. | Semiconductor storage device and process for manufacturing the same |
| US6791134B2 (en) | 1995-11-20 | 2004-09-14 | Hitachi, Ltd. | Semiconductor memory device and manufacturing method thereof |
| US6798005B2 (en) | 1995-11-20 | 2004-09-28 | Hitachi, Ltd. | Semiconductor memory device having large storage capacity and minimal step height between memory cell and peripheral circuits |
| US7196368B2 (en) | 1995-11-20 | 2007-03-27 | Renesas Technology Corp. | Semiconductor memory arrangements with crown shaped capacitor arrangements trenched in interlayer dielectric film |
| US6380574B1 (en) | 1998-05-25 | 2002-04-30 | Hitachi, Ltd. | Ferroelectric capacitor with a self-aligned diffusion barrier |
| JP2000156483A (en) * | 1998-11-18 | 2000-06-06 | Samsung Electronics Co Ltd | Fabrication of concave capacitor having junction spacer |
| JP2008205481A (en) * | 1999-05-12 | 2008-09-04 | Lucent Technol Inc | Integrated circuit and its method |
| JP2012199572A (en) * | 1999-05-12 | 2012-10-18 | Alcatel-Lucent Usa Inc | Integrated circuit and method of the same |
| KR100770468B1 (en) * | 1999-07-01 | 2007-10-26 | 가부시키가이샤 히타치세이사쿠쇼 | Method of manufacturing semiconductor integrated circuit device |
| KR20010059548A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | Method for manufacturing a semiconductor device |
| JP4642261B2 (en) * | 2000-06-27 | 2011-03-02 | 三星電子株式会社 | Semiconductor memory device having self-aligned contact and method of manufacturing the same |
| US6462368B2 (en) | 2000-10-31 | 2002-10-08 | Hitachi, Ltd. | Ferroelectric capacitor with a self-aligned diffusion barrier |
| US7872290B2 (en) | 2003-04-02 | 2011-01-18 | Samsung Electronics Co., Ltd. | Recess transistor (TR) gate to obtain large self-aligned contact (SAC) open margin |
| US7211482B2 (en) | 2003-04-02 | 2007-05-01 | Samsung Electronics Co., Ltd. | Method of forming a memory cell having self-aligned contact regions |
| US7091540B2 (en) | 2003-04-02 | 2006-08-15 | Samsung Electronics Co., Ltd. | Recess transistor (TR) gate to obtain large self-aligned contact (SAC) open margin |
Also Published As
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|---|---|
| JP3222188B2 (en) | 2001-10-22 |
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