KR20060136240A - A capacitor in semiconductor apparatus and method for forming the same - Google Patents

Abstract

The present invention suppresses the loss of the interlayer insulating film at the bottom of the lower electrode, prevents the lining of the lower electrode, and prevents oxidation of the contact plug at the bottom of the lower electrode when forming a capacitor having a cylindrical structure using a metal electrode as the lower electrode of the capacitor. The present invention provides a capacitor of the semiconductor device and a method of forming the same. To this end, the present invention provides an interlayer insulating film formed by interposing a contact plug on a semiconductor substrate, an etch stop film formed on the interlayer insulating film on both sides of the contact plug. And a conductive barrier layer formed along a stepped portion formed between the contact plug and the etch stop layer, and a lower electrode of a capacitor formed on the conductive barrier layer to protrude upward from the etch stop layer.

Cylinder, Capacitor, Ru, Metal Electrode, Conductive Barrier Film.

Description

Capacitor of Semiconductor Device and Formation Method {A CAPACITOR IN SEMICONDUCTOR APPARATUS AND METHOD FOR FORMING THE SAME}

1 is a cross-sectional view showing a defect phenomenon (see 'D' region) of an interlayer insulating film when forming a capacitor of a semiconductor device according to the prior art.

2 is a cross-sectional view illustrating a phenomenon in which a capacitor lower electrode is formed (see 'L' region) when a capacitor is formed in a semiconductor device according to the related art.

3 is a cross-sectional view illustrating an oxidation phenomenon (see 'O' region) of a contact plug when a capacitor is formed in a semiconductor device according to the prior art.

4 is a cross-sectional view showing a capacitor of a semiconductor device according to a preferred embodiment of the present invention.

5 to 9 are process cross-sectional views showing a capacitor forming process of a semiconductor device according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110 semiconductor substrate 111 interlayer insulating film

112: contact plug 113: etch stop

114: sacrificial insulating film 115: conductive barrier film

116: lower electrode of the capacitor 117: dielectric film

118: upper electrode of the capacitor 120: capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device and a method of forming the same. In particular, a DRAM device having a design rule of 60 nm or less and a ferroelectric memory (FeRAM) having a design rule of 150 nm or less The present invention relates to a capacitor applicable to an element and a method of forming the same.

In recent years, with the rapid spread of computers, the demand for semiconductor devices has increased greatly. Such semiconductor devices require high speed operation while having a high storage capacity in terms of their functions. To this end, semiconductor devices are being manufactured with manufacturing techniques for improving integration, response speed, and reliability.

As such a semiconductor device, a dynamic random access memory (DRAM) device having a high capacity and free input and output of information has been widely used. The DRAM device is composed of a memory cell area storing information data in the form of electric charge and a peripheral circuit area for input and output of the information data. The DRAM device also includes one access transistor and one accumulation capacitor.

The capacitor must be further reduced in size in order to meet the semiconductor device required to increase the degree of integration. However, as the size of the capacitor is reduced, it becomes increasingly difficult to secure the required storage capacity (hereinafter referred to as dielectric capacity). In order to secure the required dielectric capacity, it is necessary to improve the dielectric properties of the dielectric film used in the capacitor, which can be evaluated by an equivalent oxide thickness (Toxeq) and leakage currnet density. For reference, the equivalent oxide film thickness is a value obtained by converting a dielectric film made of a dielectric material other than silicon oxide into the thickness of a dielectric film made of silicon oxide, and the smaller the value, the higher the capacitance per unit area. In addition, the leakage current density is related to the electrical characteristics and power consumption of the capacitor, and a low value thereof is preferable in view of the electrical characteristics of the semiconductor device.

Accordingly, in the DRAM device of 80 nm or less, a dielectric film formed of a laminated structure of HfO ₂ / Al ₂ O ₃ was applied in order to secure a required dielectric capacity while improving leakage current characteristics.

Meanwhile, in order to manufacture a capacitor having a high dielectric capacity with a reduced size, a capacitor having a three-dimensional structure capable of improving the storage capacity of the capacitor without increasing the lateral area occupied by the capacitor on the semiconductor substrate has been recently developed. Forming. A representative example of a three-dimensional capacitor is a capacitor of a cylinder or concave structure.

However, the concave structure has a limit in securing the required dielectric capacity by using a HfO ₂ / Al ₂ O ₃ dielectric film, and a cylinder structure is applied to secure the dielectric capacity of the capacitor. When the lower electrode (storage node) of the capacitor is formed of TiN when forming the capacitor of the cylinder structure, the equivalent oxide film thickness is limited to 11 kW, and the equivalent oxide film thickness is required to secure the dielectric capacity required for devices of 50 nm or less. It should be less than 8Å. As a result, metal electrode introduction technology using ruthenium (Ru), iridium (Ir), or platinum (Pt) having a large workfuntion value as a lower electrode of the capacitor to secure a dielectric capacity required for devices of 60 nm or less. This is essential.

1 to 3 are cross-sectional views illustrating various problems occurring when a capacitor of a cylinder structure using a metal electrode according to the prior art is formed. Here, only a method of forming a capacitor having a cylindrical structure using a metal electrode made of Ru as the lower electrode of the capacitor will be described.

1 to 3, a method of forming a capacitor of a conventional cylinder structure is as follows.

First, an interlayer insulating layer (ILD) 11 including a contact plug 12 is formed on a semiconductor substrate 10 on which a transistor and a bit line forming process are completed. Here, the contact plug 12 is formed of TiN, or a structure in which TiN is laminated on tungsten or polysilicon.

Subsequently, a nitride-based etch stop layer 13 is deposited on the interlayer insulating layer 11 including the contact plug 12, and a sacrificial insulating layer (not shown) is deposited on the etch stop layer 13. The stop film 13 is etched to form a hole (not shown) that exposes the contact plug 12. Then, the lower electrode 15 of the capacitor made of Ru is formed along the inner surface of the hole.

Subsequently, the sacrificial insulating layer is removed through a wet etching process to form the lower electrode 15 having a cylindrical structure.

However, when the sacrificial insulating layer (not shown) is removed, a chemical used in the wet etching process penetrates along the interface between the lower electrode 15 and the etch stop layer 13 as shown in FIG. 1 (arrow direction). ), A defect phenomenon (see 'D' region) of melting the interlayer insulating film 11 at the bottom of the lower electrode 15 occurs. This defect phenomenon (see 'D' region) is due to the poor adhesion between the lower electrode 15 and the etch stop layer 13 made of nitride due to poor adhesion between SiO ₂ and Si-nitride. Concatenate. Accordingly, a method of densifying the bottom of the lower electrode 15 through any one of a thermal process, atomic layer deposition (ALD) and plasma enhanced ALD (PEALD) is used. This is not true.

In addition, as shown in FIG. 2, the adhesion between the lower electrode 15 and the etch stop layer 13 is poor so that the lower electrode 15 formed in a cylinder structure collapses (see 'L' region). This may occur.

In addition, when a thermal process of 700 ° C. or more is required to form a subsequent dielectric layer, as illustrated in FIG. 3, O ₂ penetrates into the contact plug 12 to oxidize the upper portion of the contact plug 12. 'See site) may occur. When such an oxidation phenomenon occurs (see 'O' region), the upper portion of the contact plug 12 is expanded to cause a problem that the lower electrode 15 of the cylinder structure falls off.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and has a semiconductor device capable of suppressing the interlayer insulating film loss at the bottom of the lower electrode when forming a capacitor having a cylindrical structure using a metal electrode as the lower electrode of the capacitor. It is an object of the present invention to provide a capacitor and a method of forming the same.

Another object of the present invention is to provide a capacitor of a semiconductor device and a method of forming the same, which can prevent the lowering of the lower electrode when a capacitor having a cylindrical structure using a metal electrode as a lower electrode of the capacitor is formed.

Another object of the present invention is to provide a capacitor of a semiconductor device and a method of forming the same, which can prevent oxidation of a contact plug at the bottom of a lower electrode when a capacitor having a cylindrical structure using a metal electrode as a lower electrode of a capacitor is formed. have.

According to an aspect of the present invention, there is provided an interlayer insulating film formed with a contact plug interposed on a semiconductor substrate, an etch stop film formed on the interlayer insulating film on both sides of the contact plug, the contact plug, and the contact plug. The present invention provides a capacitor of a semiconductor device including a conductive barrier layer formed along a stepped portion formed between the etch stop layers and a lower electrode of a capacitor formed on the conductive barrier layer to protrude upward from the etch stop layer.

According to another aspect of the present invention, there is provided a method of forming an interlayer insulating film having a contact plug interposed on a semiconductor substrate, depositing an etch stop film on the interlayer insulating film, and stopping the etch stop. Depositing a sacrificial insulating film on the film, etching the sacrificial insulating film and the etch stop film to form a hole exposing the contact plug, and forming a lower electrode of the conductive barrier film and the capacitor along the inner surface of the hole And removing the sacrificial insulating layer, and etching the conductive barrier layer so that the conductive barrier layer interposed between the etch stop layer and the lower electrode of the capacitor remains. to provide.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. Also, throughout the specification, the same reference numerals denote the same components.

Example

4 is a cross-sectional view illustrating a capacitor of a semiconductor device in accordance with a preferred embodiment of the present invention.

Referring to FIG. 4, a capacitor of a semiconductor device according to an exemplary embodiment of the present invention may include an interlayer insulating layer (ILD) 111 formed with a contact plug 112 interposed on a semiconductor substrate 110, and both sides of the contact plug 112. The etch stop film 113 formed on the interlayer insulating film 111, the conductive barrier film 115 formed along the stepped portion formed between the contact plug 112 and the etch stop film 113, and the etch stop film 113. The lower electrode 116 of the capacitor formed on the barrier layer 115 is formed to protrude. In addition, the capacitor 120 further includes a dielectric film 117 formed along the level of the upper portion of the entire structure including the lower electrode 116 of the capacitor and an upper electrode 118 of the capacitor formed along the level of the upper portion of the dielectric film 117. Is completed.

In this case, the conductive barrier film 115 may have at least 3 in order to prevent the chemical from penetrating along the interface between the lower electrode 116 of the capacitor and the etch stop film 115 while preventing O ₂ from penetrating by a subsequent thermal process. It is formed of a multi-component conductive barrier material or two-component conductive barrier material consisting of two components. The multi-component conductive barrier material is made of any one selected from the group consisting of RuTiN, RuTiO, TiAlN, TiSiN, TaSiN, WSiN and WBN, the bi-component conductive barrier material is made of any one selected from the group consisting of TiN, WN and TaN.

At this time, the lower electrode 116 of the capacitor is formed in a cylindrical structure to increase the effective area of the capacitor, selected from the group consisting of Ru, Pt, Ir, Rh, Pd, Hf, Ti, W, Ta, Au and Ag Either or a mixture thereof and nitride or a conductive oxide film is formed.

In addition, the dielectric film 117 includes HfO ₂ , Al ₂ O ₃ , ZrO ₂ , La ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , BST (BaSrTiO ₃ ), SrTiO ₃ , PZT, BLT, SPT, and Bi ₂ Ti. _It is formed of any one selected from the group consisting of ₂ O ₇ or a laminated film or a composite thereof.

That is, in the capacitor of the semiconductor device according to the preferred embodiment of the present invention, the interlayer insulating layer 111 on both sides of the contact plug 112 is interposed between the contact plug 112 and the lower electrode 116 of the capacitor. As a result, penetration of the chemical can be suppressed, and penetration of O ₂ into the contact plug 112 can be suppressed. Accordingly, defects of the interlayer insulating layer 111 and oxidation of the upper portion of the contact plug 112 may be prevented.

In addition, the conductive barrier layer 115 is formed of a barrier material in which nitride is mixed to improve adhesion between the etch stop layer 113 and the lower electrode 116 of the capacitor, thereby reducing the lower electrode 116 of the capacitor. Can be prevented.

5 to 9 are process cross-sectional views illustrating a capacitor forming process of a semiconductor device in accordance with a preferred embodiment of the present invention.

First, as shown in FIG. 5, an interlayer insulating film 111 is deposited on a semiconductor substrate 110 on which a transistor (not shown) and a bit line (not shown) forming process is completed. In this case, the interlayer insulating film 111 is formed of an oxide film-based material. For example, HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, PETEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) film, PECVD (Plasma Enhanced Chemical Vapor Deposition) film, USG It is formed as a single layer film or a laminated film in which these layers are formed using any one of an un-doped silicate glass (FSG) film, a fluorinated silicate glass (FSG) film, a carbon doped oxide (CDO) film, and an organic silicate glass (OSG) film.

Subsequently, the interlayer insulating layer 111 is etched through a mask process and an etching process to form a contact hole (not shown) that exposes a portion of the substrate 110. Thereafter, the plug material is deposited to fill the contact hole, and then an etch back or chemical mechanical polishing (CMP) process is performed to form the contact plug 112 embedded in the contact hole. In this case, the contact plug 112 is formed of any one selected from the group consisting of tungsten (W), polysilicon and TiN. Here, to form the contact plug 112 using tungsten or polysilicon, first deposit tungsten or polysilicon and then recess it to a certain depth. Next, a contact plug 112 embedded in the contact hole is formed by forming a titanium silicide (Ti-silicide), depositing TiN, and then performing a CMP process to planarize it. On the other hand, in the case of using tungsten, the titanium silicide forming step can be omitted.

Subsequently, the nitride-based etching stop film 113 and the oxide-based sacrificial insulating film 114 are sequentially deposited on the interlayer insulating film 111 including the contact plug 112.

Subsequently, a photoresist pattern (not shown) is formed on the sacrificial insulating layer 114 by a photolithography process, and an etching process using the same is performed, or an etching process using a hard mask scheme is performed. 114 and the etch stop film 113 are etched. As a result, a hole (not shown) exposing the contact plug 112 is formed.

Subsequently, the conductive barrier film 115 is deposited along the steps of the entire structure including the holes. Here, the conductive barrier film 115 deposits a multi-component conductive barrier material composed of at least three components or a two-component (two) based conductive barrier material to a thickness of 1 to 300 Å. The multi-component conductive barrier material is made of any one selected from the group consisting of RuTiN, RuTiO, TiAlN, TiSiN, TaSiN, WSiN and WBN, the bi-component conductive barrier material is made of any one selected from the group consisting of TiN, WN and TaN. .

In addition, the deposition process of the conductive barrier film 115 uses any one deposition method selected from the group consisting of ALD, PEALD, Chemical Vapor Deposition (CVD) and cyclic CVD methods. Here, the ALD method performs a cycle of source gas adsorption step / purge step / reactant step / purge step, when the conductive barrier film 115 is a multi-component conductive barrier material. By adjusting the number of cycles for each component, the composition ratio for each component can be determined. As an example, to form the conductive barrier film 115 as RuTiN (Ru gas adsorption step / purge step / reactant step / purge step) performed m times, (Ti gas adsorption step / purge step / reactant step) / Purge step) is performed n times, by adjusting the m and n to obtain the desired composition ratio. The purge step is to inject Ar or N ₂ gas into the chamber to discharge surplus gas remaining after the adsorption of source (or reactant) gas to the outside of the chamber, and the reactant step is to inject ammonia gas into the chamber. Reaction step.

In the PEALD method, plasma processing is performed during the reactant step of the ALD method.

Subsequently, as shown in FIG. 6, the lower electrode material (not shown) of the capacitor is deposited along the step above the conductive barrier film 115. Here, the lower electrode material of the capacitor is one selected from the group consisting of Ru, Pt, Ir, Rh, Pd, Hf, Ti, W, Ta, Au, and Ag, or a mixture or conductive oxide film mixed with nitride.

In addition, the deposition process of the lower electrode material of the capacitor uses any one deposition method selected from the group consisting of ALD, PEALD, CVD, and periodic CVD, which is a reactive gas O ₂ , NH ₃ , N ₂ O , N ₂ H ₄ , Me ₂ N ₂ H ₂ And using any one selected from the group consisting of H ₂ or mixed gas thereof.

Subsequently, an etch back or CMP process is performed to remove the conductive barrier layer 115 and the lower electrode material of the capacitor, which are exposed on the sacrificial insulating layer 114. As a result, the conductive barrier layer 115 connected to the contact plug 112 and the lower electrode 116 of the capacitor are formed along the inner surface of the hole (not shown).

Subsequently, as shown in FIG. 7, the sacrificial insulating layer 114 (see FIG. 6) is removed by performing a wet dip out process in which the entire structure in which the lower electrode 116 of the capacitor is formed is immersed in the chemical. At this time, since the conductive barrier film 115 surrounds the lower electrode 116 of the capacitor, the penetration of the chemical into the interlayer insulating film 111 can be suppressed even during the wet dip out process.

Subsequently, as shown in FIG. 8, the conductive barrier layer 115 protruding from the etch stop layer 113 is etched by performing a wet etching process. As a result, the conductive barrier layer 115 remains between the lower electrode 116 of the capacitor and the etch stop layer 113, and the lower electrode 116 of the capacitor has a cylinder structure. In this case, the conductive barrier film 115 interposed between the lower electrode 116 and the etch stop layer 113 of the capacitor is a mixture of a metal and a nitride between the etch stop layer 113 of the nitride film series and the lower electrode 116 of the capacitor. Improves adhesive properties. Therefore, it is possible to prevent a phenomenon in which the existing capacitor occurs.

Next, as shown in FIG. 9, the dielectric film 117 is deposited along the stepped portion of the entire structure including the lower electrode 116 of the capacitor. Here, the dielectric film 117 is formed of HfO ₂ , Al ₂ O ₃ , ZrO ₂ , La ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , BST (BaSrTiO ₃ ), SrTiO ₃ , PZT, BLT, SPT, and Bi ₂ Ti _It is formed of any one selected from the group consisting of ₂ O ₇ or a laminated film or a composite thereof. In one example, the laminated film is formed of a possible combination such as HfO ₂ / Al ₂ O ₃ and HfO ₂ / Al ₂ O ₃ / HfO ₂ , and the composite is formed of Hf _X Al _Y O _Z simultaneously containing Hf and Al. . At this time, since the conductive barrier film 115 is present between the lower electrode 116 and the contact plug 112 of the capacitor, the penetration of O ₂ into the contact plug can be suppressed even during the thermal process for forming the dielectric film 117. .

In addition, the deposition process of the dielectric film 117 uses any one deposition method selected from the group consisting of sputtering, CVD and ALD. The ALD method is carried out using one source gas adsorption step / purge step / react step / purge step. For example, in order to form the dielectric film 117 as Hf _X Al _Y O _Z using the ALD method, (Hf gas adsorption step / purge step / reactant step / purge step) is performed m times (Al gas adsorption step / purge step). Step / react step / purge step) may be performed n times, where m and n may be 1 to 9 times. At this time, the purge step is to inject the N ₂ gas into the chamber to discharge the surplus gas remaining without reacting after the source (or reactant) gas adsorption, the reacting step is to react using O ₃ gas . As another example, when Hf _X Al _Y O _Z uses the PEALD method, O ₃ is replaced with O ₂ at the reacting step of the ALD method, and plasma treatment is performed.

Subsequently, a post treatment process is performed to improve leakage current characteristics, and plasma treatment using oxygen and / or ozone is used. This post-treatment step is carried out at a temperature of 200 to 500 ℃.

Subsequently, the capacitor 120 is completed by depositing the upper electrode 118 of the capacitor along the step above the dielectric film 117. In this case, the upper electrode 118 of the capacitor is formed of the same material as the lower electrode 116 of the capacitor or formed of a conductive thin film. Only the conductive foil is made of conductive silicon or conductive TiN which is conductive by being doped with As or P or the like.

After the deposition process of the ALD method or the CVD method throughout the above process, the plasma treatment may be additionally performed every cycle or every 2 to 100 cycles in order to improve the thin film properties. The plasma treatment is performed at a power of 10 to 1500 W, and any one selected from the group consisting of O ₂ , NH ₃ , N ₂ O, N ₂ H ₄ , Me ₂ N ₂ H _2, and H ₂ as a reaction gas It is carried out using a mixed gas.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the penetration of the chemical into the interlayer insulating film on both sides of the contact plug when the sacrificial insulating film is removed by interposing the conductive barrier film between the contact plug and the lower electrode of the capacitor can be prevented. The penetration of O ₂ can be suppressed. Therefore, it is possible to prevent the defect phenomenon of the interlayer insulating film and the oxidation phenomenon of the contact plug.

In addition, the conductive barrier layer may be formed of a barrier material in which nitride is mixed to improve adhesion between the etch stop layer and the lower electrode of the capacitor, thereby preventing the lower electrode of the capacitor.

Therefore, not only the yield improvement and cost reduction effect of the DRAM device having a design rule of 60 nm or less can be obtained, but also a ferroelectric random access memory (FeRAM) having a design rule of 150 nm or less. ) Ferroelectric and fatigue characteristics of the device can be improved.

Claims (27)

An interlayer insulating film formed on the semiconductor substrate with a contact plug interposed therebetween; An etch stop layer formed on the interlayer insulating layer on both sides of the contact plug; A conductive barrier film formed along the stepped portion formed between the contact plug and the etch stop film; And A lower electrode of a capacitor formed on the conductive barrier layer so as to protrude above the etch stop layer Capacitor of a semiconductor device comprising a. The method of claim 1, The conductive barrier film is a capacitor of the semiconductor device formed of any one selected from the group consisting of RuTiN, RuTiO, TiAlN, TiSiN, TaSiN, WSiN, WBN, TiN, WN and TaN. The method of claim 1, The capacitor of the semiconductor device, wherein the lower electrode of the capacitor has a cylindrical structure. The method according to claim 1 or 3, The lower electrode of the capacitor is any one selected from the group consisting of Ru, Pt, Ir, Rh, Pd, Hf, Ti, W, Ta, Au and Ag, or a capacitor of a semiconductor device formed of a mixture of a nitride or a mixture thereof and a conductive oxide film . Forming an interlayer insulating film having a contact plug interposed on the semiconductor substrate; Depositing an etch stop film on the interlayer insulating film; Depositing a sacrificial insulating film on the etch stop layer; Etching the sacrificial insulating layer and the etch stop layer to form a hole exposing the contact plug; Forming a lower electrode of the conductive barrier layer and the capacitor along the inner surface of the hole; Removing the sacrificial insulating film; And Etching the conductive barrier layer such that the conductive barrier layer interposed between the etch stop layer and the lower electrode of the capacitor remains. Capacitor forming method of a semiconductor device comprising a. The method of claim 5, And the conductive barrier film is formed of a multi-component conductive barrier material or a two-component conductive barrier material composed of at least three components. The method of claim 6, The multi-component conductive barrier material is a capacitor forming method of a semiconductor device consisting of any one selected from the group consisting of RuTiN, RuTiO, TiAlN, TiSiN, TaSiN, WSiN and WBN. The method of claim 6, The bicomponent conductive barrier material is a capacitor forming method of a semiconductor device consisting of any one selected from the group consisting of TiN, WN and TaN. The method of claim 5, Wherein the conductive barrier film is deposited using any one method selected from the group consisting of ALD, PEALD, CVD and cyclic CVD. The method of claim 9, The ALD method is a capacitor forming method of a semiconductor device to perform the source gas adsorption step / purge step / reactant step / purge step in one cycle. The method according to claim 9 or 10, In the ALD method, when the conductive barrier film is formed of the multi-component conductive barrier material, the composition ratio for each component is determined by adjusting the number of cycles for each component. The method of claim 10, The PEALD method is a capacitor forming method of a semiconductor device to perform a plasma treatment in the reactant step. The method of claim 5, The lower electrode of the capacitor is any one selected from the group consisting of Ru, Pt, Ir, Rh, Pd, Hf, Ti, W, Ta, Au and Ag, or a semiconductor device to form a mixture or a conductive oxide film mixed with nitride Capacitor Formation Method. The method of claim 13, And forming the lower electrode of the capacitor by any one method selected from the group consisting of ALD, PEALD, CVD, and periodic CVD. The method of claim 14, When depositing the lower electrode of the capacitor, a capacitor of a semiconductor device using any one or a mixed gas selected from the group consisting of O ₂ , NH ₃ , N ₂ O, N ₂ H ₄ , Me ₂ N ₂ H ₂ and H ₂ Formation method. The method of claim 5, wherein after etching the conductive barrier film, Forming a dielectric film along a step of an upper portion of the entire structure including the lower electrode of the capacitor; And Forming an upper electrode of the capacitor along a step of an upper portion of the dielectric layer Capacitor forming method of a semiconductor device further comprising. The method of claim 16, The dielectric layer is HfO ₂ , Al ₂ O ₃ , ZrO ₂ , La ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , BST (BaSrTiO ₃ ), SrTiO ₃ , PZT, BLT, SPT, and Bi ₂ Ti ₂ O ₇ A method for forming a capacitor of a semiconductor device, which is formed from any one selected from the group consisting of one or a laminated film thereof or a composite thereof. The method according to claim 16 or 17, And the dielectric film is deposited by any one method selected from the group consisting of sputtering, CVD, and ALD. The method of claim 18, The ALD method is a capacitor forming method of a semiconductor device to perform the source gas adsorption step / purge step / reactant step / purge step in one cycle. The method of claim 19, The purge step is a capacitor forming method of a semiconductor device using N ₂ gas. The method of claim 19, The reactant step is a capacitor forming method of a semiconductor device using O ₃ gas. The method of claim 19 or 21, Wherein the ALD method is replaced by a PEALD method, during the reactant step of replacing the O ₃ with O ₂ and the plasma forming method of the capacitor of the semiconductor device. The method according to claim 16 or 17, And forming a dielectric film, and then performing post-treatment using ozone and / or oxygen plasma. The method of claim 23, wherein The said post-processing is a capacitor formation method of the semiconductor device performed at 200-500 degreeC. The method according to any one of claims 7, 14 and 18, And a plasma treatment is performed after the deposition process using the ALD or CVD method. The method of claim 25, The plasma treatment is performed using any one or a mixture of these gases selected from the group consisting of O ₂ , NH ₃ , N ₂ O, N ₂ H ₄ , Me ₂ N ₂ H _2, and H ₂ to form a capacitor of a semiconductor device. Way. The method of claim 25, And the plasma treatment is performed at a power of 10 to 1500W.

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