KR100532959B1 - Method for forming capacitor of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a capacitor of a semiconductor device. The disclosed method includes forming an interlayer insulating film on a semiconductor substrate on which a landing plug is formed, forming a contact hole for a storage electrode exposing the landing plug by etching the interlayer insulating film, and forming a contact hole on the sidewall of the contact hole. Forming a first nitride film for a spacer, forming a sacrificial plug in the contact hole, depositing an etch stop second nitride film and a sacrificial oxide film on the sacrificial plug and the interlayer insulating film, and then Etching the second nitride film for etch stop to form a first trench to expose the sacrificial plug, forming a second trench to expose the landing plug by removing the exposed sacrificial plug, and forming a second trench surface and Forming a conductive layer on the sacrificial oxide layer, and removing the conductive layer portion on the sacrificial oxide layer to store the conductive layer. Forming an electrode, removing the sacrificial oxide film, and sequentially forming a dielectric film and a plate electrode on the storage electrode. According to the present invention, since the contact hole where the poly plug is to be formed is used as the electrode area, the capacitor height can be increased without increasing the electrode height, thereby improving the charging capacity of the capacitor.

Description

Method for forming capacitor of semiconductor device

The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device capable of increasing the capacitance of the capacitor without increasing the electrode height.

The DRAM needs to be refreshed every predetermined time because the stored data is not directly connected to the power supply. In addition, the higher the charge capacity of the capacitor is advantageous because the stored data must be maintained for a long time.

However, as the integration of semiconductor devices proceeds, the cell size is reduced, and the decrease in the cell size is accompanied by a decrease in the capacitor area, and the decrease in the capacitor area leads to a decrease in the charging capacity. It is difficult to secure the charging capacity required to keep the device operating characteristics constant.

In order to secure a certain amount of charge capacity required for cell operation, a memory device currently in mass production may form a storage electrode in a three-dimensional structure, use a high dielectric constant material as a material of a dielectric film, or form a dielectric film as thin as possible. Doing.

This is based on the charge capacity of the capacitor being proportional to the electrode surface area and the dielectric constant of the dielectric film and inversely proportional to the gap between the upper and lower electrodes, i.

In practice, current capacitors respond to the reduction of capacitor area due to high integration by increasing the height of the storage electrodes by forming the three-dimensional structure, for example, a cylinder structure.

However, as the height of the storage electrode increases, the capacitor itself becomes physically unstable, and at the same time, process difficulties are encountered. In other words, as the height of the storage electrode is increased, the etching process is difficult, and in particular, in the dip-out process for removing the sacrificial oxide layer, the collapse of the storage electrode and the bridge between adjacent storage electrodes are performed. A bridge is occurring.

Accordingly, an object of the present invention is to provide a method for forming a capacitor of a semiconductor device capable of increasing the charging capacity without increasing the height of the electrode, which is devised to solve the conventional problems as described above.

In order to achieve the above object, the present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate on which the landing plug is formed; Etching the interlayer insulating film to form a contact hole for a storage electrode exposing a landing plug; Forming a first nitride film for a spacer on sidewalls of the contact hole; Forming a sacrificial plug in the contact hole; Sequentially depositing an etch stop second nitride film and a sacrificial oxide film on the sacrificial plug and the interlayer insulating film; Forming a first trench to expose the sacrificial plug by etching the sacrificial oxide film and the second nitride film for etch stop; Removing the exposed sacrificial plug to form a second trench exposing the landing plug; Forming a conductive film on the second trench surface and the sacrificial oxide film; Removing a portion of the conductive layer on the sacrificial oxide layer to form a storage electrode; Removing the sacrificial oxide film; And forming a dielectric film and a plate electrode sequentially on the storage electrode.

Here, the sacrificial plug is made of polysilicon.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be described.

In a conventional capacitor structure, a landing plug and a poly plug are interposed between the substrate bonding region and the storage electrode, wherein the contact hole where the poly plug, more precisely, the poly plug is formed, is excluded from the electrode area.

Therefore, the present invention increases the surface area of the storage electrode by using the contact hole in which the poly plug is to be formed as the electrode area, thereby improving the charging capacity of the capacitor without actually increasing the height of the electrode.

1A to 1F are cross-sectional views illustrating a method of forming a capacitor according to an embodiment of the present invention, which will be described below.

Referring to FIG. 1A, a semiconductor substrate having a gate 2, a landing plug 4, and a bit line 6 is prepared according to a known process. Reference numeral 3 denotes a first interlayer insulating film, and 5 denotes a second interlayer insulating film.

Next, a third interlayer insulating film 7 is deposited on the entire surface of the substrate including the bit lines 6. Thereafter, the third interlayer insulating film 7 is etched to form a contact hole 8 for a storage electrode exposing the landing plug 4.

Referring to FIG. 1B, a first nitride film 9 for spacers is deposited on the surface of the storage hole contact hole 8 and the third interlayer insulating film 7. At this time, the first nitride film 9 for the spacer is deposited thicker than the normal deposition thickness. Next, the first nitride film 9 is etched entirely without using a mask to remove the first nitride film portion deposited on the third interlayer insulating film 7 and the landing plug 4.

Referring to FIG. 1C, a polysilicon film is deposited on a substrate resultant to fill a contact hole 8 for a storage electrode, and then a sacrificial poly plug 10 is formed by chemical mechanical polishing (CMP). Then, the second nitride film 11 for etching stop and the sacrificial oxide film 12 are sequentially deposited on the entire surface of the substrate including the sacrificial poly plug 7.

Referring to FIG. 1D, after the photoresist pattern (not shown) is formed on the sacrificial oxide film 12 to expose a portion of the sacrificial oxide layer on the sacrificial poly plug 10, the second nitride film is used as the etch barrier. The exposed sacrificial oxide film portion is etched using (11) as an etch stop film. Thereafter, the sacrificial oxide layer 12 is etched to etch the exposed second nitride layer portion, thereby forming a first trench 13 exposing the sacrificial poly plug 10.

Referring to FIG. 1E, in the state where the photoresist pattern is removed, the sacrificial poly plug exposed by the first trench is removed by wet etching using an etchant having a large etching selectivity of the polysilicon film relative to the nitride film and the oxide film. Through this, the second trench 14 exposing the landing plug 4 is formed. The second trench 14 is higher in height than the sacrificial plug poly removed compared to the first trench 13.

Referring to FIG. 1F, after depositing the first conductive film on the surface of the second trench 14 and the sacrificial oxide film 12, the portion of the first conductive film deposited on the sacrificial oxide film 12 is etched according to a known process. To form the storage electrode 15.

Subsequently, although not shown, a dielectric film and a plate electrode are sequentially formed on the storage electrode 15 to form a capacitor according to the present invention.

In the above, since the method of the present invention uses the contact hole in which the poly plug is formed as the electrode area, the electrode area can be largely expanded without increasing the height of the capacitor, thereby obtaining a capacitor having an improved charging capacity. .

In addition, the method of the present invention increases the charging capacity while avoiding the process difficulties caused by raising the capacitor height, thereby increasing the refresh time of the cell.

In addition, in the capacitor structure of the present invention, the contact between the storage electrode and the substrate bonding region is formed through the landing plug, so that the contact resistance can be reduced as compared with the conventional one made through the landing plug and the poly plug. In addition, the current path is also reduced to further reduce the resistance. In particular, as the contact resistance can be reduced, the tWR fail generated during the write operation can be reduced, and the time required for reading and writing the data is also reduced, thereby improving the operation speed.

As described above, the present invention can increase the capacitor electrode area without increasing the electrode height by utilizing the contact hole in which the plug is to be formed as the capacitor area, thereby easily and reliably forming a high capacity capacitor. have.

In addition, the present invention may also improve process difficulties by utilizing the contact hole where the poly plug is formed as the capacitor area.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

1A to 1F are cross-sectional views illustrating processes of forming a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

1 semiconductor substrate 2 gate

3: first interlayer insulating film 4: landing plug

5: second interlayer insulating film 6: bit line

7: third interlayer insulating film 8: contact hole for storage electrode

9: first nitride film for spacer 10: sacrificial poly plug

11: second nitride film for etching stop 12: sacrificial oxide film

13: first trench 14: second trench

15: storage electrode

Claims (2)

Forming an interlayer insulating film on the semiconductor substrate on which the landing plug is formed; Etching the interlayer insulating film to form a contact hole for a storage electrode exposing a landing plug; Forming a first nitride film for a spacer on sidewalls of the contact hole; Forming a sacrificial plug in the contact hole; Sequentially depositing an etch stop second nitride film and a sacrificial oxide film on the sacrificial plug and the interlayer insulating film; Forming a first trench to expose the sacrificial plug by etching the sacrificial oxide film and the second nitride film for etch stop; Removing the exposed sacrificial plug to form a second trench exposing the landing plug; Forming a conductive film on the second trench surface and the sacrificial oxide film; Removing a portion of the conductive layer on the sacrificial oxide layer to form a storage electrode; Removing the sacrificial oxide film; And And sequentially forming a dielectric film and a plate electrode on the storage electrode. The method of claim 1, wherein the sacrificial plug is made of polysilicon.