KR101419894B1 - DRAM including micro-electro mechanical system and method of manufacturing the same - Google Patents

Abstract

In a DRAM device and a manufacturing method thereof, the DRAM device is provided with a contact plug on a substrate. A conductive beam in the form of a horizontal blade connected to the upper surface of the contact plug, extending in a direction parallel to the substrate, and having both ends lowered toward the substrate. A word line spaced apart from the conductive beam and to which a signal for mechanically moving the conductive beam is applied. And capacitors electrically short-circuiting or opening with the contact portion of the conductive beam by movement of the conductive beam. In the DRAM device, the conductive beam is moved by the word line, and both ends of the conductive beam are lowered in the direction of the substrate, so that electrical contact with the capacitor is easy.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a DRAM including an electromechanical device and a manufacturing method thereof,

The present invention relates to a DRAM and a method of manufacturing the same. More particularly, the present invention relates to a DRAM including an electromechanical element and a method of manufacturing the same.

Among the memory elements, the DRAM has a MOS transistor for selecting a cell and a capacitor as a unit cell, and distinguishes the data of the cell by the charge stored in the capacitor.

In the case of a conventional DRAM cell, since the charge stored in the capacitor continuously leaks through the PN junction of the source region of the MOS transistor, a charge compensation operation called reflashing is periodically performed on the cell do. By performing the refresh operation, the power consumption of the DRAM becomes very high. Further, in order to increase the refresh period, the capacitance of the capacitor must be very large.

However, it is not easy to form a capacitor so as to have a high capacitance within a narrow horizontal area. Further, the gate line width of the MOS transistor included in the cell is reduced, thereby increasing the resistance of the gate.

Therefore, there is a demand for a DRAM device in which a data retention time is increased, no refresh is required, or a refresh cycle is long.

An object of the present invention is to provide a novel structure of a DRAM device having excellent data retention characteristics.

Another object of the present invention is to provide a method of manufacturing the above-described DRAM device.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a substrate; A conductive beam in the form of a horizontal blade connected to the upper surface of the contact plug, extending in a direction parallel to the substrate, and having both ends lowered toward the substrate. A word line spaced apart from the conductive beam and to which a signal for mechanically moving the conductive beam is applied. And capacitors electrically short-circuiting or opening with the contact portion of the conductive beam by movement of the conductive beam.

In one embodiment of the present invention, a bit line may be provided on the substrate and electrically connected to the bottom surface of the contact plug.

In one embodiment of the present invention, the word line and the capacitor are located below the bottom surface of the conductive beam, and the top surface is exposed.

In one embodiment of the present invention, the gap between the bottom surface of the conductive beam and the top surface of the capacitor is narrower than the gap between the bottom surface of the conductive beam and the top surface of the word line.

In an embodiment of the present invention, two contact plugs may be disposed on both sides of the contact plug such that the word lines and the capacitors are symmetrical with respect to the contact plug.

In an embodiment of the present invention, the capacitor may be a stacked capacitor in which a first electrode pattern, a dielectric layer, and a second electrode pattern are sequentially deposited.

In one embodiment of the present invention, the first electrode pattern of the capacitor has a line shape extending in a direction perpendicular to the bit line, and the second electrode pattern may have an isolated pattern shape.

In an embodiment of the present invention, first and second conductive pads, each having a top surface positioned on the same plane as the word line, may be further provided on the contact plug and the capacitor.

According to an embodiment of the present invention, there is provided a semiconductor memory device comprising: an insulating film covering a cell formed on a substrate with a space for moving the conductive beam up and down; an upper bit line provided on the insulating film; And upper cells including a contact plug, a conductive beam, a word line, and a capacitor having the same structure as the cells formed in the substrate.

In one embodiment of the present invention, a ferroelectric circuit region for applying a signal to a cell is provided on one side of a substrate, and a substrate connected to the selection transistor and the selection transistor may be provided on the substrate of the ferrite circuit region .

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a capacitor on a substrate; And a contact plug is formed to be spaced apart from the side of the capacitor. A word line is formed between the capacitor and the contact plug. Next, a conductive beam is formed which has a shape of a blade connected to the upper surface of the contact plug and extending in a direction parallel to the substrate while being positioned on the capacitor and the word line, and having both ends lowered toward the substrate do.

In one embodiment of the present invention, a bit line is formed on the substrate. A first interlayer insulating film covering the bit line is formed.

In one embodiment of the present invention, a first electrode layer, a dielectric layer, and a second electrode layer are sequentially formed on the first interlayer insulating layer to form the capacitor. Then, the second electrode film, the dielectric film, and the first electrode film are patterned to form a first electrode pattern having a line shape, a dielectric film pattern, and a second preliminary electrode pattern. Next, the second preliminary electrode pattern is patterned so as to be cut in a direction perpendicular to the extending direction of the first electrode pattern to form an isolated second electrode pattern.

The patterning process for forming the second electrode pattern may be performed simultaneously with the process for forming the word line.

In one embodiment of the present invention, first and second conductive patterns of isolated shape are formed which contact the upper surface of the capacitor and the upper surface of the contact plug, respectively.

In one embodiment of the present invention, the step of exposing the capacitor upper surface and the upper surface of the contact plug may further include forming an interlayer insulating film for embedding between the capacitor and the contact plug.

In one embodiment of the present invention, the step of exposing the capacitor upper surface and the upper surface of the contact plug may further include forming an interlayer insulating film for embedding between the capacitor and the contact plug.

In one embodiment of the present invention, a sacrificial layer is formed on the capacitor, exposing the contact plug to form the conductive beam, having a first thickness on the interlayer dielectric and the word line, and a second thickness on the capacitor that is less than the first thickness Thereby forming a film pattern. A conductive film is formed along the sacrificial pattern surface while contacting the upper surface of the contact plug. The conductive film is patterned to form a conductive beam. Next, the sacrificial film pattern under the conductive beam is removed.

In one embodiment of the present invention, to form the sacrificial pattern, a first sacrificial pattern is formed covering the interlayer insulating layer and the word line while exposing the contact plug. Next, the first sacrificial film pattern and the second sacrificial film pattern covering the capacitor are formed while exposing the contact plug.

In one embodiment of the present invention, to form the sacrificial pattern, a first sacrificial film pattern is formed covering the interlayer insulating film, the word line, and the capacitor while exposing the contact plug. Next, a second sacrificial film pattern covering the interlayer insulating film and the word line is formed on the first sacrificial film pattern while exposing the contact plug.

In one embodiment of the present invention, a preliminary sacrificial film pattern is formed to cover the interlayer insulating film, the word line, and the capacitor while exposing the contact plug, in order to form the sacrificial film pattern. Thereby removing a portion of the preliminary sacrificial film pattern located on the capacitor.

In one embodiment of the present invention, a ferrite circuit region for applying a signal to the cell is provided on one side of the substrate, and a selection transistor and a wiring connected to the selection transistor are formed on the substrate of the ferrite circuit region.

As described, the DRAM device of the present invention uses a switching element that performs a mechanical operation instead of a conventional MOS transistor, so that the charge leakage of the capacitor is greatly reduced. Therefore, even if a capacitor having a small capacitance is used, data classification in a cell is possible. Further, in the switching device performing the mechanical operation, since both ends of the conductive beam are lowered toward the substrate, the distance between the conductive beam and the capacitor is relatively reduced. Therefore, when the conductive beam and the capacitor are in contact with each other, the defect caused by the contact between the conductive beam and the word line can be reduced.

The DRAM device of the present invention may have nonvolatility such that the charge stored in the cell does not change even if the power supply is interrupted because there is little charge leakage of the capacitor.

Since the DRAM device of the present invention does not have to be formed on the semiconductor material, the selection of the substrate becomes various and it is easy to construct each cell in a multi-layered structure.

Further, complicated processes such as an ion implantation process and a device isolation process for fabricating a conventional MOS transistor in manufacturing the DRAM device of the present invention are not required. Therefore, the DRAM device of the present invention can be manufactured by a simpler process.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, like reference numerals have been used for similar elements while explaining each drawing. In the accompanying drawings, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

In the present invention, the terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In the present invention, it is to be understood that each layer (film), region, electrode, pattern or structure may be formed on, over, or under the object, substrate, layer, Means that each layer (film), region, electrode, pattern or structure is directly formed or positioned below a substrate, each layer (film), region, or pattern, , Other regions, other electrodes, other patterns, or other structures may additionally be formed on the object or substrate.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, But should not be construed as limited to the embodiments set forth in the claims.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Example 1

1 is a cross-sectional view showing a DRAM device according to a first embodiment of the present invention.

Referring to FIG. 1, a substrate 100 in which a ferrier circuit region and a cell region are separated is provided.

The upper surface of the substrate 100 may be made of a semiconductor material. That is, the substrate 100 may be a single crystal silicon substrate, an SOI substrate, or the like. In this embodiment, the substrate 100 is made of a single crystal silicon substrate.

A device isolation pattern 102a is provided on the substrate 100 of the ferrier circuit region. The element isolation pattern 102a is formed through a shell row trench element isolation process. On the other hand, the substrate 100 of the cell region may be provided with a device isolation pattern of the same type as the substrate of the ferrier circuit. However, the device isolation pattern formed on the substrate of the cell region does not serve to distinguish the active region from the device isolation region, but a dummy pattern for reducing the defective dishing when forming the device isolation pattern 102a in the ferrier circuit region And is used as the pattern 102b.

A MOS transistor composed of a gate insulating film (not shown), a gate electrode 106, and a source / drain region 118 is provided on the substrate of the ferrier circuit region. The MOS transistor is provided as a switching element constituting ferrier circuits. A hard mask pattern 108 is provided on the gate electrode 106 and spacers 116 are provided on both sides of the gate electrode 106 and the hard mask pattern 108. The gate insulating film is made of silicon oxide formed by a thermal oxidation process, and the hard mask pattern 108 is made of silicon nitride.

In addition, a bit line structure 110 is provided on the substrate 100 of the cell region. The bit line structure 110 includes an insulating film pattern (not shown), a conductive film pattern 104, and a hard mask pattern 108. Among them, the conductive film pattern 104 is provided as a bit line. The bit line structure 110 has a line shape extending in a first direction.

The bit line structure 110 is made of the same material as the gate insulating film (not shown), the gate electrode 106, and the hard mask pattern 108 of the MOS transistor in the cell region, and has the same lamination structure. That is, the conductive film pattern 104 used as the bit line is made of the same material as the gate electrode 106 and has the same thickness.

The bit line 104 of the cell region and the gate electrode 106 of the ferrier circuit region preferably comprise a metal material having a low resistance. Specifically, the bit line 104 and the gate electrode 106 may comprise at least one of tungsten, tungsten nitride, and tungsten silicide. In this embodiment, the bit line 104 and the gate electrode 106 have a shape in which polysilicon and tungsten silicide are stacked.

And a first interlayer insulating film 114 covering the bit line structure 110 and the MOS transistor. A second interlayer insulating film 134 is formed on the first interlayer insulating film 114.

A first contact plug 136 that contacts the conductive film pattern 104 in the bit line structure 110 while passing through the second interlayer insulating film 134 and the first interlayer insulating film 114 located in the cell region do. A second contact plug 138 is provided which is in contact with the source / drain 118 of the MOS transistor while passing through the second interlayer insulating film 134 and the first interlayer insulating film 114 located in the ferrier circuit region.

The first and second contact plugs 136 and 138 are made of a metal material. In addition, a barrier metal material (not shown) is included on the surfaces of the first and second contact plugs 136 and 138. In this embodiment, the first and second contact plugs 136 and 138 are made of a barrier metal film (not shown) made of a titanium / titanium nitride film and tungsten.

A first conductive pad 144 is provided on the first contact plug 136. A third interlayer insulating film 154 is provided between the first conductive pads 144.

The first conductive pad 144 has the same function as raising the height of the first contact plug 136.

And a horizontal blade-shaped conductive beam 164 connected to the first conductive pad 144 and extending in a direction parallel to the substrate. Both ends of the conductive beam have a shape in which both end portions are lowered toward the substrate in the direction toward the substrate. The portion of the conductive beam 164 having a horizontal blade shape is spaced apart from the upper surface of the third interlayer insulating film 154.

Specifically, the conductive beam 164 includes an anchor portion 164a contacting the first conductive pad 144, a blade portion 164a extending in a direction parallel to the substrate 100 from the encompassing portion 164a, And a contact portion 164c positioned at both ends of the blade portion 164b and having a relatively low stepped portion in the direction toward the substrate 100. [

As shown, the blade portion 164b of the conductive beam 164 may have a slightly curved upper and lower surfaces. However, the upper and lower surfaces of the blade portion 164b may have a flat shape.

The conductive beam 164 must be made of a conductive material that moves mechanically by a potential difference. It should also be made of materials with elasticity and restitution. The material that can be used for the conductive beam 164 may be titanium nitride, carbon nanotubes, titanium, or the like. The conductive beam 164 may be a single layer or may have a stacked shape of two or more materials. In this embodiment, the conductive beam 164 is made of a titanium nitride film.

A word line 146 is provided to receive a signal for mechanically moving the conductive beam 164 while being spaced apart from the conductive beam 164. The word line 146 is located below the blade portion 164b of the conductive beam 164. In addition, the word line 146 is located between the third interlayer insulating film 154.

In addition, the upper surface of the word line 146 is flush with the upper surface of the first conductive pad 144. The word line 146 has a line shape extending in a second direction perpendicular to the first direction.

The word line 146 includes a metal material. The word line 146 may have the same stacking structure as the first conductive pad 144. In this embodiment, the word lines 146 are stacked with tungsten and titanium nitride films.

Capacitors 152 are provided that are electrically shorted or open with the conductive beam 164 as the conductive beam 164 mechanically moves.

Specifically, on the first interlayer insulating film 114, capacitors 152 are provided below the edge of the conductive beam 164. The capacitors have a shape in which the first electrode pattern 126, the dielectric film pattern 128, and the second electrode pattern 130a are stacked. The second electrode pattern 130a is provided on the upper side in terms of position but is functionally provided as a lower electrode. That is, the second electrode pattern 130a is electrically connected to the conductive beam 164 to receive charges. Also, the first electrode pattern 126 is provided at a lower position, but is functionally provided as an upper electrode.

The upper surface of the second electrode pattern 130a of the capacitor must be electrically shorted to the conductive beam 164 through the mechanical movement of the conductive beam 164.

The first electrode pattern 126 has a line shape extending in a second direction perpendicular to the first direction. Therefore, the upper electrodes of the capacitors of the respective cells arranged along the second direction are electrically connected.

The first electrode pattern 126 has a shape in which materials including a metal are stacked. For example, the first electrode pattern 126 may have a laminated structure of a metal film and a refractory metal film. The first electrode pattern 126 may have a laminated structure of a tungsten pattern and a titanium nitride film pattern. Also, a titanium / titanium nitride film pattern may be interposed as a barrier metal on the lower surface of the tungsten pattern.

In order to increase the capacitance of the capacitor 152, the dielectric film pattern 128 may be formed of a material having a high dielectric constant. For example, the dielectric layer pattern 128 may be formed of a material such as aluminum oxide, zirconium oxide, hafnium oxide, tantalum oxide, etc., and they may be used alone or in a stack of two or more. In this embodiment, the dielectric film pattern 128 has a shape in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated.

The second electrode pattern 130a includes a metal material. For example, the second electrode pattern 130a may have a laminated structure of a titanium nitride film pattern and a tungsten pattern.

The capacitor 152 may be surrounded by a second interlayer insulating film 134.

A second conductive pad 148 is formed on the second electrode pattern 130a. As shown, the upper surface of the second conductive pad 148 is preferably located in the same plane as the upper surface of the word line 146 and the first conductive pad 144. The second conductive pads 148 may be surrounded by the third interlayer insulating films 154.

The upper surface of the second conductive pad 148, which is a portion directly contacting the conductive beam 164, is made of the same material as the conductive beam 164. In this embodiment, since the conductive beam 164 is made of titanium nitride, the upper surface of the second conductive pad 148 is also provided with titanium nitride.

The upper surfaces of the first conductive pads 144, the second conductive pads 148 and the word lines 146 are located on the same plane and the third interlayer insulating film 154 is provided therebetween .

The end of the conductive beam 164 is positioned opposite the second conductive pad 148 in contact with the capacitor. Also, the end of the conductive beam 164 has a shape lowered toward the substrate 100. The gap between the conductive beam 164 and the upper surface of the second conductive pad 148 is therefore narrower than the gap between the conductive beam 164 and the word line 146.

Accordingly, the conductive beam 164 can easily contact the second conductive pad 148 by a signal applied to the word line 146. In addition, when the conductive beam 164 and the second conductive pad 148 are in contact with each other, a sufficient gap can be maintained between the conductive beam 164 and the word line 146. Therefore, it is possible to prevent a defect that the conductive beam 164 and the word line 146 are in contact with each other.

On the other hand, wirings 150 that are in electrical contact with the second contact plugs 138 are provided on the second interlayer insulating film 134 of the ferrier circuit region. The wires 150 may be formed of the same material as the word line 146 and the first and second conductive pads 144 and 148. A third interlayer insulating film 154 is provided between the wirings 150.

A cell of a DRAM device according to an embodiment of the present invention includes a word line 146 and a conductive beam 164 mechanically moving by the word line 146, A bit line 104 and a capacitor 152 shorted or open with the conductive beam 164 by movement of the conductive beam 164.

In addition, since the gap between the conductive beam 164 and the word line 146 is kept relatively wide, the capacitor 152 and the conductive beam 164 are short-circuited by the movement of the conductive beam 164 It is possible to prevent the conductive beam 164 and the word line 146 from being shorted to each other.

The DRAM device according to the present embodiment writes or reads data to or from the capacitor 152 by contacting or non-contacting the conductive beam 164 with the capacitor 152.

Further, in the DRAM device according to the present embodiment, since the switching device and the capacitor 152 are kept in a non-contact state in the standby state, the leakage of the charge stored in the capacitor 152 is greatly reduced. Therefore, the refresh operation can be omitted or the refresh cycle can be greatly increased.

Also, since the leakage of the charge stored in the capacitor 152 is reduced, the capacitance of the capacitor 152 can be reduced. That is, even if the capacitance is reduced, the data stored in the cell can be more easily distinguished by the charge stored in the capacitor 152. In this way, since the capacitance of the capacitor 152 can be reduced, the capacitor 152 can have excellent operation characteristics even if the lower electrode does not have a cylinder shape and the upper and lower electrodes are stacked.

FIGS. 2 to 15 are cross-sectional views for explaining one method for fabricating the DRAM device according to the first embodiment of the present invention.

Referring to FIG. 2, a substrate 100 in which a ferrier circuit region and a cell region are separated is provided. The substrate 100 includes a single crystal silicon substrate or an SOI substrate. In this embodiment, a single crystal silicon substrate 100 is used.

The substrate 100 in the ferrier circuit region is subjected to a shell row trench element isolation process to form a device isolation pattern 102a. That is, a portion corresponding to the device isolation region is selectively etched in the ferrier circuit region to form a trench, and an isolation material is filled in the trench and polished to form a device isolation pattern 102a.

When the device isolation pattern 102a is formed only in the substrate 100 of the ferrite circuit region, the substrate 100 of the cell region is dishing (dishing) when the device isolation pattern 102a is formed, ) Phenomenon may occur. Also, a dishing phenomenon may occur on the upper surface of the element isolation pattern 102a in the ferrite circuit area.

Therefore, a dummy pattern 102b is also formed in the cell region in the step of forming the element isolation pattern 102a in the ferrier circuit region. That is, when a trench is formed in the ferrite circuit region, a trench is formed in the cell region at regular intervals, and a dummy pattern 102b is formed in the trench by performing insulation material deposition and polishing.

By forming the dummy pattern 102b, it is possible to reduce the dishing phenomenon in which the substrate is locally excessively broken. However, the dummy pattern 102b does not serve to electrically separate the elements, unlike the element isolation pattern 102a in the ferrier circuit region. Therefore, when the device isolation process is performed in the ferrier circuit region, the substrate dummy pattern 102b in the cell region may not be formed if the dishing is hardly generated.

Although not shown, when an SOI substrate is used as the substrate 100, a separate trench isolation process is not required. That is, the device isolation region is defined only by patterning the silicon located in the ferrier circuit region.

Referring to FIG. 3, an insulating film, a conductive film, and a hard mask film are formed on the substrate 100.

The insulating film formed in the ferrier circuit region may be used as a gate insulating film. The gate insulating film may be silicon oxide formed by thermally oxidizing the substrate.

The conductive film is formed as a bit line in the cell region through a subsequent process, and as a gate electrode in the ferrier circuit region. In order to use the conductive film as a bit line, it must be formed of a material having a low resistance. Therefore, it is preferable that the conductive film includes a metal material. In this embodiment, the conductive film has a laminated structure of polysilicon and tungsten silicide. Alternatively, however, it may be formed of a laminated structure of a polysilicon and a metal material or a metal material alone.

Thereafter, the hard mask film 108 is formed by patterning the hard mask film. The hard mask pattern 108 formed on the cell region has a line shape extending in the first direction. In addition, the hard mask pattern 108 of the ferrier circuit region is formed at a portion where the gate electrode is to be formed. The hard mask pattern 108 may be formed by depositing silicon nitride by a chemical vapor deposition method and then patterning through a photolithography process.

The conductive film is etched using the hard mask pattern 108 as an etching mask. Thus, a bit line structure 110 in which an insulating film (not shown), a bit line 104, and a hard mask pattern 108 are stacked is formed in the cell region. A gate structure 112 in which a gate insulating film (not shown), a gate electrode 106, and a hard mask pattern 108 are stacked is formed in the ferrier circuit region.

An insulating film (not shown) for a spacer is formed on the substrate on which the bit line structure 110 and the gate structure 112 are formed. The spacer insulating film may be formed by depositing silicon nitride. Thereafter, the spacer insulating film is anisotropically etched to form spacers 116 on the sidewalls of the bit line structure 110 and the gate structure 112.

Next, the source / drain 118 is formed by implanting impurities below the substrate surface on both sides of the gate structure 112.

The source / drain of the LDD structure may be formed by performing a process of implanting impurities at a low concentration below the surface of the substrate on both sides of the gate structure 112 before forming the spacer 116.

Referring to FIG. 4, a first interlayer insulating film 114 covering the gate structure 112 and the bit line structure 110 is formed. The first interlayer insulating film 114 may be formed by forming silicon oxide through a chemical vapor deposition process and planarizing the upper surface.

A first electrode layer 120, a dielectric layer 122, and a second electrode layer 124 are formed on the first interlayer insulating layer 114 as a capacitor. The first and second electrode films 120 and 124 may include a metal. In addition, the dielectric layer 122 may include a metal oxide having a high dielectric constant.

Specifically, the barrier metal layer 120a, the tungsten layer 120b, and the titanium nitride layer 120c are formed as the first electrode layer 120. The barrier metal layer 120a may be formed by depositing a titanium / titanium nitride layer.

As the dielectric layer 122, aluminum oxide, zirconium oxide, hafnium oxide, tantalum oxide, or the like can be used. These may be used alone or may be formed by stacking two or more of them. For example, the dielectric film can be formed by sequentially stacking aluminum oxide, zirconium oxide, and aluminum oxide. In this way, the capacitance of the capacitor can be increased by using a dielectric film having a high dielectric constant.

The titanium nitride film 124a and the tungsten film 124b are formed as the second electrode film 124.

That is, the titanium nitride films 120c and 124a may be used as materials that substantially function as the upper and lower electrodes while being in contact with the dielectric film 122. [ Thus, when the dielectric film 122 is formed of a metal oxide having a high dielectric constant and the titanium nitride films 120c and 124a are used as the upper and lower electrodes, the leakage current of the capacitor is reduced and better electrical characteristics are exhibited.

Referring to FIG. 5, a first mask pattern (not shown) is formed on the second electrode film 124. The first mask pattern has a line shape extending in a second direction perpendicular to the first direction.

The second electrode film 124, the dielectric film 122, and the first electrode film 120 are sequentially etched using the first mask pattern to form a line-shaped preliminary capacitor 132 extending in the first direction do. The preliminary capacitor 132 has a shape in which a first electrode pattern 126, a dielectric film pattern 128, and a preliminary second electrode pattern 130 are stacked. The preliminary capacitors 132 are sufficiently spaced such that a first contact plug and two bit lines may be provided between the preliminary capacitors 132 having a line shape. Thereafter, the first mask pattern is removed.

Referring to FIG. 6, an insulating film for burying a portion between the preliminary capacitors 132 is formed. The insulating layer may be formed by depositing silicon oxide through a chemical vapor deposition process. Thereafter, the second interlayer insulating film 134 is formed by polishing the insulating film so that the upper surface of the preliminary second electrode pattern 130 is exposed.

Next, on the second interlayer insulating film 134, a contact hole exposing the upper surface of the bit line 104 and a second contact hole exposing the upper surface of the source / drain 118 are formed. Thereby forming a mask pattern (not shown). That is, the second mask pattern exposes a part of the second interlayer insulating film 134 located between the preliminary capacitors 132 in the cell region, and in the ferrier circuit region, the source / A part of the second interlayer insulating film 134 is exposed.

The second interlayer insulating film 134 and the first interlayer insulating film 114 are sequentially etched using the second mask pattern as an etching mask. In addition, the hard mask pattern 108 included in the bit line structure 110 is etched. A first contact hole exposing the bit line 104 is formed on the bottom surface of the cell region, and a second contact hole exposing the substrate corresponding to the source / drain 118 is formed on the bottom surface of the ferrite circuit region. Thereby forming a hole.

Unlike the above description, the first and second contact holes may be formed through a separate etching process. However, when the first and second contact holes are formed through separate etching processes, the process for forming the mask pattern must be performed twice, which complicates the process.

Thereafter, conductive material is deposited and planarized in the first and second contact holes to form a first contact plug 136 in the cell region and a second contact plug 138 in the ferrier circuit region. The first and second contact plugs 136 and 138 include a metallic material.

Specifically, a barrier metal film (not shown) is formed on the sidewalls and bottom surfaces of the first and second contact holes. The barrier metal film may be formed by depositing a titanium / titanium nitride film. A tungsten film (not shown) is deposited on the barrier metal film to fill the inside of the first and second contact holes. Thereafter, the first and second contact plugs 136 and 138 are formed by polishing the tungsten film so that the surfaces of the second interlayer insulating film 134 and the preliminary second electrode pattern are exposed.

7, a conductive film (not shown) for forming a word line on the first contact plug 136, the second contact plug 138, the second preliminary electrode pattern 130, and the second interlayer insulating film 134 Not shown). The conductive film includes a metal material.

It is preferable that the conductive film has a structure in which two layers are stacked. Specifically, a portion of the conductive film directly contacting the first and second contact plugs 136 and 138 and the second preliminary electrode pattern 130 (that is, a lower layer film) improves the adhesion property and decreases the contact resistance The first and second contact plugs 136 and 138 and the second preliminary electrode pattern 130 are formed of the same metal material as the upper surfaces of the first and second contact plugs 136 and 138 and the second preliminary electrode pattern 130. That is, the lower layer film in the conductive film may be formed of a tungsten film.

On the other hand, a portion of the upper layer film in the conductive film is in direct contact with the conductive beam formed in the subsequent process. Therefore, it is preferable that the upper layer film in the conductive film is formed of the same material as the conductive beam in order to improve the contact property with the conductive beam. In this embodiment, the upper film in the conductive film is formed of titanium nitride.

A first conductive pad connected to the word line, the first contact plug 136, a second conductive pad connected to the preliminary capacitor 132, and a second conductive plug connected to the second contact plug 138 of the ferrite circuit region, Thereby forming a second hard mask pattern 142 used as a mask for patterning the wirings. The second hard mask pattern 142 may be formed of silicon nitride.

In detail, the second hard mask pattern 142 for patterning the word line has a line shape extending between the first contact plug 136 and the capacitor and extending in the second direction. The second hard mask pattern 142 for forming the first conductive pad has an isolated pattern shape facing the first contact plug 136. The second hard mask pattern 142 for forming the second conductive pad has an isolated pattern shape opposite to the preliminary second electrode pattern 130.

As shown in the figure, the second hard mask pattern 142 for forming the second conductive pad may be formed to have a narrower line width than the preliminary second electrode pattern 130. Alternatively, the second hard mask pattern 142 may be formed to have the same line width as the preliminary second electrode pattern 130.

In addition, the second hard mask pattern 142 formed in the ferrier circuit region has a shape facing the second contact plug 138.

Referring to FIG. 8, the conductive film is etched using the second hard mask pattern 142 as an etch mask. A first conductive pad 144, a word line 146, and a second conductive pad 148 are formed in the cell region through the etching process, and a wiring 150 is formed in the ferrier circuit region.

Subsequently, the preliminary second electrode pattern 130 exposed in the cell region is etched to form a second electrode pattern 130a having an isolated shape. That is, the second electrode patterns 130a having an isolated shape are formed by removing a portion of the line-shaped preliminary second electrode patterns 130 extending in the second direction.

Thus, the capacitor 152 including the first electrode pattern 126 having a line shape extending in the second direction, the dielectric film pattern 128, and the second electrode pattern 130a having an isolated shape is completed. Therefore, the capacitors 152 arranged in the second direction share the first electrode patterns 126 with each other.

Since the first conductive pad 144, the word line 146, and the second conductive pad 148 are formed through the same deposition process and patterning process, the first conductive pad 144, the word line 146, and the second conductive pad 148 are formed of the same material.

Referring to FIG. 9, an insulating film is formed to fill the gap between the second hard mask patterns 142. Thereafter, the third interlayer insulating film 154 is formed by polishing the insulating film so that the upper surface of the second hard mask pattern 142 is exposed.

After the third interlayer insulating film 154 is formed, the remaining second hard mask pattern 142 is removed.

10, a first sacrificial layer 156 is formed on the third interlayer insulating layer 154, the word line 146, the first and second conductive pads 144 and 148, and the wirings 150 . The first sacrificial layer 156 is formed by depositing a conductive layer and a material having an etch selectivity.

Examples of the material that can be used as the first sacrificial layer 156 include polysilicon, silicon oxide, and the like. When the silicon oxide is formed by the first sacrificial layer 156, the third interlayer insulating layer 154 may be etched faster than the third interlayer insulating layer 154 because the structure is less dense than the third interlayer insulating layer 154 .

The thickness of the first sacrificial layer 156 is the difference between the gap between the conductive beam and the word line 146 and the gap between the conductive beam and the second conductive pad 148. That is, the gap between the conductive beam and the word line 146 is wider than the gap between the conductive beam and the second conductive pad 148 by the thickness of the first sacrificial layer 156.

Referring to FIG. 11, a portion of the first sacrificial layer 156 formed on the second conductive pad 148 is removed through an etching process to form a first preliminary sacrificial layer pattern 156a.

That is, through the etching process, the first sacrificial layer 156 corresponding to the contact portion of the conductive beam formed in the subsequent process is etched to form the first preliminary sacrificial layer pattern 156a.

Referring to FIG. 12, a second sacrificial layer 158 covering the first preliminary sacrificial layer pattern 156a and the second conductive pad 148 is formed. The second sacrificial layer 158 is formed by depositing a material having an etch selectivity with respect to a conductive layer to be formed later. The second sacrificial layer 158 may be formed of the same material as the first sacrificial layer pattern 156a or may be formed of a different material from the first sacrificial layer pattern 156a. For example, the first preliminary sacrificial layer pattern 156a may be formed of silicon oxide, and the second sacrificial layer 158 may be formed of a polysilicon layer.

The thickness of the second sacrificial layer 158 is the same as the gap between the contact portion of the conductive beam formed in the subsequent process and the upper surface of the second conductive pad 148.

Referring to FIG. 13, the second sacrificial layer 158 and a portion of the first preliminary sacrificial pattern 156a are sequentially etched to form an opening 160 exposing the upper surface of the first conductive pad 144 . Also, a first sacrificial pattern 156b and a second sacrificial pattern 158a are formed to expose the upper surface of the first conductive pad 144 through the etching process.

The opening 160 may have a contact hole shape exposing the first conductive pad 144. Alternatively, the opening 160 may have a trench shape that exposes the first conductive pads 144 disposed in the second direction on the bottom surface. In the present embodiment, it is described that the opening 160 has a trench shape extending in the second direction.

Referring to FIG. 14, a conductive film (not shown) for forming a conductive beam on the second sacrificial film pattern 158a is formed while filling the opening 160. The conductive film should be made of a material that moves mechanically by a potential difference. It should also be made of materials with elasticity and restitution. Therefore, materials that can be used as the conductive film include titanium nitride film, carbon nanotube, titanium, etc., and they may be formed as a single layer, or two or more materials may be laminated. In this embodiment, a titanium nitride film is used.

Thereafter, the conductive film is patterned to form a conductive beam 164 opposed to the word line 146 and the second conductive pad 148. At this time, the edge portion of the conductive beam 164 extends to a portion facing the upper portion of the second conductive pad 148. The conductive beam 164 is formed to face the bit line 104 and has an isolated pattern shape.

The conductive beam 164 formed through the above process has an encompassing portion 164a contacting with the first conductive pad 144, a blade portion 164b extending in a direction parallel to the substrate 100, And a contact portion 16c which is provided at both ends and has a shape lowered toward the substrate.

As shown in the figure, first and second sacrificial layer patterns 156a and 158a are interposed between the third interlayer insulating layer 154 and the word line 146 and the conductive beam 164. On the other hand, only the second sacrificial film pattern 158a is interposed between the second conductive pad 148 and the conductive beam 164. Therefore, both ends of the conductive beam 164 are shaped to be lowered toward the substrate 100.

Referring to FIG. 15, the first and second sacrificial film patterns 156a and 158a are removed to complete the DRAM device.

If the first and second sacrificial layer patterns 156a and 158a are formed of the same material, the first and second sacrificial layer patterns 156a and 158a may be removed by one etching process. Alternatively, if the first and second sacrificial layer patterns 156a and 158a are formed of different materials, the first and second sacrificial layer patterns 156a and 158a may be removed through two etching processes .

The removal of the first and second sacrificial film patterns 156a and 158a is preferably performed through a wet etching process. However, the first and second sacrificial film patterns 156a and 158a may be removed through isotropic dry etching or the like.

When the first and second sacrificial film patterns 156a and 158a are removed, the conductive beam 164 and the word line 146 and the conductive beam 164 and the second conductive pad 148 are spaced apart from each other .

The gap d1 between the conductive beam and the word line is wider than the gap d2 between the conductive beam 164 and the second conductive pad 148. [

The contact portion 164c of the conductive beam 164 is brought into contact with or not in contact with the second conductive pad 148 in accordance with the voltage applied to the word line 146. [ When the conductive beam 164 contacts the second conductive pad 148, an electrical signal applied through the bit line 106 is transferred to the capacitor 152 or data stored in the capacitor 152 is transferred to the bit line 106. [ And may be output via line 106.

As described above, according to the method of this embodiment, it is possible to manufacture a DRAM device in which a MOS transistor is provided in the ferrier circuit area and a switching device that performs a mechanical operation in the cell area. Particularly, the patterning process for forming the MOS transistor in the ferrier circuit region and the bit line forming process for the cell region are simultaneously performed. Further, the metal wiring process of the ferrite circuit region and the switching device performing the mechanical operation are simultaneously formed. Therefore, the DRAM device can be manufactured through a simple process.

FIGS. 16 and 17 are cross-sectional views for explaining another method for manufacturing the DRAM device according to the first embodiment of the present invention.

The manufacturing method of the DRAM device described below is the same as the manufacturing method described above except for a series of steps for forming the conductive beam. Therefore, the following description will be given only to the parts different from the manufacturing method described above. The same reference numerals are used for the same components.

The same process as described with reference to Figs. 2 to 10 is performed to form the structure shown in Fig.

Referring to FIG. 16, a second sacrificial layer (not shown) is formed to cover the first sacrificial layer 156. The second sacrificial layer is formed by depositing a material having an etch selectivity with the conductive film to be formed later. The second sacrificial layer 156 may be formed of a different material from the first sacrificial layer 156. For example, the first sacrificial layer 156 may be formed of silicon oxide, and the second sacrificial layer may be formed of a polysilicon layer. The thickness of the second sacrificial layer is the same as the gap of the conductive beam formed by the second conductive pad 148 and the subsequent process.

Next, a second preliminary sacrificial layer pattern 170 is formed by selectively etching a portion of the second sacrificial layer opposed to the second conductive pad 148.

Only the first sacrificial layer 156 is formed on the second conductive pad 148 and the first sacrificial layer 156 and the second sacrificial layer 156 are formed on the third interlayer insulating layer 154 and the word line 146. In this case, 2 preliminary sacrificial film pattern 170 is covered.

17, an opening 160 exposing the upper surface of the first conductive pad 144 is formed by sequentially etching a portion of the second preliminary sacrificial film pattern 170 and the first sacrificial layer 156 . In addition, a first sacrificial pattern 157 and a second sacrificial pattern 170a are formed to expose the upper surface of the first conductive pad 144 through the etching process.

Thereafter, the conductive beam 164 is formed in the same manner as described with reference to Figs. 14 and 15, and the first and second sacrificial film patterns 157 and 170a are removed. Thereby, the DRAM device shown in Fig. 1 is completed.

FIGS. 18 to 20 are cross-sectional views for explaining another method for manufacturing the DRAM device according to the first embodiment of the present invention.

The manufacturing method of the DRAM device described below is the same as the manufacturing method described with reference to FIGS. 2 to 16 except for a series of steps for forming the conductive beam. Therefore, the following description will be given only to the parts different from the manufacturing method described above. The same reference numerals are used for the same components.

The same process as described with reference to Figs. 2 to 9 is performed to form the structure shown in Fig.

18, a preliminary sacrificial layer 180 is formed on the third interlayer insulating layer 154, the word line 146, the first and second conductive pads 144 and 148, and the wirings 150. Referring to FIG. do. The preliminary sacrificial layer 180 is formed by depositing a material having an etch selectivity with respect to a conductive layer to be formed later.

Examples of the material that can be used as the preliminary sacrificial layer 180 include polysilicon, silicon oxide, and the like. When the silicon oxide is formed as the preliminary sacrificial layer 180, the third interlayer insulating layer 154 may be etched faster than the third interlayer insulating layer 154 because the structure is less dense than the third interlayer insulating layer 154.

The thickness of the preliminary sacrificial layer 180 is the same as the gap between the conductive beam formed subsequently and the word line 146. Therefore, the preliminary sacrificial layer 180 should be formed thicker than the first sacrificial layer in the process described with reference to FIG.

Referring to FIG. 19, an etch mask pattern (not shown) for selectively exposing the upper portion of the second conductive pad 148 is formed on the preliminary sacrificial layer 180. The etch mask pattern may be formed of a photoresist pattern.

The sacrificial layer 180a is formed by partially etching the preliminary sacrificial layer 180 located on the second conductive pad 148 using the etch mask pattern. The etching process may be performed by wet etching or dry etching.

At this time, since only a part of the thickness of the preliminary sacrificial layer 180 is etched, the completed sacrificial layer 180a has a relatively thin thickness on the second conductive pad 148.

Thereafter, the etching mask pattern is removed.

Referring to FIG. 20, an opening 160 exposing the top surface of the first conductive pad 144 is formed by sequentially etching a portion of the sacrificial layer 180a. Also, a sacrificial pattern 180b exposing the upper surface of the first conductive pad 144 is formed through the etching process.

Thereafter, the conductive beam 164 is formed in the same manner as described with reference to Figs. 14 and 15, and the sacrificial film pattern 180b is removed. Since the sacrificial layer pattern 180b is formed of a single material, it can be removed through one etching process. By performing the above processes, the DRAM device shown in FIG. 1 is completed.

21 to 23 are cross-sectional views for explaining another method for manufacturing the DRAM device according to the first embodiment of the present invention.

The manufacturing method of the DRAM device described below is the same as the manufacturing method described with reference to Figs. 2 to 15 except for a series of steps for forming a conductive beam. Therefore, the following description will be given only to the parts different from the manufacturing method described above. The same reference numerals are used for the same components.

The same process as described with reference to Figs. 2 to 9 is performed to form the structure shown in Fig.

21, a preliminary sacrificial layer 190 is formed on the third interlayer insulating layer 154, the word line 146, the first and second conductive pads 144 and 148, and the wirings 150. Referring to FIG. do. The preliminary sacrificial layer 190 is formed by depositing polysilicon. The thickness of the preliminary sacrificial layer 190 is the same as the gap between the conductive line formed in the subsequent process and the word line 146. Therefore, the preliminary sacrificial layer 190 should be formed thicker than the first sacrificial layer in the process described with reference to FIG.

Referring to FIG. 22, a hard mask pattern (not shown) for selectively exposing the upper portion of the second conductive pad 148 is formed on the preliminary sacrificial layer 190. The hardmask pattern may comprise silicon nitride.

The portion exposed by the hard mask pattern is oxidized to form a silicon oxide layer 192 on a part of the preliminary sacrificial layer 190. Under the silicon oxide film, the preliminary sacrificial layer 190 is left to a certain thickness.

Through the oxidation process, the preliminary sacrificial layer 190 becomes a sacrificial layer 190a having a relatively thin thickness on the second conductive pad 148. [

Referring to FIG. 23, the silicon oxide layer 192 and the hard mask pattern are selectively removed. Preferably, the removal process is performed by wet etching. The sacrificial layer 190a has a relatively low thickness on the second conductive pad 148. [

Next, an opening 160 exposing the upper surface of the first conductive pad 144 is formed by sequentially etching a portion of the sacrificial layer 190a. Also, a sacrificial pattern 190b exposing the upper surface of the first conductive pad 144 is formed through the etching process.

Thereafter, the conductive beam 164 is formed in the same manner as described with reference to Figs. 14 and 15, and the sacrificial film pattern 190b is removed. Since the sacrificial layer pattern 190b is formed of a single material, the sacrificial layer pattern 190b may be removed through a single etching process. By performing the above processes, the DRAM device shown in FIG. 1 is completed.

Example 2

24 is a cross-sectional view showing a DRAM device according to a second embodiment of the present invention.

The DRAM device of the second embodiment described below is the same as the DRAM device of the first embodiment except that the cells are repeatedly stacked over the substrate.

That is, since the MOS transistor is not provided in the DRAM cell, the cell can be formed not only on the semiconductor substrate but also on the insulating film. Therefore, the DRAM cells of the first embodiment are provided on the substrate, and DRAM cells having the same structure are provided on the insulating film covering the DRAM cells. Referring to Fig. 16, a description will be given in detail of a DRAM device according to a second embodiment.

Referring to FIG. 24, a ferrite circuit and a DRAM cell are provided on a substrate 100 whose surface is made of a semiconductor material. The ferry circuit and the DRAM cell have the same configuration as the DRAM device of the first embodiment. In particular, in the DRAM cell, the conductive beam 164 has horizontal blades whose both ends are lowered toward the substrate.

A MOS transistor can not be formed in the insulating film formed on the substrate. Therefore, the ferry circuits including the MOS transistor must be formed on the substrate. Therefore, the ferrier circuit region of the substrate is formed with ferrier circuits for driving the DRAM cells stacked on the substrate.

In the DRAM cell of the first embodiment, a fourth interlayer insulating film 154 is formed on the third interlayer insulating film 154 and the wirings 150 and is formed on the upper, lower and side portions of the conductive beam 164, An insulating film 204 is provided. That is, the fourth interlayer insulating film 204 is not formed around the conductive beam 164 so as to provide a space 161 for allowing the conductive beam 164 to move up and down.

The fourth interlayer insulating film 204 may be formed of an insulating material having fine pores 206 or containing fine patterns. The pores 206 and the spacing of the patterns are sized to allow the etchant to penetrate. Specifically, the spacing of the pores 206 and the patterns is preferably 10 to 50 nm.

A fifth interlayer insulating film 208 is provided on the fourth interlayer insulating film 204. The fifth interlayer insulating film 208 has a shape such that pores 206 included in the fourth interlayer insulating film 204 and patterns between the patterns are not buried or partially buried.

A two-layer bit line structure 214 is provided on the fifth interlayer insulating film 208. The two-layer bit line structure 214 has a structure in which a two-layer bit line 210 and a two-layer hard mask pattern 212 are stacked. That is, unlike the bit line structure 214 located on the substrate, no separate insulating film pattern is provided below the two-layer bit line 210.

A two-layer contact plug 218, a two-layer first conductive pad 222, a two-layer word line 224, a two-layer capacitor 220 and a two-layer second conductive pad 222 are formed on the two- (226). The two-layer contact plug 218, the two-layer first conductive pad 222, the two-layer word line 224, the two-layer capacitor 220 and the two-layer second conductive pad 226 are formed on the substrate And has the same structure as the first contact plug 136, the first conductive pad 144, the word line 146, the capacitor 152, and the second conductive pad 148.

On the two-layer bit line structure 214 and the fifth interlayer insulating film 208, two layers having the same structure as the first through third interlayer insulating films 114, 134, and 154 formed on the substrate 100 First to third interlayer insulating films 216, 228 and 230 are provided.

That is, two-layer cells having the same shape as the cell formed on the substrate 100 are provided on the fifth interlayer insulating film 208. On the other hand, on the fifth interlayer insulating film 208, MOS transistors for forming a ferrier circuit are not provided.

Although not shown, two-layered fourth and fifth interlayer insulating films having the same structure as the fourth interlayer insulating film 204 and the fifth interlayer insulating film 208 may be provided on the two-layered cells. Further, on the two-layer fifth interlayer insulating film, three-layer cells having the same structure as the two-layer cells may be provided. In this way, cells having the same structure as that formed on the substrate can be stacked in a plurality of layers.

25 and 26 are cross-sectional views for explaining a method of manufacturing the DRAM according to the second embodiment of the present invention.

The method of forming the ferrier circuits and the cells on the substrate in the DRAM device according to the second embodiment of the present invention is very similar to the method of manufacturing the DRAM device of the first embodiment. Therefore, redundant description will be omitted.

First, the structure shown in Fig. 14 is completed by performing the same process as described with reference to Fig. 4 to Fig.

Referring to FIG. 25, a third sacrificial layer 200 is additionally formed on the conductive beam 164 and the second sacrificial layer pattern 158a. The third sacrificial layer 200 may be formed of the same material as the second sacrificial layer pattern 158a.

The third sacrificial layer 200 is removed through a subsequent process to create a space between the conductive beam 164 and the interlayer insulating layer located on the conductive beam 164. That is, by adjusting the thickness of the third sacrificial layer 200, the interval between the conductive beam 164 and the interlayer insulating layer formed on the upper portion can be adjusted.

The second sacrificial layer pattern 156 and the third sacrificial layer are patterned such that the second sacrificial layer pattern 156 and the third sacrificial layer 200 are left only on the upper portion and the sidewall portion and the lower portion of the conductive beam 164 . Thereby, a sacrificial film structure in which the first to third sacrificial film patterns are stacked is formed. The sacrificial film structure has an isolated shape covering the conductive beam 164 and its periphery. The third interlayer insulating film 154, the second conductive pad 148, and the wiring 150 are exposed at portions where the sacrificial film structure is not formed.

Referring to FIG. 26, a fourth interlayer insulating film 204 is formed on the sacrificial film structure, the third interlayer insulating film 154, the second conductive pad 148, and the wiring 150. The fourth interlayer insulating film 204 may be formed of an insulating material having fine pores 206 or containing fine patterns. The pores 206 and the spacing of the patterns are sized to allow the etchant to penetrate. Specifically, the interval between the pores and the patterns is preferably 10 to 50 nm.

For example, the fourth interlayer insulating film 204 may be formed of a self-assembling block copolymer. In addition, the fourth interlayer insulating film 204 may have a repeating pattern shape having an interval of about 20 nm or a shape of holes of 20 nm. The self-assembly block copolymer includes polystyrene, polymethylmethacrylate (PMMA), and the like.

An etchant for etching the sacrificial film structure is supplied to a structure having the fourth interlayer insulating film 204 formed thereon. The etchant is supplied through pores 206 and a pattern interval included in the fourth interlayer insulating film 204, thereby removing the sacrificial film structure.

As described above, the sacrificial film structure is removed so that the conductive beam 164 and the word line 146 and the second conductive pad 148 are separated from each other. Further, the conductive beam 164 and the fourth interlayer insulating film 204 are also separated from each other. Thus, the conductive beam 164 is moved up and down according to the voltage of the word line 146 by generating the space 161 on the upper, lower and side portions of the conductive beam 164.

Referring again to FIG. 24, a fifth interlayer insulating film 208 is formed on the fourth interlayer insulating film 204. The fifth interlayer insulating film 208 is formed so as not to fill the pores 206 of the fourth interlayer insulating film 204, or to fill only a part of the pattern space. That is, the fifth interlayer insulating film 208 is formed by depositing an insulating material through a deposition process with a poor step coverage characteristic. The fifth interlayer insulating film 208 may be formed of silicon oxide.

The fifth interlayer insulating film 208 functions as a substrate of cells formed in two layers. Thus, since the DRAM cells of this embodiment are formed on the insulating film, a process of forming a semiconductor material film is not required. Therefore, it is possible to easily stack the cells in a multiple layer.

A two-layer bit line structure 214 is formed on the fifth interlayer insulating film 208. The two-layer bit line structure 214 may be formed by forming a conductive film and a hard mask film, and then patterning the conductive film and the hard mask film. Therefore, the two-layer bit line structure 214 has a stacked structure of a two-layer bit line 210 and a two-layer hard mask pattern 212. In addition, the two-layer bit line structure 214 has a line shape extending in the same direction as the bit line structure 110 formed on the substrate 100.

MOS transistors constituting a ferrier circuit are not formed on the fifth interlayer insulating film 208. Therefore, as shown, no gate structure is formed on the fifth interlayer insulating film 208, and only the DRAM cells are formed.

Next, a two-layer contact plug 218, a two-layer first conductive pad 222, a two-layer word line 224, a two-layer contact plug 218, and a second conductive layer 222 are formed by performing the same process as described with reference to FIGS. Layer capacitor 220, a two-layer second conductive pad 226, a two-layer conductive beam 232, and two-layer first to third interlayer insulating films 216, 228 and 230 are formed.

Thereby, a DRAM device having a two-layer structure is completed.

Although not shown, the same processes as those described above are repeatedly performed on the two-layered third interlayer insulating film 230 to form the DRAM cells stacked in two or more layers.

Example 3

FIG. 27 is a cross-sectional view showing a DRAM device according to a third embodiment of the present invention. FIG.

The cells of the DRAM device according to the third embodiment have the same configuration as those of the first embodiment. However, the ferry circuit of the third embodiment uses a mechanical switching element instead of the MOS transistor as the switching element.

Referring to FIG. 27, a substrate 300 in which a ferrier circuit region and a cell region are separated is provided. Since the DRAM device according to the present embodiment has a mechanical switching element instead of a MOS transistor in the ferrite circuit area, the substrate may not be made of a semiconductor material. Accordingly, at least the upper surface of the substrate 300 includes an insulating material.

A DRAM cell having the same structure as that of the first embodiment is provided on the substrate 300 of the cell region. However, in this embodiment, the bit line structure 306 formed on the substrate 300 may not have an insulating film pattern at the bottom.

Since the substrate of the cell region is provided with a DRAM cell having the same configuration as that of Embodiment 1, only the ferrier circuits located on the substrate of the ferrier circuit region will be described below.

First wirings 308 are provided on the substrate of the ferrite circuit region. The first wirings 308 apply an external electrical signal through a mechanical switching element in the ferrite circuit area or output a signal through the mechanical switching element. The first wirings 308 may have the same lamination structure as the bit line structure 306.

First and second interlayer insulating films 310 and 322 are formed to cover the first wirings 308.

Second contact plugs 326 electrically connected to the first wires 308 are formed in the first and second interlayer insulating layers 310 and 322. The second contact plug 326 may be made of the same material as the first contact plug 324 located in the cell region.

On the second contact plug 326, a switching element having the same configuration as that of the switching element of the DRAM cell is provided.

Specifically, a third conductive pad 334 is provided on the second contact plug 326, and a third interlayer insulating layer 340 is provided between the third conductive pads 334. A second conductive beam 342b in the form of a horizontal blade connected to the third conductive pad 334 and extending laterally to be parallel to the substrate 300 is provided. In particular, the second conductive beam 342b has a horizontal blade shape with both ends lowered toward the substrate.

Also provided is a conductive line 336 spaced from the second conductive beam 342b and positioned below the second conductive beam 342b and adapted to receive a signal for mechanically moving the second conductive beam 342b .

And a second wire 338 contacting the edge portion of the second conductive beam 342b when the second conductive beam 342b descends. The second wiring 338 is electrically connected to or isolated from the first wiring 308 by driving the second conductive beam 342b.

In this manner, when the mechanical switching element is formed in the ferrier circuit region, the substrate 300 may not be formed of a semiconductor material. Therefore, although not shown, it is possible to easily implement a DRAM device which is stacked vertically in the same shape as that formed on the substrate.

28 is a cross-sectional view for explaining a method of manufacturing a DRAM device according to a third embodiment of the present invention.

Since the cells of the DRAM device according to the third embodiment have the same configuration as that of the first embodiment, the processes for forming the cells are almost the same. However, the ferrier circuit of the third embodiment uses a mechanical switching element instead of the MOS transistor as the switching element, so that there is a difference in the process performed to form the ferrier circuit.

Referring to FIG. 28, a substrate 300 in which a ferrier circuit region and a cell region are separated is provided. At least the surface of the substrate 300 is made of an insulating material.

A conductive film and a hard mask pattern 304 are formed on the substrate 300. The hard mask pattern 304 formed on the cell region has a line shape extending in the first direction. In addition, the hard mask pattern 304 of the ferrite circuit region is formed in the first wiring region.

The conductive film is etched using the hard mask pattern 304 as an etch mask to form a bit line 302 in the cell region and a first wiring 308 in the ferrier circuit region.

A first interlayer insulating film 310 covering the bit line 302 and the first wiring 308 is formed. The first electrode pattern 312, the dielectric layer 314, and the second preliminary electrode pattern 314 have a line shape extending in a second direction perpendicular to the bit line 302 on the first interlayer insulating film 310 of the cell region. Thereby forming the stacked preliminary capacitors. Thereafter, a second interlayer insulating film 322 is formed between the preliminary capacitors.

A contact hole to be connected to the bit line 302 and contact holes to be connected to the first wiring 308 are formed in the second interlayer insulating film 322. A first contact plug 324 connected to the bit line 302 and a second contact plug 326 connected to the first wiring 308 are formed by embedding a conductive material in the contact holes .

Next, a conductive film and a hard mask pattern are deposited on the first and second contact plugs 324 and 326 and the second interlayer insulating film 322. Using the hard mask pattern as an etching mask, A second conductive pad 332 and a word line 330 are formed in the cell region by patterning the conductive film and a third conductive pad 334 and a conductive line 336 are formed in the peripheral circuit region. And the second wiring 338 are formed. The upper surface of the conductive film is preferably deposited with the same material as a conductive beam in a subsequent process.

Specifically, as in the first embodiment, the first and second conductive pads 328 and 332 are formed to have an isolated shape on the first contact plug 324 and the second preliminary electrode pattern. In addition, the word line 330 is formed to have a line shape extending in the second direction between the preliminary capacitor and the first contact plug.

On the other hand, the third conductive pad 334 is formed to have an isolated shape on the second contact plug 326. In addition, the second wiring 338 is formed to have a pattern shape for signal transmission.

After the second conductive pad 332 is formed, the second electrode pattern 316 having an isolated shape is formed by etching the second preliminary electrode pattern. By performing the above process, the capacitor included in the cell is completed.

Referring again to FIG. 27, a third interlayer insulating film 340 is formed to fill a gap between the formed patterns. After the third interlayer insulating layer 340 is formed, the hard mask pattern is removed, and the surface of the third interlayer insulating layer 340 is partially etched to have a flat upper surface.

A first preliminary sacrificial layer pattern and a second sacrificial layer are sequentially formed on the third interlayer insulating layer 340 and the surfaces of the respective patterns. An opening is formed to expose the first conductive pad 328 and the third conductive pad 334 by etching a portion of the first sacrificial film pattern and the second sacrificial film. By forming the opening, the first sacrificial film pattern and the second sacrificial film pattern are formed, respectively.

Thereby forming a conductive film for forming a conductive beam on the first and second sacrificial film patterns while filling the openings. Thereafter, the conductive film is patterned to form a first conductive beam 342a electrically connected to the first contact plug 324 and a second conductive beam 342b electrically connected to the second contact plug 326, Respectively. The first and second conductive beams 342a and 342b have a shape in which both ends are lowered toward the substrate. Examples of materials that can be used for the first and second conductive beams 342a and 342b are the same as those described in the first embodiment.

Thereafter, by removing the first and second sacrificial film patterns, a device that performs a mechanical switching operation in the cell region and the ferry region is formed.

As described, it is possible to employ elements that perform mechanical switching operations on the ferrier circuit and the cell, respectively. That is, in the ferrier circuit, the second wiring and the first wiring are short-circuited or opened according to the movement of the second conductive beam, thereby performing the switching operation. In addition, the DRAM cells operate in the same manner as in the first embodiment to store data in the capacitor.

As described above, the DRAM device according to the present invention improves the data retention ability by greatly reducing the charge leakage in the capacitor included in the cell. Therefore, the refresh operation is not required, and the data stored in the capacitor does not change and can function as a nonvolatile element.

Therefore, the present invention can be used not only in various electronic products and communication devices using conventional DRAM devices, but also in electronic products and storage media using nonvolatile devices. It can also be used in a variety of electronic and communications products where a reduction in power consumption is desired.

1 is a cross-sectional view showing a DRAM device according to a first embodiment of the present invention.

FIGS. 2 to 15 are cross-sectional views for explaining one method for fabricating the DRAM device according to the first embodiment of the present invention.

FIGS. 16 and 17 are cross-sectional views for explaining another method for manufacturing the DRAM device according to the first embodiment of the present invention.

FIGS. 18 to 20 are cross-sectional views for explaining another method for manufacturing the DRAM device according to the first embodiment of the present invention.

21 to 23 are cross-sectional views for explaining another method for manufacturing the DRAM device according to the first embodiment of the present invention.

24 is a cross-sectional view showing a DRAM device according to a second embodiment of the present invention.

25 and 26 are cross-sectional views for explaining a method of manufacturing the DRAM according to the second embodiment of the present invention.

FIG. 27 is a cross-sectional view showing a DRAM device according to a third embodiment of the present invention. FIG.

28 is a cross-sectional view for explaining a method of manufacturing a DRAM device according to a third embodiment of the present invention.

Claims (22)

A contact plug provided on a substrate; A conductive beam in the form of a horizontal blade connected to the upper surface of the contact plug and extending in a direction parallel to the substrate and having both ends lowered toward the substrate; A word line spaced apart from the conductive beam and to which a signal for mechanically moving the conductive beam is applied; And And capacitors electrically short-circuiting or opening with the contact portion of the conductive beam by movement of the conductive beam, Wherein the contact plugs are disposed on opposite sides of the contact plugs such that the word lines and the capacitors are respectively symmetrical about the contact plugs, one word line and a capacitor are provided on one side of the contact plugs, And a word line and a capacitor. The device of claim 1, further comprising a bit line electrically connected to a bottom surface of the contact plug on the substrate. The device of claim 1, wherein the word line and the capacitor are located below the bottom surface of the conductive beam and are disposed such that the top surface is exposed. The device of claim 1, wherein the gap between the bottom surface of the conductive beam and the top surface of the capacitor is narrower than the gap between the bottom surface of the conductive beam and the top surface of the word line. delete The device of claim 1, wherein the capacitor is a stacked capacitor in which a first electrode pattern, a dielectric layer, and a second electrode pattern are sequentially deposited. The device of claim 6, wherein the first electrode pattern of the capacitor has a line shape extending in a direction perpendicular to the bit line, and the second electrode pattern has an isolated pattern shape. The device of claim 1, further comprising first and second conductive pads on the contact plug and the capacitor, the first and second conductive pads having a top surface located in the same plane as the word line. The method according to claim 1, An insulating layer covering the cells formed on the substrate while providing a space for the conductive beam to move up and down; An upper bit line provided on the insulating film; And Further comprising upper cells including contact plugs, conductive beams, word lines and capacitors having the same structure as the cells formed in the substrate on the insulating film and the upper bit line. The semiconductor device according to claim 1, wherein a peripheral circuit region for applying a signal to the cell is provided on one side of the substrate, and a wiring connected to the selection transistor and the selection transistor is provided on the substrate of the ferrite circuit region Diram device. delete delete delete delete delete delete delete delete delete delete delete delete

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