KR100878495B1 - Method of manufacutring capacitor for semiconductor device - Google Patents

Abstract

The present invention provides a method of manufacturing a capacitor of a semiconductor device capable of reducing the etching thickness of the capacitor oxide film to prevent bowing and bridges and at the same time ensuring sufficient capacitor capacity corresponding to the highly integrated device.

According to the present invention, the capacitor oxide film is deposited in two times, and each is etched to form capacitors on the upper and lower portions of the bit line to form a stacked double capacitor, thereby preventing the bowing phenomenon by reducing the etching depth of the capacitor oxide film. Accordingly, it is possible to prevent the bridge between the storage node electrodes, thereby improving the yield of the device. In addition, the multilayered double capacitor can secure sufficient capacitor capacity corresponding to high integration, thereby improving the electrical characteristics of the device.

Bitline, Capacitor, Bowing, Bridge, Capacitor Oxide

Description

METHODS OF MANUFACUTRING CAPACITOR FOR SEMICONDUCTOR DEVICE}             

1A to 1H are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

※ Explanation of symbols for main parts of drawing

10 semiconductor substrate 11, 19 first and second interlayer insulating film

12A, 12B, 12C: first to third plug

13: nitride film 14, 25: first and second capacitor oxide films

15, 26: first and second holes for the capacitor

16 and 27: first and second storage node electrodes

17, 28: first and second dielectric film

18, 29: first and second plate electrodes

20: contact hole for bit line 21: contact hole spacer

22: bit line 23: hard mask

24: bit line spacer C1, C2: first and second capacitors

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device capable of securing a sufficient capacitor capacity corresponding to high integration.

In general, a capacitor used in a memory cell is composed of a storage node electrode, a dielectric film, and a plate electrode, and has a sufficient capacitor capacity corresponding to the device within a cell area which decreases with high integration. Increasingly, the height of the capacitor is increasing.

Such capacitors typically define a capacitor region by applying a capacitor oxide layer, which is a sacrificial layer, after the formation of the storage node contact, and then sequentially form the storage node electrode, the dielectric layer, and the plate electrode. A capacitor oxide film should be formed and etched to a corresponding thickness.

On the other hand, due to the reduction in design rule margin due to cell area reduction, it is possible to secure sufficient capacitor capacity corresponding to the device only by increasing the capacitor height, for example, 2 μm or more. Accordingly, the capacitor oxide film should be applied to a thickness of 2 μm or more and etched to 2 μm or more to form a capacitor hole to limit the capacitor region. However, when the capacitor oxide film is etched to a thickness of 2 μm or more, the space between the holes is not only narrowed, but bowing occurs during etching, which causes a bridge between storage node electrodes, thereby lowering the yield of the device. Therefore, there is a limit to increasing the capacitor height.

The present invention has been proposed to solve the problems of the prior art as described above, which reduces the etching thickness of the capacitor oxide film to prevent bowing, bridges, etc., and at the same time secures a sufficient capacitor capacity corresponding to the highly integrated device. It is an object of the present invention to provide a method for manufacturing a capacitor of a device.

According to an aspect of the present invention for achieving the above technical problem, an object of the present invention comprises the steps of preparing a semiconductor substrate having a first interlayer insulating film having a first to third plugs spaced apart from each other; Forming a nitride film and a first capacitor oxide film on the substrate; Etching the first capacitor oxide layer to expose the first and third plugs to form a first hole for the capacitor; Forming a first storage node electrode to be embedded only in the first hole; Removing the first capacitor oxide film; Sequentially forming a first dielectric layer and a first plate electrode on the first storage node electrode and the nitride layer; Forming a first capacitor by full-etching the first plate electrode and the second dielectric layer so that the surface of the first storage node electrode is exposed; Forming a second interlayer insulating film on the entire surface of the substrate; Forming a contact hole for a bit line exposing a second plug between the first and third plugs; Forming a first spacer on the contact hole sidewall; Forming a bit line in contact with the third plug through the contact hole; Forming a second spacer on the bitline sidewalls; Forming a second capacitor oxide film on the entire surface of the substrate; Etching the second capacitor oxide layer to expose the first storage node electrode to form a second hole for the capacitor; Forming a second storage node electrode to be buried only in the second hole; Removing the second capacitor oxide film; And sequentially forming a second dielectric layer and a second plate electrode on the second storage node electrode and the second interlayer insulating layer to form a second capacitor.

Preferably, the etching depth of the first capacitor oxide layer is 1 μm or less, and the entire surface etching is performed by a chemical mechanical polishing process in the step of forming the first capacitor.

In addition, the first and second dielectric films are the same as one selected from a PZT film, an STO film, a BST film, an ONO film, an NO film, a titanium oxide film (TiO), a tantalum oxide film (TaO), and a tantalum nitride film (TaON). A film or another film, the first and second plate electrodes are made of the same film or another film as a polysilicon film or a metal film, and the first and second spacers are made of a nitride film, respectively.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.                     

1A to 1H are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, a first interlayer insulating film 11 is formed on a semiconductor substrate 10 on which a cell region is defined and a predetermined process such as a transistor is completed, and a portion of the substrate 10 of the cell region is exposed. The interlayer insulating layer 11 is etched to form first to third contact holes spaced at predetermined intervals. Next, the polysilicon film is deposited to be filled in the first to third contact holes, and the polysilicon film is etched by the chemical mechanical polishing (CMP) process or the etch-back process to etch the entire surface of the polysilicon film. The first to fifth plugs 12A, 12B, and 12C that form contact are formed. Next, the nitride film 13 and the first capacitor oxide film 14 are sequentially deposited on the entire surface of the substrate, and the first capacitor oxide film 14 and the nitride film 13 are exposed to expose the first and third plugs 12A and 12C. ) To form the first hole 15 for the capacitor to define the first capacitor region. Preferably, the first capacitor oxide film 14 is formed to a thickness of 1/2 or less, more preferably 1 μm or less, of the total capacitor oxide film so that the etching depth does not exceed 1 μm.

Referring to FIG. 1B, a first conductive film, such as a polysilicon film or a metal film, is deposited on the first capacitor oxide film 14 so as to be filled in the first hole 15, and the first capacitor oxide film is formed by a CMP process or an etch back process. The first storage node electrode 16 is formed by etching the conductive layer so that 14 is exposed. Next, the nitride film 13 is used as an etch stop film and the first capacitor oxide film 14 of the cell region is removed to expose the nitride film 13 and the first storage node electrode 16.                     

Referring to FIG. 1C, the first dielectric layer 17 is deposited on the exposed surfaces of the first storage node electrode 16 and the nitride layer 13, and the first plate electrode 18 is disposed on the first dielectric layer 17. Form. Preferably, the first dielectric layer 17 is one of PZT, STO, BST, ONO, NO, titanium oxide (TiO), tantalum oxide (TaO), and tantalum oxynitride (TaON). The first plate electrode 18 is formed of a polysilicon film or a metal film. Next, the first capacitor C1 is formed by etching the entire surface of the first plate electrode 18 and the first dielectric layer 17 so that the surface of the first storage node electrode 16 is exposed by a CMP process or an etch back process. .

Referring to FIG. 1D, the second interlayer insulating film 19 is formed on the entire surface of the substrate, and the second interlayer insulating film 19 is exposed to expose the second plug 12B between the first and third plugs 12A and 12C. The bit plate contact hole 20 is formed by etching the first plate electrode 18, the first dielectric layer 17, and the nitride layer 13. Next, a nitride film is deposited on the surface of the contact hole 20 and the second interlayer insulating layer 19, and is etched back through the etch back process to form the contact hole spacer 20 on the sidewall of the contact hole 20.

Referring to FIG. 1E, a second conductive layer is deposited on the second interlayer insulating layer 19 to be filled in the contact hole 20, a hard mask 23 is formed on the second conductive layer, and the hard mask 23 is formed. The second conductive film is patterned using the bit line 22. Next, a nitride film is deposited on the entire surface of the substrate and etched back through the etch back process to form the bit line spacers 24 on the sidewalls of the bit line 22 and the hard mask 23.

Referring to FIG. 1F, the second capacitor oxide layer 25 is deposited on the entire surface of the substrate, and the second capacitor oxide layer 25 is etched to expose the first storage node electrode 16 of the first capacitor C1 to expose the capacitor. The second capacitor region is defined by forming the second hole 26.

Referring to FIG. 1G, a third conductive film such as a polysilicon film or a metal film is deposited on the second capacitor oxide film 25 so as to be buried in the second hole 26, and the second capacitor oxide film (eg, by a CMP process or an etch back process). The second conductive layer is formed by etching the entire surface of the third conductive layer so that the 25 is exposed. Next, the second capacitor oxide film 25 in the cell region is removed using the second interlayer insulating film 19 as an etch stop film to expose the second interlayer insulating film 19 and the second storage node electrode 27.

Referring to FIG. 1H, a second dielectric layer 28 is deposited on the exposed surfaces of the second storage node electrode 27 and the second interlayer dielectric layer 19, and a second plate electrode is formed on the second dielectric layer 28. 29) to form a second capacitor C2, thereby completing a stacked double capacitor in which the first and second capacitors C1 and C2 are stacked. Preferably, the second dielectric film 28, like the first dielectric film 17, has a PZT film, an STO film, a BST film, an ONO film, an NO film, a titanium oxide film (TiO), a tantalum oxide film (TaO), and a tantalum nitride oxide film (TaON). Is formed of the same film as the first dielectric film 17 or a different film, and the second plate electrode 29 is formed of the first silicon film or the polysilicon film like the first plate electrode 18. The film is formed of the same film as the plate electrode 18 or a different film.

According to the above embodiment, the capacitor oxide film is divided into two times and deposited and etched to form capacitors above and below the bit line, respectively, to form a stacked double capacitor, thereby reducing the etching depth of the capacitor oxide film to prevent bowing phenomenon. As a result, it is possible to prevent the bridge between the storage node electrodes, thereby improving the yield of the device. In addition, the multilayered double capacitor can secure sufficient capacitor capacity corresponding to high integration, thereby improving the electrical characteristics of the device.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention can reduce the etching thickness of the capacitor oxide film by applying the stacked double capacitor, thereby preventing the bowing and the resulting bridge, thereby improving the yield of the device, and sufficient capacitor corresponding to the highly integrated device. By securing the capacity, the electrical characteristics of the device can be improved.

Claims (8)

Preparing a semiconductor substrate having a first interlayer insulating film having first to third plugs spaced apart from each other; Forming a nitride film and a first capacitor oxide film on the substrate; Etching the first capacitor oxide layer to expose the first and third plugs to form a first hole for a capacitor; Forming a first storage node electrode to be buried only in the first hole; Removing the first capacitor oxide film; Sequentially forming a first dielectric layer and a first plate electrode on the first storage node electrode and the nitride layer; Forming a first capacitor by full etching the first plate electrode and the second dielectric layer so that the surface of the first storage node electrode is exposed; Forming a second interlayer insulating film on the entire surface of the substrate; Forming a contact hole for a bit line exposing a second plug between the first and third plugs; Forming a first spacer on sidewalls of the contact hole; Forming a bit line in contact with the third plug through the contact hole; Forming a second spacer on the bit line sidewalls; Forming a second capacitor oxide film on the entire surface of the substrate; Etching the second capacitor oxide layer to expose the first storage node electrode to form a second hole for a capacitor; Forming a second storage node electrode to be buried only in the second hole; Removing the second capacitor oxide film; And And forming a second capacitor by sequentially forming a second dielectric layer and a second plate electrode on the second storage node electrode and the second interlayer insulating layer. The method of claim 1, The first capacitor oxide film is a capacitor manufacturing method of the semiconductor device, characterized in that formed in less than 1/2 of the total capacitor oxide film thickness. The method of claim 1, In the forming of the first capacitor, the entire surface etching is performed by a chemical mechanical polishing process or an etch back process. The method of claim 1, The first and second dielectric films each comprise a film selected from a PZT film, an STO film, a BST film, an ONO film, a NO film, a titanium oxide film, a tantalum oxide film, and a tantalum oxynitride film, respectively. . The method according to claim 1 or 4, And the first and second dielectric films are made of the same film or different films. The method of claim 1, Wherein the first and second plate electrodes are made of a polysilicon film or a metal film, respectively. The method according to claim 1 or 6, And the first and second plate electrodes are made of the same film or different films. The method of claim 1, The first and second spacers are a capacitor manufacturing method of a semiconductor device, characterized in that each consisting of a nitride film.

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