KR20040059437A - Method of manufacturing capacitor for semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to increase the capacitance and to prevent bowing by additionally forming a sub capacitor at lower of a main capacitor. CONSTITUTION: A bit line(11) with a hard mask(12) and a spacer(13) is formed on a cell region(R1) of a substrate(10). An interlayer dielectric(14) with a contact hole is formed on the resultant structure. A storage node contact(16) is formed in the contact hole. The interlayer dielectric on the bit line is selectively etched. The first dielectric film(17) and the first plate electrode(18) are formed on the exposed bit line, thereby forming a sub capacitor(C1) on the cell region. A nitride pattern(19) is formed to expose the storage node contact. A nitride spacer(20) is formed at both sidewalls of the nitride pattern. A capacitor oxide layer(21) is formed on the resultant structure. A capacitor hole is formed to expose the storage node contact. A storage node electrode(22) is formed on the storage node contact. The second dielectric(23) and the second plate electrode(24) are formed on the storage node electrode, thereby forming a main capacitor(C2).

Description

METHODS OF MANUFACTURING CAPACITOR FOR SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device capable of securing a sufficient capacitor capacity corresponding to high integration.

In general, a capacitor used in a memory cell is composed of a storage node electrode, a dielectric film, and a plate electrode, and has a sufficient capacitor capacity corresponding to the device within a cell area which decreases with high integration. Increasingly, the height of the capacitor is increasing.

Such capacitors typically define a capacitor region by applying a capacitor oxide layer, which is a sacrificial layer, after the formation of the storage node contact, and then sequentially form the storage node electrode, the dielectric layer, and the plate electrode. Therefore, in order to obtain a capacitor having a desired height, A capacitor oxide film should be formed and etched to a corresponding thickness.

However, when the capacitor oxide film is applied and etched to a thickness of 2 μm or more, for example, the hole in the etched portion of the capacitor oxide film becomes larger and the space between the remaining capacitor oxide films becomes narrower, causing bowing. Adjacent holes penetrate in the horizontal direction, thereby lowering insulation characteristics between subsequent storage node electrodes and causing bridges between storage node electrodes, thereby lowering the yield of devices.

The present invention has been proposed to solve the problems of the prior art as described above, it is possible to effectively prevent the bowing phenomenon during the capacitor oxide film by securing a sufficient capacitor capacity corresponding to high integration without increasing the height of the capacitor above the limit height It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device.

1A to 1G are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

※ Explanation of symbols for main parts of drawing

10 semiconductor substrate 11 bit line

12: hard mask 13: bit line spacer

14 interlayer insulating film 15 contact hole

16: storage node contact 17: first dielectric layer

18: first plate electrode 19: nitride film pattern

20 nitride film spacer 21 capacitor oxide film

22: storage node electrode 23: the second dielectric film

24: second plate electrode C1: subcapacitor

C2: main capacitor

According to an aspect of the present invention for achieving the above technical problem, an object of the present invention is to prepare a semiconductor substrate in which a cell region and a peripheral region is defined and a bit line having a hard mask and a spacer is formed in the cell region step; Forming an interlayer insulating film having a planarized surface on the entire surface of the substrate so as to cover the bit lines; Forming a contact hole by etching the interlayer insulating layer so that the substrates on both sides of the bit line are exposed; Forming a storage node contact buried only in the contact hole and in contact with the substrate; Exposing an upper portion of the storage node contact by removing the interlayer dielectric layer on the bit line of the cell region; Sequentially depositing a first dielectric layer and a first plate electrode on the front surface of the substrate and etching the entire surface to expose the surface of the storage node contact to form a subcapacitor in the cell region; Forming a nitride film pattern exposing only a storage node contact on the substrate; Forming a nitride film spacer on the nitride film pattern sidewalls; Forming a capacitor oxide film on the entire surface of the substrate; Etching the capacitor oxide layer to expose the storage node contact to form a hole for the capacitor; Forming storage node electrodes separated from each other on the hole surface; And sequentially forming and patterning a second dielectric layer and a second plate electrode on the entire surface of the substrate on which the storage node electrode is formed to form a main capacitor in the cell region.

The forming of the interlayer insulating film having the planarized surface may include forming the interlayer insulating film on the entire surface of the substrate to cover the bit line; And the entire surface is etched by a predetermined thickness by a chemical mechanical polishing process to planarize the surface, and the chemical mechanical polishing process is performed such that the thickness of the interlayer insulating film remains at about 2000 kPa or more above the bit line.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

1A to 1G are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, the cell region R1 and the peripheral region R2 are defined, and a hard mask is disposed on the cell region R1 of the semiconductor substrate 10 where predetermined processes such as transistors and bit line contacts are completed. 12 is formed and a bit line 11 having a bit line spacer 13 is formed at a side thereof. Next, an interlayer insulating film 14 is formed on the entire surface of the substrate so as to cover the bit line 11, and the interlayer insulating film 14 is etched by a predetermined thickness by chemical mechanical polishing (CMP). The surface of 14 is planarized. Preferably, the CMP process is performed such that the thickness of the interlayer insulating film 14 remains above about 2000 kV over the bit line 11. Subsequently, the planarization interlayer insulating layer 14 is etched using a storage node contact mask to partially expose the substrates on both sides of the bit line 11 by a self-aligned contact (SAC) process. ).

Referring to FIG. 1B, a conductive film such as a polysilicon film is deposited on the interlayer insulating film 14 to be filled in the contact hole 15, and the surface of the interlayer insulating film 14 is subjected to a CMP process or an etch-back process. The conductive layers are separated from each other by etching the entire surface so as to be exposed, thereby forming a storage node contact 16 contacting the substrate 10 in the cell region R1. Next, as shown in FIG. 1C, the upper portion of the storage node contact 16 is exposed by removing the interlayer dielectric layer 14 positioned on the bit line 12 of the cell region R1 using the cell region open mask. Let's do it.

Referring to FIG. 1D, the first dielectric layer 17 and the first plate electrode 18 are sequentially deposited on the entire surface of the substrate. Preferably, the first dielectric layer 17 is one of PZT, STO, BST, ONO, NO, titanium oxide (TiO), tantalum oxide (TaO), and tantalum oxynitride (TaON). The first plate electrode 18 is formed of a polysilicon film or a metal film. Next, the first plate electrode 18 and the first dielectric layer 17 are etched by the CMP process or the etch back process so that the surface of the storage node contact 16 is exposed. 16) the sub-capacitor C1 formed of the first dielectric film 17 and the first plate electrode 18 is formed.

Referring to FIG. 1E, a first nitride film is deposited on the entire surface of the substrate and patterned to expose the storage node contact 16 to form a nitride film pattern 19. Next, a second nitride film is deposited on the entire surface of the substrate to cover the nitride film pattern 19, and the entire surface is etched so that the surface of the nitride film pattern 19 is exposed by an etch back process, thereby forming the nitride film spacer 20 on the sidewall of the nitride film pattern 19. To form. Here, the nitride film spacer 20 is formed to insulate between the first plate electrode 28 of the subcapacitor C1 and the storage node electrode of the subsequent main capacitor. Preferably, the first and second nitride films are formed of low voltage (Low). Pressure (LP) -nitride film or Plasma Enhanced (PE) -nitride film.

Referring to FIG. 1F, the capacitor oxide film 21 is formed on the entire surface of the substrate, and the capacitor oxide film 21 is etched to expose the storage node contact 16 to form a capacitor hole. Preferably, the capacitor oxide film 21 is formed to have a thickness of, for example, 2 μm or less so that a bowing phenomenon does not occur during etching. Next, a storage node electrode 22 is formed on the hole surface and the capacitor oxide film 21 surface, and a photoresist film (not shown) is formed as a buried material film so as to be embedded in the hole in which the storage node electrode 22 is formed. do. Next, the photoresist film and the storage node electrode 22 are etched by the CMP process or the etch back process to expose the surface of the capacitor oxide film 21 to separate the storage node electrodes 22 from each other, and then the photoresist film is removed. do.

Referring to FIG. 1G, the second dielectric layer 23 and the second plate electrode 24 are sequentially deposited and patterned on the entire surface of the substrate to form the storage node electrode 22 and the second dielectric layer 23 in the cell region R2. ) And the second capacitor electrode 24 is formed. Preferably, the second dielectric layer 23 is one of PZT, STO, BST, ONO, NO, titanium oxide (TiO), tantalum oxide (TaO), and tantalum nitride oxide (TaON). The same film as the first dielectric film 17 or another film is formed, and the second plate electrode 24 is also formed of the same film as the first plate electrode 18 or a different film from the polysilicon film or the metal film.

According to the above embodiment, as the subcapacitor is further formed using the storage node contact under the main capacitor, sufficient capacitor capacity corresponding to high integration can be ensured without increasing the height of the capacitor above the limit height. Accordingly, a bowing phenomenon does not occur during the capacitor oxide film etching and the bridge between the storage node electrodes is prevented, thereby improving the yield of the device.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention described above can improve the yield of the device by effectively preventing the bowing phenomenon during the capacitor oxide film by securing a sufficient capacitor capacity corresponding to high integration without increasing the height of the capacitor above the limit height.

Claims (10)

Preparing a semiconductor substrate having a cell region and a peripheral region defined therein, wherein a bit line having a hard mask and a spacer is formed in the cell region; Forming an interlayer insulating film having a planarized surface on an entire surface of the substrate to cover the bit line; Forming a contact hole by etching the interlayer insulating layer so that the substrates on both sides of the bit line are exposed; Forming a storage node contact buried only in the contact hole and in contact with the substrate; Exposing an upper portion of the storage node contact by removing an interlayer insulating layer on a bit line of the cell region; Sequentially depositing a first dielectric layer and a first plate electrode on the entire surface of the substrate and etching the entire surface to expose the surface of the storage node contact to form a subcapacitor in the cell region; Forming a nitride film pattern exposing only the storage node contact on the substrate; Forming a nitride film spacer on sidewalls of the nitride film pattern; Forming a capacitor oxide film on the entire surface of the substrate; Etching the capacitor oxide layer to expose the storage node contact to form a hole for a capacitor; Forming storage node electrodes separated from each other on the hole surface; And And sequentially depositing and patterning a second dielectric layer and a second plate electrode on the entire surface of the substrate on which the storage node electrode is formed to form a main capacitor in the cell region. The method of claim 1, Forming the interlayer insulating film having the planarized surface is Forming an interlayer insulating film on an entire surface of the substrate to cover the bit line; And And etching the entire surface of the insulating interlayer by a predetermined thickness to planarize a surface thereof. The method of claim 2, A method for manufacturing a capacitor of a semiconductor device, characterized in that the front surface etching of the interlayer insulating film is performed by a chemical mechanical polishing process. The method of claim 3, wherein Wherein the chemical mechanical polishing process is performed such that the thickness of the interlayer dielectric layer remains at least about 2000 GPa over the bit line. The method of claim 1, The front surface etching of the first dielectric film and the first plate electrode is a capacitor manufacturing method of a semiconductor device, characterized in that for performing a chemical mechanical polishing process or an etch back process. The method of claim 1, The nitride film is a capacitor manufacturing method of a semiconductor device, characterized in that formed by a low pressure-nitride film or a plasma-enhanced nitride film. The method of claim 1, The first and second dielectric films each comprise a film selected from a PZT film, an STO film, a BST film, an ONO film, a NO film, a titanium oxide film, a tantalum oxide film, and a tantalum oxynitride film, respectively. . The method according to claim 1 or 7, And the first and second dielectric films are formed of the same film or different films. The method of claim 1, And the first and second plate electrodes are made of a polysilicon film or a metal film, respectively. The method according to claim 1 or 9, And the first and second plate electrodes are made of the same film or different films.