KR100345065B1 - Method for manufacturing capacitor in semiconductor device - Google Patents

Abstract

The present invention includes sequentially depositing an interlayer insulating film and a nitride film on a semiconductor substrate defining a cell region and a peripheral region; Forming a first photoresist pattern in the capacitor formation region, and subsequently etching the nitride film and the interlayer insulating film using the pattern as an etch barrier to form a contact hole; Depositing a plug polysilicon film in the contact hole; Sequentially depositing a cap oxide film and a hard mask film on the resultant product; Forming a second photoresist pattern defining a capacitor formation region, and sequentially etching the hard mask film and the cap oxide film to expose the plug polysilicon film by using the pattern as an etch barrier to form a lower electrode module; Depositing a polysilicon film with a lower electrode material on the entire lower electrode module structure, and then coating a photoresist on the polysilicon film so that the inside of the lower electrode module is buried; Grinding the lower mask layer and the lower silicon polysilicon layer deposited on the cap oxide layer through the CMP process, and separating the lower mask layer into one independent memory storage cell; Removing the photoresist buried through the coating process inside the lower electrode module; Forming an amorphous TaON thin film for a dielectric film on the polysilicon film for the lower electrode; And annealing the amorphous TaON thin film to crystallize the TaON thin film, and then depositing an upper electrode metal film to form a capacitor having a convex structure.

Description

METHODS FOR MANUFACTURING CAPACITOR IN SEMICONDUCTOR DEVICE

The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a TaON capacitor of a semiconductor device having a convex structure.

Recently, with the development of semiconductor manufacturing technology, the demand for memory devices is increasing rapidly. The capacitor used as the data storage means varies in capacitance depending on the area of the electrode, the distance between the electrodes, and the dielectric constant of the dielectric film inserted between the electrodes. However, as the semiconductor device is highly integrated, the capacitor formation area in the semiconductor device is reduced, and as a result, the electrode area of the capacitor is reduced, thereby reducing the capacitance of the capacitor. In general, such a capacitor manufacturing method is provided with a semiconductor substrate having an interlayer insulating film provided with a contact hole. A polysilicon film is deposited inside the contact hole and then etched back to form a plug polysilicon film. Then, a PE-Nitride layer is deposited as an etch barrier layer on the plug polysilicon layer, and a PSG layer having a relatively high wet etching rate is deposited as a cap oxide layer. Then, the cap oxide film is etched to form a basic lower electrode structure for producing a capacitor. In this case, the etch barrier nitride layer serves as a dry etching barrier when cap oxide is etched and a wet etching barrier when the cap oxide layer is diped out, and an etching barrier having a sufficient thickness of at least 200 mm 3 or more is required to secure an etching selectivity. Do. However, if the thickness of the etching barrier is increased to secure the etching selectivity, cracks are generated due to stress on the semiconductor substrate. On the other hand, when the nitride film is formed to have a thin thickness so that cracks do not occur, the nitride film is attacked due to lack of selectivity when the cap oxide film is dry etched, and the subsequent interlayer insulating film is etched to become a leakage current source during subsequent etching of the nitride film. The refresh characteristics of the capacitors deteriorate.

Accordingly, as shown in FIG. 1A, an interlayer insulating film 2 having contact holes is formed on the semiconductor substrate 1 that defines the cell region A and the peripheral region B. As shown in FIG. Then, a plug polysilicon film 3 is formed in the contact hole, and an etch barrier film 4 and a cap oxide film, for example, a PSG film 5 are sequentially deposited on the entire surface of the resultant product. Subsequently, a cap oxide film 5 is etched by forming a photoresist pattern (not shown) defining a capacitor region and using the photoresist pattern as an etch barrier so that the interlayer insulating film 2 is exposed. As a result, a basic lower electrode structure for manufacturing the capacitor is formed.

Referring to FIG. 1B, a polysilicon film for the charge storage electrode 6 and an N / O or Ta2O5 film 7 for the dielectric film are sequentially deposited on the entire surface of the resultant product. Then, a USG film 8 such as a PSG and SOG film having a fast wet etching rate is deposited on the entire surface of the substrate, or the photoresist film 8 is coated on the entire surface to fill the inside of the cylinder structure.

1C, the USG film 8 or the photoresist film 8, such as the PSG film or SOG film, or the Ta2O5 film and the polysilicon film 6, in turn, is polished until the interlayer insulating film 2 is exposed. do. Then, the PSG film, the USG film 8 or the photoresist film 8 is wet etched.

Referring to FIG. 1D, a capacitor structure of a cylindrical cylinder structure is formed by dipping out the cap oxide film 5 to use both the inside and the outside of the charge storage electrode 6.

However, the conventional capacitor manufacturing method of the semiconductor device as described above has the following problems.

When the cap oxide film 5 is diped out to use the outer side of the charge storage electrode 6 of the cylindrical cylinder structure, the cap oxide film 5 in the peripheral region B is wet-etched together, and FIG. 1D. As shown in FIG. 2, a step is generated between the cell region and the peripheral region by the height l of the charge storage electrode. Therefore, there is no DOF (Depth Of Focus) margin during the exposure process, so a process of planarizing and depositing the interlayer insulating film should be added. As a result, a CMP process, which is a polishing process after deposition of an interlayer insulating film, is required, and a cell recess mask process and an etching process that partially etch only the insulating film of the cell region are needed to improve the uniformity of the CMP. Hereinafter, a stripping step and a subsequent cleaning step of the photoresist film including the mask are required in subsequent steps. Therefore, the number of unit processes is large and the process is complicated, and manufacturing cost is high.

Accordingly, the present invention has been made to solve the above problems, by using a TaON thin film having a high dielectric constant and forming a capacitor of a concave structure, the semiconductor does not generate a step between the cell region and the peripheral region It is an object of the present invention to provide a method of manufacturing a capacitor of a device.

1A to 1D are cross-sectional views for explaining a capacitor manufacturing method of a conventional semiconductor device.

2A to 2G are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device of the present invention.

Explanation of symbols on the main parts of the drawings

10 semiconductor substrate 11 interlayer insulating film

12: nitride film 13: plug polysilicon film

12a: barrier nitride film 12b: buffer oxide film

14 cap oxide film 15 hard mask film

16: lower electrode module 17: polysilicon film for the lower electrode

18: photoresist film 19: amorphous TaON thin film

19a: crystallized TaON thin film 20: upper electrode metal film

In order to achieve the above object, the present invention comprises the steps of sequentially depositing an interlayer insulating film and a nitride film on a semiconductor substrate defining a cell region and a peripheral region; Forming a first photoresist pattern in the capacitor formation region, and subsequently etching the nitride film and the interlayer insulating film using the pattern as an etch barrier to form a contact hole; Depositing a plug polysilicon film in the contact hole; Sequentially depositing a cap oxide film and a hard mask film on the resultant product; Forming a second photoresist pattern defining a capacitor formation region, and sequentially etching the hard mask film and the cap oxide film to expose the plug polysilicon film by using the pattern as an etch barrier to form a lower electrode module; Depositing a polysilicon film with a lower electrode material on the entire lower electrode module structure, and then coating a photoresist on the polysilicon film so that the inside of the lower electrode module is buried; Polishing the hard mask film and the polysilicon film for the lower electrode deposited on the cap oxide film through a chemical mechanical polishing (CMP) process, and separating the polysilicon film for each of the cells into one independent memory storage cell; Removing the photoresist buried through the coating process inside the lower electrode module; Forming an amorphous TaON thin film for a dielectric film on the polysilicon film for the lower electrode; And annealing the amorphous TaON thin film to form a crystallized TaON thin film, and then depositing a metal film for the upper electrode to form a capacitor having a convex structure.

The nitride film is continuously deposited with a barrier nitride film and a buffer oxide film, for example, a PE-TEOS film. At this time, the buffer oxide film is preferably deposited to a thickness of 200 ~ 1000Å using LP-CVD, PE-CVD or RT-CVD equipment.

The nitride film and the interlayer insulating film are etched at 30% transient etching, respectively.

The plug polysilicon film is composed of a doped polysilicon film having a p concentration of 2E + 20 atoms / cc or more using LP-CVD or RTP equipment.

The hard mask film is preferably composed of a doped poly or undoped polysilicon film with a thickness of 500-2000 kPa.

The cap oxide film preferably uses an oxide film such as a PE-TEOS film, a PSG film or a USG film using a Si-H Base source.

When etching the cap oxide layer for forming the lower electrode, the lower nitride layer is used as an etching barrier, and the etching process is performed at a rate of 10% to 100%, and the etching selectivity of the cap oxide layer and the nitride layer is preferably 5 to 20: 1. Keep it.

The polysilicon film for the lower electrode may further include being formed in a Hemi-Sphrical Grain (HSG) shape in order to increase the charge capacity of the capacitor device.

In the CMP process, the polysilicon film for the lower electrode including the hard mask film is processed to a 5 to 20% CMP target.

Before depositing the amorphous TaON thin film, a compound such as H2SO4 solution or NH4OH solution is added before or after the HF cleaning to clean the upper part of the polysilicon film for the lower electrode using HF solution, and to remove foreign substances including other organic substances. Clean. Then, before depositing the amorphous TaON thin film, the upper part of the polysilicon film for lower electrode is nitrided in an NH 3 gas atmosphere using plasma or RTP.

The amorphous TaON thin film is formed by the reaction of Ta chemical vapor obtained from NH3 and the raw material in an LPCVD chamber in which the raw material tantalum ethylene (Ta (OC2H5) 5) is vaporized in a vaporizer and supplied with NH3 gas. do. At this time, the amorphous TaON thin film is preferably deposited to a thickness of 50 ~ 100Å.

The amorphous TaON thin film is heat-treated at a temperature of 650 to 750 ° C. in a chamber supplied with N 2 O or O 2 gas in-situ to remove impurities in the thin film and to form a crystallized TaON thin film.

The upper electrode metal film is formed of a TiN, TaN, W, WN, WSi, Ru, RuO 2, Ir, IrO 2, Pt film, or the like.

(Example)

Hereinafter, with reference to the accompanying drawings will be described in detail a capacitor manufacturing method of the semiconductor device of the present invention.

Referring to FIG. 2A, an interlayer insulating film 11 and a nitride film 12 are sequentially deposited on the semiconductor substrate 10 defining the cell region A and the peripheral region B. FIG. The nitride film 12 is continuously deposited with a barrier nitride film 12a and a buffer oxide film 12b, for example, a PE-TEOS film. At this time, the buffer oxide film is preferably deposited to a thickness of 200 ~ 1000Å using LP-CVD, PE-CVD or RT-CVD equipment.

Referring to FIG. 2B, a first photoresist layer pattern (not shown) is formed in the capacitor formation region, and the nitride layer 12 and the interlayer dielectric layer 11 are sequentially etched using the pattern as an etch barrier to form contact holes. . At this time, the etching of the nitride film 12 and the interlayer insulating film 11 proceeds with a 30% transient etching of the thickness, respectively. Then, a plug polysilicon film 13 is deposited in the contact hole by a known method. The plug polysilicon film is composed of a doped polysilicon film having a p concentration of 2E + 20 atoms / cc or more using LP-CVD or RTP equipment.

Referring to FIG. 2C, the cap oxide layer 14 and the hard mask layer 15 for process margin are sequentially deposited on the resultant by the miniaturization pattern of the semiconductor device. Here, the hard mask film is preferably composed of a poly or undoped polysilicon film doped with a thickness of 500 ~ 2000Å. In addition, the cap oxide film preferably uses a PE-TEOS film, a PSG film or a USG film using a Si-H Base source. Then, a second photoresist pattern (not shown) defining a capacitor formation region is formed, and then the hard mask layer 15 and the cap oxide layer 14 are sequentially formed so that the plug polysilicon layer is exposed by etching the pattern. The lower electrode module 16 is etched to form the lower electrode module 16. In this case, when the cap oxide layer 14 for forming the lower electrode is etched, the lower nitride layer is used as an etching barrier, and the etching process proceeds to a transient etching of 10% to 100%. The etching selectivity of the cap oxide film and the nitride film is preferably maintained at 5 ~ 20: 1.

Referring to FIG. 2D, a polysilicon film 17 for lower electrodes is deposited on the entire surface of the resultant product. Then, a photoresist 18 having a relatively fast etching speed is deposited on the polysilicon film for the lower electrode so that the inside of the lower electrode module is embedded. In this case, the lower silicon polysilicon layer 17 further includes a HSG (Hemi-Sphrical Grain) shape (not shown), in order to increase the charge capacity of the capacitor element.

Next, referring to FIG. 2E, the hard mask layer 15 and the polysilicon layer 17 for lower electrode deposited on the cap oxide layer 14 are polished through a CMP process to store one independent memory. Separating into a cell (not shown). Here, when the cap oxide is excessively polished through the CMP process, the area of the lower electrode is reduced to reduce the capacitance of the entire capacitor. Accordingly, in the CMP process, the polysilicon film for the lower electrode including the hard mask film is advanced to the CMP target of 5 to 20%. Then, the photoresist inside the lower electrode module 16 is removed.

Referring to FIG. 2F, an amorphous TaON thin film for a dielectric film is formed on the polysilicon film for the lower electrode. Here, before depositing the amorphous TaON thin film, a compound such as H2SO4 solution or NH4OH solution is added before or after the HF cleaning to clean the upper part of the polysilicon film for the lower electrode using HF solution and to remove foreign substances including other organic substances. To clean the interface. Then, before depositing the amorphous TaON thin film, the upper part of the polysilicon film for lower electrode is nitrided in an NH 3 gas atmosphere using plasma or RTP. The amorphous TaON thin film is formed by the reaction of Ta chemical vapor obtained from NH3 and raw materials in an LPCVD chamber in which a raw material tantalum ethylene (Ta (OC2H5) 5) is vaporized in a vaporizer and supplied with NH3 gas. do. At this time, the amorphous TaON thin film is preferably deposited to a thickness of 50 ~ 100Å.

Then, referring to Figure 2g, the amorphous TaON thin film is heat-treated at a temperature of 650 ~ 750 ℃ in a chamber supplied with N2O or O2 gas in-situ to remove impurities in the thin film at the same time crystallized TaON thin film (19a ). Then, a capacitor electrode having a concave structure is deposited on the crystallized TaON thin film by depositing an upper electrode metal film, for example, TiN, TaN, W, WN, WSi, Ru, RuO 2, Ir, IrO 2, or Pt film. Form.

As described in detail above, since the present invention uses a TaON thin film having a higher dielectric constant than the conventional NO and having better leakage current and breakdown field characteristics than the Ta 2 O 5 film, the equivalent oxide film (Tox) of the capacitor can be lowered. Therefore, even if the concave type lower electrode has a simple structure, a capacitance of 25 fF / cell or more can be obtained, and there is no need for a polishing process or a planarization process such as an etch back after the formation of the interlayer insulating film required to form the lower electrode of the conventional cylindrical cylinder structure. . As a result, the step between the cell region and the peripheral region does not occur in the process of forming the TaON capacitor of the concave structure, thereby increasing the throughput and reducing the process around time (TAT).

As a result, the manufacturing cost of the semiconductor device can be greatly reduced, so that the capacitor can be manufactured more economically.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (16)

Sequentially depositing an interlayer insulating film and a nitride film on a semiconductor substrate defining a cell region and a peripheral region; Forming a first photoresist pattern in the capacitor formation region, and subsequently etching the nitride film and the interlayer insulating film using the pattern as an etch barrier to form a contact hole; Depositing a plug polysilicon film in the contact hole; Sequentially depositing a cap oxide film and a hard mask film on the resultant product; Forming a second photoresist pattern defining a capacitor formation region, and subsequently etching the hard mask layer and the cap oxide layer to expose the plug polysilicon layer using the pattern as an etch barrier to form a lower electrode module structure; Depositing a polysilicon film with a lower electrode material on the entire lower electrode module structure, and then coating a photoresist on the polysilicon film so that the inside of the lower electrode module is buried; Grinding the lower mask film and the polysilicon film for lower electrode deposited on the cap oxide film through a chemical mechanical polishing (CMP) process, and separating each of the lower mask film into one independent memory storage cell; Removing the photoresist buried through the coating process inside the lower electrode module; Forming an amorphous TaON thin film for a dielectric film on the polysilicon film for the lower electrode; And Annealing the amorphous TaON thin film to form a crystallized TaON thin film, and then depositing a metal film for the upper electrode to form a capacitor having a convex structure. The method of claim 1, wherein the nitride film is continuously deposited with a barrier nitride film and a buffer oxide film, for example, a PE-TEOS film. The method of claim 1, wherein the buffer oxide film is deposited to a thickness of 200 to 1000 Å using LP-CVD, PE-CVD, or RT-CVD equipment. The method of claim 1, wherein the nitride film and the interlayer insulating film are etched at 30% transient etching, respectively. 2. The method of claim 1, wherein the plug polysilicon film is composed of a doped polysilicon film having a p concentration of 2E + 20 atoms / cc or more using LP-CVD or RTP equipment. 2. The method of claim 1, wherein the hard mask film is made of a poly or undoped polysilicon film, preferably doped with a thickness of 500 to 2000 microns. The method of claim 1, wherein the cap oxide film is preferably an oxide film such as a PE-TEOS film, a PSG film, or a USG film using a Si-H base source. The method of claim 1, wherein when the cap oxide layer is etched to form the lower electrode, the lower nitride layer is used as an etch barrier, and the etching process is performed at a rate of 10% to 100%. Capacitor manufacturing method of a semiconductor device, characterized in that 5 to 20: 1. 2. The method of claim 1, wherein the polysilicon film for lower electrodes is preferably formed in an HSG shape in order to increase the charge capacity of the capacitor element. The method of claim 1, wherein the CMP process is performed by performing a polysilicon film for a lower electrode including a hard mask film to a CMP target of 5 to 20%. The method of claim 1, wherein before the deposition of the amorphous TaON thin film, the HF solution is used to clean the upper part of the polysilicon film for the lower electrode, and to remove foreign substances including other organic substances, a compound such as an H 2 SO 4 solution or an NH 4 OH solution is washed with the HF. A method for manufacturing a capacitor of a semiconductor device, characterized in that the interface is cleaned before or after. The method of claim 1, wherein before the amorphous TaON thin film is deposited, an upper portion of the polysilicon film for lower electrode is nitrided in an NH 3 gas atmosphere by using plasma or RTP. 2. The Ta chemistry of claim 1, wherein the amorphous TaON thin film is made of gaseous state tantalum acrylate (Ta (OC2H5) 5) in a vaporizer in a vapor phase, and is obtained from Ta3 chemicals obtained from NH3 and raw materials in an LPCVD chamber supplied with NH3 gas. Capacitor manufacturing method of a semiconductor device, characterized in that formed by the reaction of steam. The method of claim 13, wherein the amorphous TaON thin film is deposited to a thickness of preferably 50 to 100 GPa. The amorphous TaON thin film of claim 1, wherein the amorphous TaON thin film is heat-treated at a temperature of 650 to 750 ° C. in a chamber supplied with N 2 O or O 2 gas in-situ to remove impurities in the thin film and to form a crystallized TaON thin film. A capacitor manufacturing method of a semiconductor device. The method of claim 1, wherein the upper electrode metal film is formed of a TiN, TaN, W, WN, WSi, Ru, RuO 2, Ir, IrO 2, Pt film, or the like.