KR100465605B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR100465605B1
KR100465605B1 KR1019970081355A KR19970081355A KR100465605B1 KR 100465605 B1 KR100465605 B1 KR 100465605B1 KR 1019970081355 A KR1019970081355 A KR 1019970081355A KR 19970081355 A KR19970081355 A KR 19970081355A KR 100465605 B1 KR100465605 B1 KR 100465605B1
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film
insulating film
interlayer insulating
forming
semiconductor device
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KR1019970081355A
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KR19990061101A (en
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황정웅
차한섭
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로, 아날로그 논리 소자의 캐패시터 유전체로 엠.아이.엠 구조의 유전체로서 Ta2O5막을 사용함으로서 고유전 상수를 가지고 있을 뿐만 아니라, 적절한 처리를 통해 물질 자체가 가지고 있는 높은 누설전류를 줄이게 되면 공정온도가 매우 낮아 금속막 이후의 공정에서 충분히 사용할 수 있으며, 전극에 의한 소모현상을 최대한 억제하여 전압계수 특성의 향상을 통해 높은 정확성, 고유전의 아날로그 캐패시터를 형성할 수 있는 반도체 소자의 제조방법을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and by using a Ta 2 O 5 film as a dielectric of an M.I.M structure as a capacitor dielectric of an analog logic device, not only has a high dielectric constant, but also the material itself through appropriate treatment When the high leakage current is reduced, the process temperature is very low, so that it can be used in the process after the metal film, and it is possible to minimize the consumption phenomenon by the electrode to improve the voltage coefficient characteristics to form a high accuracy and high dielectric analog capacitor. Provided are a method of manufacturing a semiconductor device.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 아날로그 논리 소자의 엠.아이.엠(metal-insulator-metal) 구조에서의 캐패시터 유전체로 Ta2O5막을 사용함으로서 고정확성, 고유전의 아날로그 캐패시터를 형성할 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a high-accuracy, high-k dielectric capacitor is used by using a Ta 2 O 5 film as a capacitor dielectric in an M.I.M (metal-insulator-metal) structure of an analog logic device. It relates to a technology that can be formed.

일반적으로, 캐패시터 용량은 C = ∈

Figure pat00001
로 알려져 있다. 따라서 용량(C)를 극대화 시키는 방법은 면적(A)를 넓게 하거나, 전극판 간격(d)를 좁게 하거나 또는 유전 상수가 높은 물질을 사용하는데 유전 상수가 높은 물질은 예를들어 Ta2O5, TiO2, SrTiO3등이 있으나, 상기 박막의 특성이나 신뢰도에서 그 특성이 우수하지 못하다.Typically, the capacitor capacity is C = ∈
Figure pat00001
Known as Therefore, the method of maximizing the capacity (C) is to widen the area (A), to narrow the electrode plate spacing (d), or to use a material with a high dielectric constant, such as Ta 2 O 5 , TiO 2 , SrTiO 3 and the like, but the characteristics are not excellent in the characteristics and reliability of the thin film.

또한, 면적(A)를 극대화 시키는 방향으로 기술들이 개발되고 있으나, 제한된 셀 면적에서 (A)를 극대화시키면 필연적으로 저장전극의 높이가 증가하거나, 제조공정이 복잡해진다.In addition, techniques have been developed to maximize the area (A), but maximizing (A) in a limited cell area inevitably increases the height of the storage electrode or complicated manufacturing process.

한편, 종래의 아날로그(analog) 캐패시터 구조는 폴리실리콘막/절연막/폴리실리콘막 전극구조로 이루어져 있다. 이 경우 폴리실리콘막에 불순물을 주입하여 전극(electrode) 역할을 충분히 할 수 있도록 해주고 있으나, 전극에 전압 인가시 폴리실리콘막 전극의 소모(depletion)로 인해 전압계수(voltage coefficient) 특성의 악화를 가져온다. On the other hand, the conventional analog capacitor structure is composed of a polysilicon film / insulating film / polysilicon film electrode structure. In this case, an impurity is injected into the polysilicon film to fully function as an electrode, but when the voltage is applied to the electrode, deterioration of the voltage coefficient characteristic occurs due to depletion of the polysilicon film electrode. .

따라서, 이를 해결하기 위해서는 전극 소모가 없는 금속막 전극을 사용하여야 하나 금속막과 금속막 사이의 캐패시터 유전체(dielectric)로 쓸수 있는 적절한 물질이 없어 이 구조를 구현하지 못하고 있다.Therefore, in order to solve this problem, a metal film electrode without electrode consumption should be used, but there is no suitable material that can be used as a capacitor dielectric between the metal film and the metal film.

이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 고유전 상수(high dielectric constant)를 가지고 있을 뿐만 아니라, 적절한 처리를 통해 물질 자체가 가지고 있는 높은 누설전류를 줄이게 되면 공정온도가 매우 낮아 금속막 이후의 공정에서 충분히 사용할 수 있는 아날로그 캐패시터의 유전체로서 Ta2O5막을 사용함으로서 전극에 의한 소모현상을 최대한 억제하여 전압계수 특성의 향상을 통해 높은 정확성, 고유전의 아날로그 캐패시터를 형성할 수 있으며, 소자의 신뢰성을 향상시키는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Thus, the present invention is to solve the above problems, not only has a high dielectric constant (high dielectric constant), but also by reducing the high leakage current of the material itself through appropriate treatment process temperature is very low after the metal film By using Ta 2 O 5 film as the dielectric of the analog capacitor which can be used in the process of, it is possible to minimize the consumption phenomenon by the electrode and to improve the voltage coefficient characteristics to form the high accuracy, high dielectric analog capacitor. It is an object of the present invention to provide a method for manufacturing a semiconductor device that improves reliability.

상기 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 아날로그 캐패시터 제조방법은 소정의 하부 구조물을 구비하는 반도체 기판 상부에 형성되어 있는 절연막상에 제1 금속배선을 형성하는 공정과, 상기 제1 금속배선 상부에 층간절연막을 형성하는 공정과, 상기 제1 금속배선의 상부 표면이 노출되는 콘택홀을 형성하는 공정과, 상기 구조의 전표면에 Ta2O5막과 TiN막을 순차적으로 형성하는 공정과, 상기 콘택홀을 매립하는 콘택플러그를 형성하는 공정과, 상기 구조의 전표면에 제2 금속배선을 형성하는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, an analog capacitor manufacturing method of a semiconductor device according to the present invention includes a process of forming a first metal wiring on an insulating film formed on an upper surface of a semiconductor substrate having a predetermined lower structure, and the first metal wiring. Forming an interlayer insulating film thereon; forming a contact hole exposing the upper surface of the first metal wiring; and sequentially forming a Ta 2 O 5 film and a TiN film on the entire surface of the structure; And forming a contact plug to fill the contact hole, and forming a second metal wiring on the entire surface of the structure.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 1a 및 도 1b는 본 발명에 따른 반도체 소자의 제조공정도이다.1A and 1B are manufacturing process diagrams of a semiconductor device according to the present invention.

먼저, 반도체 기판(도시되지 않음) 상부에 소정의 하부 구조물들, 예컨대 소자분리 산화막과, 모스 전계효과 트랜지스터, 비트선, 캐패시터 등을 형성한 다음, 산화막 재질의 절연막(10)을 형성하고, 상기 절연막(10) 상부에 Al막 또는 Cu막으로 이루어진 제1 금속배선(12)을 형성한 후, 상기 구조의 전표면에 제1 층간절연막(14)과 제2 층간절연막(16)을 순차적으로 형성한다. 이 때, 상기 제1 층간절연막(14)은 13000 ∼ 15000Å 두께의 고밀도 플라즈마 화학기상증착(high density plasma chemical vapor deposition oxide 이하, HDPCVD 라 칭함) 산화막으로 형성하며, 상기 제2 층간절연막(16)은 300 ∼ 700Å 두께의 O3-TEOS 산화막으로 형성한다.First, predetermined lower structures such as a device isolation oxide film, a MOS field effect transistor, a bit line, a capacitor, and the like are formed on a semiconductor substrate (not shown), and then an insulating film 10 made of an oxide film is formed. After forming the first metal wiring 12 made of an Al film or a Cu film on the insulating film 10, the first interlayer insulating film 14 and the second interlayer insulating film 16 are sequentially formed on the entire surface of the structure. do. In this case, the first interlayer insulating film 14 is formed of an oxide film of high density plasma chemical vapor deposition oxide (hereinafter referred to as HDPCVD) having a thickness of 13000 to 15000 Å, and the second interlayer insulating film 16 is It is formed of an O 3 -TEOS oxide film having a thickness of 300 to 700 GPa.

그 다음, 상기 제2 및 제1 층간절연막(16),(14)에서 콘택마스크를 이용한 식각공정으로 상기 제1 금속배선(12)의 상부 표면을 노출시키는 콘택홀을 형성하고, MIM 구조의 아날로그 캐패시터의 유전체로 상기 구조의 전표면에 Ta2O5막(18)과 TiN막(20)을 순차적으로 형성한다.Next, contact holes are exposed in the second and first interlayer insulating layers 16 and 14 to expose the upper surface of the first metal wiring 12 by an etching process using a contact mask, and an analog of MIM structure is formed. The Ta 2 O 5 film 18 and the TiN film 20 are sequentially formed on the entire surface of the structure using the dielectric of the capacitor.

이 때, 상기 Ta2O5막(18)은 400 ∼ 450℃에서 저압화학기상증착(Low Pressure CVD, 이하 LPCVD라 칭함)에 의해 100 ∼ 500Å 두께로 형성하며, 상기 TiN막(20)은 500 ∼ 700Å 두께로 형성한다.At this time, the Ta 2 O 5 film 18 is formed to a thickness of 100 ~ 500 kPa by low pressure chemical vapor deposition (Low Pressure CVD, hereinafter referred to as LPCVD) at 400 ~ 450 ℃, the TiN film 20 is 500 It is formed to a thickness of -700 kPa.

또한 상기 TiN막(20) 형성전(前) O3 플라즈마를 이용하여 400 ∼ 500℃ 에서 30 ∼ 90분간 열처리공정을 실시하여 상기 Ta2O5막(18)이 가지고 있는 높은 누설전류 특성을 완화시켜 준다(도 1a 참조).In addition, by performing an annealing process at 400 to 500 ° C. for 30 to 90 minutes using an O 3 plasma before forming the TiN film 20, the high leakage current characteristic of the Ta 2 O 5 film 18 is alleviated. (See Fig. 1a).

다음, 상기 콘택홀을 메우는 W막을 형성하고 화학적 기계적연마(Chemical Mechanical Polishing 이하, CMP) 공정을 실시하여 상기 제1 층간절연막(14)이 노출될 때까지 평탄화하여 W막 패턴으로 된 콘택플러그(22)을 형성한 후, 전표면에 Al막 또는 Cu막 패턴으로 이루어진 제2 금속배선(24)을 형성한다(도 1b 참조).Next, a contact film 22 having a W film pattern is formed by forming a W film filling the contact hole and performing a chemical mechanical polishing (CMP) process until the first interlayer insulating film 14 is exposed. ), A second metal wiring 24 formed of an Al film or Cu film pattern is formed on the entire surface (see FIG. 1B).

상기한 바와 같이 본 발명에 따르면, 엠.아이.엠(metal-insulator-metal) 구조의 아날로그 캐패시터의 유전막으로서 Ta2O5막을 사용함으로서 전극에 의한 소모 현상을 최대한 억제하여 전압계수 특성의 향상을 통해 높은 정확성, 고유전의 아날로그 캐패시터를 형성할 수 있으며, 소자의 신뢰성을 향상시키는 이점이 있다.As described above, according to the present invention, by using a Ta 2 O 5 film as the dielectric film of the M.I.M (metal-insulator-metal) analog capacitor, the consumption phenomenon caused by the electrode can be minimized to improve the voltage coefficient characteristics. This allows the formation of high accuracy, high dielectric analog capacitors, and improves device reliability.

도 1a 및 도 1b는 본 발명에 따른 반도체 소자의 제조공정도 1A and 1B are a manufacturing process diagram of a semiconductor device according to the present invention

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10 : 절연막 12 : 제1 금속배선10 insulating film 12 first metal wiring

14 : 제1 층간절연막 16 : 제2 층간절연막14: first interlayer insulating film 16: second interlayer insulating film

18 : Ta2O5막 20 : TiN막18: Ta 2 O 5 film 20: TiN film

22 : 콘택플러그 24 : 제2 금속배선22: contact plug 24: second metal wiring

Claims (8)

반도체 소자의 아날로그 캐패시터 제조방법에 있어서,In the analog capacitor manufacturing method of a semiconductor device, 소정의 하부 구조물을 구비하는 반도체 기판 상부에 형성되어 있는 절연막상에 제1 금속배선을 형성하는 공정과,Forming a first metal wiring on an insulating film formed on the semiconductor substrate having a predetermined lower structure; 상기 제1 금속배선 상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film on the first metal wiring; 상기 제1 금속배선의 상부 표면이 노출되는 콘택홀을 형성하는 공정과,Forming a contact hole exposing an upper surface of the first metal wiring; 상기 구조의 전표면에 Ta2O5막과 TiN막을 순차적으로 형성하는 공정과,Sequentially forming a Ta 2 O 5 film and a TiN film on the entire surface of the structure; 상기 콘택홀을 매립하는 콘택플러그을 형성하는 공정과,Forming a contact plug to fill the contact hole; 상기 구조의 전표면에 제2 금속배선을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 아날로그 캐패시터 제조방법.And forming a second metal wiring on the entire surface of the structure. 제1항에 있어서, 상기 층간절연막은 제1 층간 절연막 및 제2 층간 절연막의 적층 구조로 형성하되, 상기 제1 층간절연막은 13000 ∼ 15000Å 두께의 HDPCVD 산화막으로 형성하고, 상기 제2 층간절연막은 300 ∼ 700Å 두께의 O3-TEOS 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 아날로그 캐패시터 제조방법.The method of claim 1, wherein the interlayer insulating film is formed of a laminated structure of a first interlayer insulating film and a second interlayer insulating film, wherein the first interlayer insulating film is formed of an HDPCVD oxide film of 13000 ~ 15000Å thickness, the second interlayer insulating film 300 A method of manufacturing an analog capacitor for a semiconductor device, characterized by forming an O 3 -TEOS oxide film having a thickness of ˜700 GHz. 제1항에 있어서, 상기 Ta2O5막은 400 ∼ 450℃에서 LPCVD법에 의해 100 ∼ 500Å 두께로 형성된 것을 특징으로 하는 반도체 소자의 아날로그 캐패시터 제조방법.2. The method of claim 1, wherein the Ta 2 O 5 film is formed to a thickness of 100 to 500 kHz by LPCVD at 400 to 450 ° C. 제1항에 있어서, 상기 Ta2O5막 형성 후 O3 플라즈마를 이용하여 400 ∼ 500℃ 에서 30 ∼ 90분간 열처리공정을 추가로 실시하는 것을 특징으로 하는 반도체 소자의 아날로그 캐패시터 제조방법.The method of manufacturing an analog capacitor of a semiconductor device according to claim 1, wherein after the Ta 2 O 5 film is formed, a heat treatment step is further performed at 400 to 500 ° C. for 30 to 90 minutes using an O 3 plasma. 제1항에 있어서, 상기 TiN막은 500 ∼ 700Å 두께로 형성된 것을 특징으로 하는 반도체 소자의 아날로그 캐패시터 제조방법.2. The method of claim 1, wherein the TiN film is formed to a thickness of 500 to 700 GPa. 제1항에 있어서, 상기 콘택플러그는 W막으로 형성하는 것을 특징으로 하는 반도체 소자의 아날로그 캐패시터 제조방법.The method of claim 1, wherein the contact plug is formed of a W film. 제6항에 있어서, 상기 콘택플러그는 W막을 전면 증착후, CMP 방법으로 층간절연막을 노출시켜 형성하는 것을 특징으로 하는 반도체 소자의 아날로그 캐패시터 제조방법.The method of claim 6, wherein the contact plug is formed by exposing the W film on the entire surface and then exposing the interlayer insulating film by a CMP method. 제1항에 있어서, 상기 제1 및 제2 금속배선은 Al막 또는 Cu막으로 형성된 것을 특징으로 하는 반도체 소자의 아날로그 캐패시터 제조방법.The method of claim 1, wherein the first and the second metal wirings are formed of an Al film or a Cu film.
KR1019970081355A 1997-12-31 1997-12-31 Manufacturing method of semiconductor device KR100465605B1 (en)

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JP3967544B2 (en) 1999-12-14 2007-08-29 株式会社東芝 MIM capacitor
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