KR100334529B1 - Capacitor Formation Method of Semiconductor Device - Google Patents

Abstract

The present invention relates to a method for forming a capacitor of a semiconductor device, in which a lower electrode and an upper electrode are formed of a Pt-based metal layer in a capacitor using a Ta ₂ O ₅ film as a dielectric film to reduce the thickness of the effective oxide film of the Ta ₂ O ₅ film. By improving the electrical characteristics of the capacitor, and forming a precious metal storage electrode of the desired height by using a core insulating film to increase the surface area of the storage electrode while simplifying the process, thereby improving the reliability and yield of the semiconductor device.

Description

Capacitor Formation Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device. In particular, when a Pt-based metal layer is used as an electrode material in a capacitor forming process using a Ta ₂ O ₅ film as a dielectric film, a storage electrode having a desired height is formed using a core insulating film. As a result, the present invention relates to a method for simplifying a process, reducing a step, and improving an electrical property of a capacitor, thereby improving characteristics and yield of a semiconductor device.

Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size.

In particular, in a DRAM device composed of one MOS transistor and a capacitor, a material having a high dielectric constant is used as the dielectric film, a thickness of the dielectric film is increased, or the surface area of the charge storage electrode is increased to increase the capacitance of the capacitor. There is a way.

Although not shown, looking at the capacitor manufacturing method of the semiconductor device according to the prior art as follows.

First, a device isolation oxide film and a gate oxide film are formed on a semiconductor substrate, a MOS field effect transistor and a bit line including a gate electrode and a source / drain electrode are formed, and then an interlayer insulating film is formed on the entire surface of the structure.

Next, a charge storage electrode contact hole is formed by removing an interlayer insulating layer on an upper portion of the source / drain electrode, which is intended to be a charge storage electrode contact, and polycrystalline a charge storage electrode contacting the source / drain electrode through the contact hole. After forming a silicon layer pattern, a dielectric film having an oxide film, a nitride film, or an oxide film-nitride film-oxide film laminated structure is formed on the surface of the charge storage electrode, and a plate electrode is formed on the dielectric film to complete the capacitor.

In the capacitor of the semiconductor device according to the prior art as described above, the dielectric film requires high dielectric constant, low leakage current density, high dielectric breakdown voltage, and stable interfacial characteristics with the upper and lower electrodes. The oxide film has a dielectric constant of about 3.8. The nitride film is relatively small at about 7.2, and the polysilicon layer used as the electrode has a relatively high resistivity of about 800 to 1000 mu OMEGA cm.

Therefore, in order to increase the capacitance of the capacitor, a high dielectric film such as a Ta ₂ O ₅ film is used as a gigabit DRAM dielectric film. The Ta ₂ O ₅ film is used to form a storage electrode in a cylindrical shape to secure sufficient capacitance at a small cell area, and to form a hemispherical silicon (HSG) to increase the surface area.

However, when a capacitor having a polycrystalline silicon layer / Ta ₂ O ₅ / TiN laminated structure is formed, an effective oxide film thickness of the Ta ₂ O ₅ film is 30 because of an oxide film that is inevitably present between the polysilicon layer and the Ta ₂ O ₅ film. It has a high value in the range of ˜35 kHz. However, when Pt or Ir, which is a noble metal having excellent oxidation resistance, is used as the electrode material, the effective oxide film thickness of the Ta ₂ O ₅ film can be reduced to 10 to 15 kPa.

However, Pt or Ir is a chemically very stable material, and since the vapor pressure of by-products generated during the etching process is low, it is not easily removed, so it is difficult to obtain an etching surface of 75 ° or more, and thus 0.5 to 0.5 in a pattern having a space of 0.2 μm or less. It is difficult to form a storage electrode having a height of 1.0 μm.

In order to solve the above problems of the prior art, a Pt-based metal layer is formed in a capacitor forming method using a Ta ₂ O ₅ or BST ((Ba ₁ - _x SR _x ) TiO ₃ ) film as a dielectric film. Using as a material, using a core insulating film to form a storage electrode having a desired height to enable high integration of the semiconductor device, and to reduce the thickness of the effective oxide film formed between the dielectric film and the storage electrode to improve the electrical characteristics of the capacitor Accordingly, an object of the present invention is to provide a method of forming a capacitor of a semiconductor device, thereby improving the characteristics and reliability of the semiconductor device.

1 to 8 are cross-sectional views showing a capacitor forming method of a semiconductor device according to the present invention.

〈Explanation of the Signs of Major Parts of Drawings〉

11 semiconductor substrate 13 interlayer insulating film

15: storage electrode contact plug 17: first diffusion barrier

19: second diffusion barrier film 21: core insulation film

23: adhesive layer 25: metal layer for the lower electrode

27: high dielectric film 29: metal layer for the upper electrode

In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention,

Forming an interlayer insulating film having a storage electrode contact plug on the semiconductor substrate having a predetermined lower structure formed thereon;

Forming a diffusion barrier layer on the interlayer dielectric layer and connected to the storage electrode contact plugs;

Etching the diffusion barrier layer using a storage electrode mask;

Forming a core insulating film on the diffusion barrier to expose both edges of the diffusion barrier to a predetermined thickness;

Sequentially forming an adhesive layer and a first metal layer for the lower electrode on the entire surface;

Forming a first metal layer spacer on a sidewall of the core insulating layer by etching the first metal layer and the adhesive layer for the lower electrode by a front etching process;

Sequentially forming a Ta ₂ O ₅ film or a high dielectric film of BST ((Ba ₁ - _x SR _x ) TiO ₃ ) material on the entire surface and a second metal layer for the upper electrode;

It is characterized by including a step of rapid heat treatment and tubular heat treatment.

Hereinafter, with reference to the accompanying drawings will be described in detail.

1 to 8 are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the present invention.

First, lower structures such as an isolation layer (not shown), a gate oxide layer (not shown), a gate electrode (not shown), and a bit line (not shown) are formed on the semiconductor substrate 11.

Next, the interlayer insulating film 13 is formed on the entire surface.

Next, the interlayer insulating layer 13 is etched using the storage electrode contact mask as an etching mask to form a storage electrode contact hole (not shown).

Next, a polysilicon layer is formed on the interlayer insulating layer 13 to fill the storage electrode contact hole. At this time, the polysilicon layer is formed to a thickness of 500 ~ 3000Å by chemical vapor deposition (CVD) method.

The storage silicon contact plug 15 is formed by removing the entire surface etching or chemical mechanical polishing (CMP) process of the polysilicon layer. (See Fig. 1)

Next, a first diffusion barrier 17 and a second diffusion barrier 19 are formed on the interlayer insulating layer 13 to be connected to the storage electrode contact plug 15. At this time, the first diffusion barrier 17 is formed of a Ti film 100 ~ 1000 Å thick, the second diffusion barrier 19 is formed of a TiSiN film 200 ~ 1000 Å thick. The second diffusion barrier 19 may be formed of a TiAlN film, a TaSiN film, or a TaAlN film in addition to the TiSiN film. (See Fig. 2)

Next, the second diffusion barrier 19 and the first diffusion barrier 17 are etched using a storage electrode mask that protects a wider area than the storage electrode contact plug 15 and protects a portion intended as the storage electrode. do. (See Fig. 3)

Next, a core insulating film 21 is formed over the entire surface. Here, the core insulation layer 21 may be formed of an oxide film, phospho silicate glass (hereinafter referred to as PSG), borophospho silicate glass (hereinafter referred to as BPSG) or nitride film. To form a thickness of 3000 ~ 15000Å. (See Fig. 4)

Next, a photoresist pattern (not shown) is formed on the core insulation layer 21 to protect a portion of the second diffusion barrier layer 19 as a storage electrode.

Next, the core insulation layer 21 is removed by a dry etching method using the photoresist pattern as an etching mask, and then the photoresist pattern is removed. (See Fig. 5)

Next, an adhesion layer 23 is formed on the entire surface of the core insulating layer 21 to improve adhesion between the core insulating layer 21 and the lower electrode formed by a subsequent process by chemical vapor deposition. At this time, the adhesive layer 23 using TiCl ₄ / NH ₃ or tetra dimethyl amino titanium (TDMAT) or tetra di-ethyl amino titanium (TDMET) The TiN film may be formed to a thickness of 200 to 500 GPa, or may be formed of a Ti or WN film instead of the TiN film.

Next, the lower electrode metal layer 25 is deposited on the adhesive layer 23 by 200 to 1000 kPa by a metal organic chemical vapor deposition (MOCVD) method. The lower electrode metal layer 25 may be formed using a metal layer such as a Pt film, an Ir film, a Ru film, an Iro ₂ film, or a RuO ₂ film. (See FIG. 6)

Next, the lower electrode metal layer 25 and the adhesive layer 23 are etched entirely to form a spacer having an upper portion separated from the sidewall of the core insulating layer 21. (See Fig. 7)

Next, a high dielectric film 27 is formed on the entire surface by chemical vapor deposition. The high dielectric film 27 may be formed using a Ta ₂ O ₅ film or a BST ((Ba _1-x Sr _x ) TiO ₃ ) film. The high dielectric film 27 is formed to have a thickness of 50 to 200 Å at 300 to 450 ° C. using a chemical vapor deposition method.

Next, the upper electrode metal layer 29 is formed on the high dielectric film 27 to a thickness of 200 to 1000 Å at 200 to 500 ° C. using an organometallic chemical vapor deposition method. The upper electrode metal layer 29 may be formed of a metal layer such as a Pt film, an Ir film, a Ru film, an Iro ₂ film, a RuO ₂ film, a TiN film, or a WN film. (See FIG. 8)

Thereafter, a rapid thermal anneal process and a tubular anneal process are performed to complete the capacitor formation process of the semiconductor device.

As described above, in the capacitor forming method of the semiconductor device according to the present invention, in the capacitor using the Ta ₂ O ₅ film as the dielectric film, the thickness of the effective oxide film of the Ta ₂ O ₅ film is reduced by using the lower electrode and the upper electrode as the metal layer. This improves the electrical characteristics of the capacitor and reduces the step between the cell and ferry sections. The core insulating film is used to form metal storage electrodes of desired height, thereby increasing the surface area of the storage electrodes in highly integrated semiconductor devices and simplifying the process. There is an advantage of improving the reliability and yield of the semiconductor device.

Claims (11)

Forming an interlayer insulating film having a storage electrode contact plug on the semiconductor substrate having a predetermined lower structure formed thereon; Forming a diffusion barrier layer on the interlayer dielectric layer and connected to the storage electrode contact plugs; Etching the diffusion barrier layer using a storage electrode mask; Forming a core insulating film on both sides of the etched diffusion barrier to expose both edges of the diffusion barrier to a predetermined thickness; Sequentially forming an adhesive layer and a first metal layer for the lower electrode on the entire surface; Forming a first metal layer spacer on a sidewall of the core insulating layer by etching the first metal layer and the adhesive layer for the lower electrode by a front etching process; Sequentially forming a Ta ₂ O ₅ film or a high dielectric film of BST ((Ba ₁ - _x SR _x ) TiO ₃ ) material on the entire surface and a second metal layer for the upper electrode; A method of forming a capacitor of a semiconductor device comprising the step of rapid heat treatment and tubular heat treatment. The method of claim 1, And the storage electrode contact plug is formed of a polycrystalline silicon layer. The method of claim 1, The diffusion barrier is a capacitor formation method of a semiconductor device, characterized in that the laminated structure of the Ti / TiSiN film. The method of claim 3, wherein And wherein the TiSiN film is formed of a TiAlN film, a TaSiN film, or a TaAlN film. The method of claim 1, The core insulation film is formed of an oxide film, a nitride film, PSG or BPSG to form a thickness of 3000 ~ 15000kPa capacitor of a semiconductor device. The method of claim 1, And the adhesive layer forms a TiN film, a Ti film, or a WN film at a thickness of 200 to 500 GPa. The method of claim 1, The first metal layer is a capacitor forming method of a semiconductor device, characterized in that to form a thickness of 200 ~ 1000 방법 at 200 ~ 500 ℃ using an organometallic chemical vapor deposition method. The method of claim 1, Wherein the first metal layer is formed using a Pt film, an Ir film, a Ru film, an Iro ₂ film, or a RuO ₂ film. The method of claim 1, The high dielectric film is a capacitor formation method of a semiconductor device, characterized in that to form a 50 ~ 200Å thickness at 300 ~ 450 ℃ using chemical vapor deposition method. The method of claim 1, The second metal layer is a capacitor forming method of a semiconductor device, characterized in that formed using a metal organic chemical vapor deposition method at a thickness of 200 ~ 1000Å at 200 ~ 500 ℃. The method of claim 1, And the second metal layer is formed using a Pt film, an Ir film, a Ru film, an Iro ₂ film, a RuO ₂ film, a TiN film, or a WN film.