KR20010059002A - A method for forming capacitor in semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a capacitor of a semiconductor device is provided, which dose not need a specific process for forming a seed layer in using an Electro Chemical Deposition method and prevents a diffusion preventing film from being degraded in a next thermal process. CONSTITUTION: The method includes eight steps. The first step is to form a contact hole for an upper electrode which penetrates an interlayer dielectric film and exposes a silicon substrate. The second step is to form an iridium film(14) on the surface of a resultant of the first step. The third step is to form an amorphous Si-Ir-O film(13) to the boundary surface between the silicon substrate and the iridium film by performing the first thermal process under an oxygen atmosphere. The fourth step is to form a sacrificial film on the upper portion of a resultant of the third step. The fifth step is to define the lower electrode area by selectively etching the sacrificial film, but expose the iridium film into the contact hole. The sixth step is to form a conductive film(16) for the lower electrode using an Electro Chemical Deposition method on the upper portion of the exposed iridium film. The seventh step is to remove the sacrificial film and the exposed iridium film sequentially. The eighth step is to sequentially form a dielectric film and a conductive film(18) for the upper electrode on the upper portion of a resultant of the seventh step.

Description

A method for forming capacitor in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a capacitor of a highly integrated memory device using a high dielectric material or ferroelectric material as a dielectric film.

Currently, semiconductor memory devices can be classified into random access memory (RAM) and read only memory (ROM). In particular, the RAM is divided into a dynamic RAM (hereinafter referred to as DRAM) and a static RAM, among which a DRAM is a unit cell with one transistor and one capacitor. This configuration is leading the memory market because it is most advantageous in density.

On the other hand, due to the progress of high integration, memory capacity has increased by four times in three years, and now 256M DRAM and 1G DRAM are approaching the mass production stage.

As the integration degree of DRAM increases, the area of the memory cell should decrease to 0.5 μm ² for 256M DRAM and the area of the capacitor, which is one of the basic components of the cell, to 0.3 μm ² or less. For this reason, the technology used in the conventional semiconductor process is starting to show a limit above 256M DRAM.

In other words, in order to obtain the required capacitance when manufacturing a capacitor using SiO ₂ / Si ₃ N ₄ , which is a dielectric material used in 64M DRAM, the area occupied by the capacitor is the cell area even though the thickness of the thin film is as thin as possible. It should be over six times.

For this reason, a method of increasing the surface area for securing the capacitance has been proposed and research on it has been continued until now. In order to increase the surface area of the lower electrode of the capacitor, various techniques have been proposed, such as a three-dimensional stack capacitor structure, a trench capacitor structure, or a technique using a hemispherical polysilicon film.

However, in devices larger than 256M DRAM, the dielectric material of traditional Oxide Nitride Oxide (ONO) material can no longer reduce the thickness to increase the capacitance, and the process is too complicated to make the structure more complex to increase the surface area. This is accompanied by a rise in manufacturing cost and a drop in yield.

To solve this problem, high dielectric materials such as tantalum oxide films (Ta ₂ O ₅ ), (Ba, Sr) TiO ₃ (BST), which have a higher dielectric constant than those of conventional ONO materials, are used as dielectric materials. It is adopted as a dielectric film of a capacitor.

However, the dielectric constant of such a high dielectric material is greatly changed depending on the lower electrode of the capacitor, and the results of the previous studies are known to show the best dielectric properties when deposited on a metal material.

Therefore, metals such as platinum (Pt), iridium (Ir), rhodium (Rh), ruthenium (Ru), and the like have been mentioned as electrode materials for high-k dielectric capacitors instead of conventionally used polysilicon.

Meanwhile, in the high-k dielectric capacitor according to the prior art, a contact plug for electrical connection with a lower electrode is formed using doped polysilicon, and then silicon (Si) and oxygen (O ₂ ) are diffused between the contact plug and the lower electrode. In order to prevent this, a nitride diffusion barrier such as TiN, TaN, TiAlN, TaSiN has been used.

However, these nitride-based diffusion barrier films are formed at high temperature after formation of the high dielectric film and then oxidize during heat treatment to form a low dielectric constant layer, thereby reducing the dielectric constant of the high dielectric film. There is a problem of stress. In consideration of these problems, when the temperature is lowered during the subsequent heat treatment performed after the formation of the high-k dielectric film, there is a problem that the dielectric properties are lowered.

In addition, such a nitride-based diffusion barrier typically uses an ohmic contact layer such as titanium silicide or cobalt silicide between polysilicon plugs for ohmic contact, which increases the total number of processes. Doing.

On the other hand, in order to obtain a capacitor having a higher dielectric constant than when forming a high dielectric capacitor having a stack structure, the height of the lower electrode should be formed high to increase the contact area with the high dielectric film, which is used as the lower electrode material. Metals such as platinum, iridium, and ruthenium are problematic in that their etching is not easy. In consideration of these problems, there have been attempts to use the lower electrode by using an electrochemical deposition (ECD) method. However, the lower electrode forming process using the ECD method requires a separate seed layer forming process using chemical vapor deposition (CVD) or physical vapor deposition (PVD). Therefore, there is a problem in that the productivity of the device is lowered due to the increase in the number of processes.

On the other hand, this problem is applied to the process of forming a ferroelectric capacitor similar to a general high dielectric capacitor, except for using a ferroelectric film.

An object of the present invention is to provide a method for forming a capacitor which can avoid a separate seed layer forming process while applying the ECD method, and can prevent deterioration of the diffusion barrier film by a subsequent thermal process.

1A to 1F are diagrams illustrating a capacitor formation process according to an embodiment of the present invention.

* Brief description of symbols for the main parts of the drawings

10 semiconductor substrate 11 interlayer insulating film

12 silicon nitride film 13 Si-Ir-O layer

14 iridium film 16 conductive film for lower electrode

17: high dielectric film 18: conductive film for the upper electrode

The present invention for achieving the above object is a first step of forming a contact hole for the lower electrode through the predetermined interlayer insulating film to expose the silicon substrate; A second step of forming an iridium film along the entire structure surface of the first step; Performing a first thermal process in an oxygen atmosphere to form an amorphous Si—Ir—O film at an interface between the silicon substrate and the iridium film; A fourth step of forming a sacrificial layer on the entire structure of the third step; A fifth step of selectively etching the sacrificial layer to define a lower electrode region, wherein the iridium layer in the contact hole is exposed; A sixth step of forming a conductive film for a lower electrode by using an electrochemical deposition method on the exposed iridium film; A seventh step of removing the sacrificial layer and removing the exposed iridium layer; And an eighth step of sequentially forming a dielectric film and an upper electrode conductive film on the entire structure.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1A to 1F are flowcharts of forming a high dielectric capacitor according to an embodiment of the present invention.

In the present embodiment, first, as shown in FIG. 1A, a predetermined lower layer process including a MOS transistor, a bit line, and the like is performed on a silicon substrate 10, and an upper part of a silicon oxide film (interlayer insulating film) 11 formed in the process is performed. After the silicon nitride film (SiN _x ) 12 is deposited on the silicon nitride film 12, the silicon nitride film 12 and the silicon oxide film 11 are sequentially etched to form contact holes to expose the junctions of the MOS transistors formed on the silicon substrate 10. . In this case, the silicon nitride film 12 may be formed to a thickness of about 300 to 1000 ,, and may be replaced with a silicon oxynitride film (SiO _x N _y ) having a higher etching selectivity than the silicon oxide film 11.

Next, as illustrated in FIG. 1B, an iridium (Ir) film 14 is thinly deposited to a thickness of about 100 to 500 kPa by chemical vapor deposition (CVD) along the upper surface of the entire structure. The heat treatment is performed to form an amorphous Si—Ir—O layer 13 having a thickness of about 50 to about 200 kHz at the interface between the silicon substrate 10 and the iridium film 14. Here, the Si-Ir-O layer 13 serves as a diffusion barrier to prevent oxygen from diffusing to the silicon substrate 10 during the thermal process of the oxygen atmosphere after the formation of the high dielectric film to be formed thereafter. At the same time, the ohmic contact of the lower electrode is provided.

Next, as shown in FIG. 1C, after the sacrificial oxide film 15 is deposited to a thickness of about 2000 to 15000 상부 over the entire structure, the sacrificial oxide film 15 is exposed to expose the iridium film 14 in the region where the capacitor lower electrode is to be formed. Select). In this case, the sacrificial oxide film 15 is formed using USG (undoped silicate glass) or PSG (phospho silicate glass).

Next, as shown in FIG. 1D, a conductive film 16 for lower electrodes having a desired thickness is formed by ECD. At this time, the lower electrode conductive film 16 is formed to have a thickness of about 2000 to 15000 에서 on the iridium film 14 in contact with the silicon nitride film 13 using platinum (Pt). At this time, the ECD method is performed using the exposed iridium film 14 as a seed layer.

Next, as shown in FIG. 1E, the sacrificial oxide film 15 is removed and the exposed iridium film 14 is selectively removed. Subsequently, in order to stabilize the conductive film 16 for the lower electrode formed by the ECD method, a rapid thermal process (Rapid Thermal Process) for 5 to 180 seconds in an atmosphere of nitrogen (N ₂ ) or argon (Ar) at a temperature of 300 to 850 ° C. RTP) is performed to form the conductive film 16 for the lower electrode.

Subsequently, as shown in FIG. 1F, the high dielectric film 17 is formed to a thickness of about 80 to 400 에 on the entire structure by using the CVD method, and then the upper electrode conductive film 18 is formed on the top of the entire structure. Use to form a thickness of about 300 ~ 1000Å. Subsequently, in order to stabilize the upper electrode conductive film 18 and the high dielectric film 17, a high-temperature thermal process of a mixed gas atmosphere of oxygen / nitrogen (or argon) is performed at a temperature of about 550 to 850 ° C. Complete the high dielectric capacitor formation process. In this case, BST, Ta ₂ O _5, or the like may be used as a material for forming the high dielectric film 17, and a material such as platinum, iridium, or ruthenium may be used as the upper electrode conductive film 18.

In the present invention as described above, the Si-Ir-O layer formed at the interface between the iridium film and the silicon substrate surface simultaneously serves as a diffusion barrier and an ohmic contact layer, and the iridium film uses the ECD method as the conductive film for the lower electrode. The formation of the seed layer also serves to reduce the overall number of processes. In addition, the Si—Ir—O layer has oxidation resistance in which a low dielectric layer is not formed in a subsequent high temperature thermal process.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

In this embodiment described above, a high dielectric film is used as the dielectric film of the capacitor, but ferroelectrics such as (Sr, Bi) Ta ₂ O ₉ (SBT) and Pb (Zr _x Ti _x-1 ) O ₃ (PZT) may be used. Even when the present invention is applied. In addition, although the conductive film material for the lower electrode was formed of a platinum film by applying the ECD method, it is also applicable to a metal such as iridium and ruthenium.

The present invention simplifies the capacitor formation process by reducing the number of processes, and the application of the Si-Ir-O layer allows subsequent thermal processes to be carried out at a sufficiently high temperature, which is effective in improving the dielectric properties and the capacitor properties.

Claims (7)

Forming a contact hole for the lower electrode through the predetermined interlayer insulating film to expose the silicon substrate; A second step of forming an iridium film along the entire structure surface of the first step; Performing a first thermal process in an oxygen atmosphere to form an amorphous Si—Ir—O film at an interface between the silicon substrate and the iridium film; A fourth step of forming a sacrificial layer on the entire structure of the third step; A fifth step of selectively etching the sacrificial layer to define a lower electrode region, wherein the iridium layer in the contact hole is exposed; A sixth step of forming a conductive film for a lower electrode by using an electrochemical deposition method on the exposed iridium film; A seventh step of removing the sacrificial layer and removing the exposed iridium layer; And Eighth step of sequentially forming a dielectric film and an upper electrode conductive film on the entire structure Capacitor formation method of a semiconductor device comprising a. The method of claim 1, After performing the seventh step, And a ninth step of performing a second thermal process for stabilizing the conductive film for the lower electrode. The method according to claim 1 or 2, And the dielectric film is a high dielectric film or a ferroelectric film. The method of claim 1, The method of forming a capacitor of a semiconductor device, characterized in that the iridium film is formed to a thickness of about 100 ~ 500Å by chemical vapor deposition. The method of claim 2, The ninth step, A method of forming a capacitor of a semiconductor device, characterized in that the rapid thermal process for 5 to 180 seconds in a nitrogen or argon atmosphere of about 300 ~ 850 ℃ temperature. The method according to claim 1 or 5, The Si-Ir-O film is a capacitor forming method of a semiconductor device, characterized in that formed to a thickness of 50 ~ 200 ~. The method according to claim 1 or 2, And the lower electrode conductive film and the upper electrode conductive film are any one of platinum, iridium, and ruthenium.