KR20040060006A - Method for manufacturing semiconductor memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor memory device is provided to be capable of minimizing the oxidation of a storage node contact plug in annealing a dielectric film. CONSTITUTION: Interlayer dielectrics(125,135) with a storage node contact plug(140) are formed on a semiconductor substrate(100). An oxide pillar(150a) is formed on the interlayer dielectric to shield the storage node contact plug. A dielectric film(155) is formed on the interlayer dielectric and the oxide pillar and annealed. An upper electrode and an insulating layer are formed on the dielectric film and selectively etched to expose the oxide pillar. By removing the exposed oxide pillar, the storage node contact plug is exposed. A lower electrode is formed to contact the exposed storage node contact plug.

Description

Method for manufacturing semiconductor memory device

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a semiconductor memory device having a metal-insulator-metal (MIM) capacitor.

In recent years, as the degree of integration of semiconductor devices increases, the area occupied by devices within chips is decreasing. Accordingly, the lower electrode of the capacitor is formed in a three-dimensional form, such as a cylinder (cylinder), fin (fin), or the like to increase the surface area by coating a hemispherical grain on the surface of the lower electrode, to reduce the thickness of the dielectric film A method of using a high dielectric constant or ferroelectric material having high dielectric constant or high dielectric constant as a dielectric film has been proposed.

Here, when a material having a high dielectric constant, such as Ta ₂ O ₅ , HfO BST ((Ba, Sr) TiO ₃ ), is used as the dielectric film, a polysilicon film that has been used as an electrode is used as the capacitor electrode. Difficult to do Accordingly, when a high dielectric film or a ferroelectric film is used as the dielectric film, precious metals such as platinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh), osmium (Os), etc. having a very high work function are used as the capacitor electrode materials. It is used.

Here, a method of manufacturing a general MIM capacitor will be described with reference to FIG. 1.

Referring to FIG. 1, a first interlayer insulating film 20 is formed on a semiconductor substrate 10, for example, a silicon substrate on which a MOS transistor (not shown) and a bit line (not shown) are formed. A contact hole is formed to be in electrical communication with a predetermined portion of the first interlayer insulating layer 20, for example, the source region of the MOS transistor, and then a doped polysilicon film is deposited to sufficiently fill the contact hole. Subsequently, the doped polysilicon layer is etched entirely to form a storage node contact plug 25. Thereafter, the etch stop layer 30 and the second interlayer insulating layer 35 are sequentially stacked on the first interlayer insulating layer 20 on which the storage node contact plug 25 is formed. A predetermined portion of the second interlayer insulating layer 35 and the etch stop layer 30 is etched to expose the storage node contact plug 25 and an adjacent region thereof, thereby defining the capacitor region c.

Subsequently, a lower electrode metal film is deposited on the semiconductor substrate 10 product to be in contact with the exposed storage node contact plug 25, and then the lower electrode metal film is exposed to CMP so that the surface of the second interlayer insulating film 35 is exposed. chemical mechanical polishing or front-side etching to form a lower electrode 40 in the form of a concave. A dielectric film 43 having a high dielectric constant is deposited on the lower electrode and the surface of the second interlayer insulating film 35. At this time, since the dielectric film 43 contains a large amount of impurities and has a low dielectric constant in the deposition state, in order to improve dielectric properties and stability, a rapid thermal process (RTP) or furnace annealing (RTP) is performed at high temperature in an oxygen or inert gas atmosphere. furnace annealing). Thereafter, the upper electrode 45 is formed on the dielectric layer 43 to complete the storage capacitor 50.

However, in the conventional MIM capacitor, during the high temperature heat treatment process to improve the dielectric properties and stability of the dielectric film, oxygen atoms provided in the dielectric film or oxygen atoms provided in the atmosphere composition are diffused to oxidize the storage node contact plug 25. do. Due to the oxidation of the storage node contact plug 25, the contact resistance is increased and the leakage current is also increased.

Meanwhile, in order to solve such a problem, in order to prevent oxidation of the storage node contact plug 25, a barrier metal film such as titanium nitride (TiN) is interposed between the storage node contact plug 25 and the lower electrode 40. Although a technique has been proposed, the above problems still exist.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of minimizing oxidation of a storage node contact plug in a heat treatment process of a dielectric film.

1 is a view for explaining a method of manufacturing a general semiconductor memory device.

2A to 2E are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100 semiconductor substrate 150a oxide film pillar

155 dielectric layer 161 upper electrode

165: third interlayer insulating film 170: lower electrode

In order to achieve the above object of the present invention, the present invention deposits an interlayer insulating film including a storage node contact plug on a semiconductor substrate, and then forms an oxide pillar to shield the storage node contact plug on the interlayer insulating film. do. Then, a dielectric film is deposited on the surface of the interlayer insulating film and the oxide film pillar, and the dielectric film is heat treated. Subsequently, an upper electrode is formed on the surface of the dielectric film, a separation insulating film is deposited on the upper electrode, and then the separation insulating film and the upper electrode are removed to expose the oxide film pillar surface. Subsequently, the exposed oxide pillar is selectively removed to expose the storage node contact plug, and then a lower electrode is formed on the surface of the dielectric layer to be in contact with the exposed storage node contact plug.

Preferably, the dielectric film is formed of one of HfO ₂ , Al ₂ O ₃ / HfO ₂ , Ta ₂ O ₅ , BST, SBT, and PZT films, and the heat treatment process of the dielectric film is performed in an oxygen atmosphere or a nitrogen atmosphere. The heat treatment may be performed by a rapid thermal process (RTP) or furnace annealing at a temperature of 400 to 850 ℃.

The upper electrode may be formed of a metal film such as Ru, TiN, W, Pt or Ir, or a metal oxide film such as RuO ₂ or IrO _2, and forming the upper electrode and forming the separation insulating film. Between the steps, further comprising the step of performing a heat treatment to ensure the interfacial properties of the upper electrode. It is preferable that the heat treatment of the upper electrode is performed at a temperature of 650 ° C. or lower in an oxygen or nitrogen atmosphere.

The separating insulating film may be formed of a material having a selectivity ratio with the oxide pillar, and the removing of the insulating insulating film and the upper electrode to expose the surface of the oxide pillar may include removing the insulating insulating film and the upper electrode. Proceed by chemical mechanical polishing (CMP) or full surface etching.

The method may further include performing a heat treatment to remove the damage of the exposed storage node contact plug surface between the removing of the oxide pillar and the forming of the lower electrode.

The lower electrode may be formed of a metal film such as Ru, TiN, W, Pt or Ir, or a metal oxide film such as RuO ₂ or IrO _2, and the lower electrode may be formed in a space where the oxide pillar is removed. . In addition, the dielectric layer, the upper electrode, and / or the lower electrode may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. 2A through 2E are cross-sectional views of respective processes for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 2A, the device isolation layer 102 is formed in a known manner so as to define an active region in a predetermined portion on the semiconductor substrate 100. In the drawing, for example, a local oxidation silicon (LOCOS) oxide film is illustrated as the device isolation film 102, but a shallow trench isolation (STI) film may be used. Thereafter, a gate insulating film 105 and a conductive layer are deposited on the semiconductor substrate 100, and then patterned to form a gate electrode 110, and spacers 115 are formed on both sides of the gate electrode 110. . Thereafter, impurities are implanted into the semiconductor substrate 100 regions on both sides of the gate electrode 110 to form the source and drain regions 120a and 120b, thereby completing the transistor. In this case, the transistor may be formed as described above, or may employ a self align contact method.

Next, a first interlayer insulating layer 125 is formed on the resultant of the semiconductor substrate 100, and a bit line contact hole is formed by etching the first interlayer insulating layer 125 to expose the drain region 120b. The bit line 130 is formed on the first interlayer insulating layer 125 to be in contact with the exposed drain region 120b in a known manner. As is known, the bit line 130 may extend in a direction orthogonal to the gate electrode 110, that is, the word line.

A second interlayer insulating layer 135 is deposited on the semiconductor substrate 100 on which the bit lines are formed. Thereafter, the second and first interlayer insulating layers 135 and 125 are etched to expose the source region 120a to form a storage node contact hole. Thereafter, the doped polysilicon layer 142 is deposited to sufficiently fill the storage node contact hole, and then etched or CMPed to fill the polysilicon layer 142 in the storage node contact hole. Thereafter, in order to remove a portion of the upper region of the doped polysilicon layer 142, the upper region of the storage node contact hole is partially exposed by performing the front etching again on the doped polysilicon layer 142. Thereafter, a barrier metal film, for example, a titanium metal film 148 is deposited on the resultant, and the titanium metal film 148 is etched entirely so that the second interlayer insulating film 135 is exposed to form a doped polysilicon film ( 142) A barrier metal film (titanium metal film: 148) is buried in the upper portion. At this time, the titanium silicide layer 146 is generated at the contact portion between the doped polysilicon layer 142 and the titanium metal layer 148. In this way, the storage node contact plug 140 is formed in the second interlayer insulating layer 135 and the first interlayer insulating layer 125. Subsequently, a sacrificial oxide layer 150 is deposited on the storage node contact plug 140 and the second interlayer insulating layer 135.

Referring to FIG. 2B, a photoresist pattern (not shown) is formed on the sacrificial oxide layer 150 in a known manner so that the sacrificial oxide layer 150 may include the storage node contact plug 140 and a peripheral region thereof. do. In the form of a photoresist pattern, the sacrificial oxide film 150 is etched to form an oxide film pillar 150a that shields the storage node contact plug 140.

As illustrated in FIG. 2C, the dielectric layer 155 is deposited on the second interlayer insulating layer 135 and the oxide pillar 150a to have a thickness of 50 to 300 μm by chemical vapor deposition (CVD) or atomic layer deposition (ALD). do. At this time, the dielectric film 155 may be a high-k dielectric film such as HfO ₂ , Al ₂ O ₃ / HfO ₂ , Ta ₂ O ₅ , BST, SBT, PZT, and the like, and these dielectric films 155 may be in an amorphous state at the time of deposition. Has Then, to improve the dielectric properties and stability of the dielectric film 155, heat treatment is performed by RTP or furnace annealing at a temperature of 400 to 850 ℃ in an oxygen atmosphere or a nitrogen atmosphere. At this time, during the heat treatment process, since the storage node contact plug 140 is shielded by the oxide pillar 150a without contact with any electrode, oxygen atoms do not diffuse to the storage node contact plug 140, so that the storage node contact plug is not included. 140 is not oxidized.

Next, an upper electrode conductive layer 160 is deposited on the dielectric layer 155 to a thickness of 100 to 5000 kV by CVD or ALD. As the upper electrode conductive layer 160, for example, a metal film such as Ru, TiN, W, Pt or Ir, or a metal oxide film such as RuO ₂ or IrO ₂ may be used. Subsequently, in order to improve the interfacial properties of the upper electrode conductive layer 160, an additional heat treatment process may be performed at a temperature of 650 ° C. or less under an oxygen or nitrogen atmosphere. Even during the low temperature heat treatment process below 650 ° C., since the oxide pillar 150a shields the storage node contact plug 140, the oxidation of the additional storage node contact plug 140 is prevented.

Referring to FIG. 2D, a third interlayer insulating layer 165 is deposited on the conductive layer 160 for the upper electrode. In this case, the third interlayer insulating layer 165 may be formed of a material having an etch selectivity with respect to the oxide pillar 150a. Subsequently, the third interlayer insulating layer 165 and the upper electrode conductive layer 160 are etched or CMP so as to expose the surfaces of the oxide pillars 150a (see FIG. 2C), thereby defining respective upper electrodes 161. The exposed oxide pillars 150a are selectively removed by a wet or dry etching method to expose the storage node contact plug 140. Thereafter, in order to remove process damage of the storage node contact plug 140 when the oxide pillar 150a is removed, heat treatment may be performed at an inert gas atmosphere at a low temperature of 650 ° C. or lower.

As shown in FIG. 2E, the conductive layer for the lower electrode is deposited on the resultant. At this time, the conductive layer for the lower electrode may be the same as the material of the upper electrode 161, by a CVD or ALD method, a thickness of 100 to 5000Å, preferably an oxide film to contact the storage node contact plug 140 The space from which the pillar 150a has been removed is deposited to a thickness sufficient to fill up. Thereafter, the lower electrode conductive layer is etched or CMP-etched to expose the surface of the third interlayer insulating film 165 to form the lower electrode (storage node electrode 170), thereby completing the capacitor 175.

As described in detail above, according to the present invention, a sacrificial oxide pillar is formed on a storage node contact plug, and then dielectric deposition, dielectric film heat treatment, upper electrode deposition, and heat treatment are performed. Accordingly, the storage node contact plug is shielded by the sacrificial oxide pillar during the dielectric film heat treatment process, thereby preventing the diffusion of oxygen atoms, thereby preventing the storage node contact plug from being oxidized.

Further, in the present embodiment, since the upper electrode and the lower electrode are formed after the deposition of the dielectric film, the interface characteristics between the upper and lower electrodes and the dielectric film can be improved.

This invention is not limited only to the above-mentioned embodiment, It can variously change and implement in the range which does not change the summary of this invention.

In the present embodiment, for example, a metal film is used as the lower electrode. However, the same effect can be achieved by using a doped polysilicon film without being limited thereto.

The present invention described above can minimize the oxidation of the storage node contact plug in the heat treatment process of the dielectric film, thereby improving the reliability and yield of the semiconductor device.

Claims (12)

Depositing an interlayer insulating film including a storage node contact plug on a semiconductor substrate; Forming an oxide pillar to shield the storage node contact plug on the interlayer insulating layer; Depositing a dielectric film on surfaces of the interlayer insulating film and the oxide pillar; Heat treating the dielectric film; Forming an upper electrode on the surface of the dielectric layer; Depositing a separation insulating film on the upper electrode; Removing the separation insulating layer and the upper electrode to expose the oxide pillar surface; Selectively removing the exposed oxide pillar to expose a storage node contact plug; And Forming a lower electrode on a surface of a dielectric layer to be in contact with the exposed storage node contact plug. The method of claim 1, The dielectric film is a method of manufacturing a semiconductor memory device, characterized in that formed of one of the film selected from HfO ₂ , Al ₂ O ₃ / HfO ₂ , Ta ₂ O ₅ , BST, SBT, PZT film. The method according to claim 1 or 2, The heat treatment process of the dielectric film is a method of manufacturing a semiconductor memory device, characterized in that the heat treatment is carried out in an oxygen atmosphere or a nitrogen atmosphere and a rapid thermal process (RTP) or furnace annealing method at a temperature of 400 to 850 ℃. The method of claim 1, The upper electrode is formed of a metal film such as Ru, TiN, W, Pt or Ir, or a metal oxide film such as RuO ₂ or IrO ₂ . The method of claim 1, And performing a heat treatment to secure the interfacial properties of the upper electrode between the forming of the upper electrode and the forming of the insulating layer for separation. The method of claim 5, wherein The heat treatment of the upper electrode is a method of manufacturing a semiconductor memory device, characterized in that the temperature of 650 ℃ or less in the oxygen or nitrogen atmosphere. The method of claim 1, And the insulating insulating film is formed of a material having a selectivity ratio with the oxide pillar. The method of claim 1, The removing of the insulating layer and the upper electrode so that the surface of the oxide pillar is exposed, the method of manufacturing a semiconductor memory device, characterized in that to proceed by the chemical mechanical polishing (CMP) or the entire surface etching the separation insulating layer and the upper electrode. . The method of claim 1, And performing a heat treatment to remove the damage of the exposed storage node contact plug surface between removing the oxide pillar and forming the lower electrode. Manufacturing method. The method of claim 1, The lower electrode is formed of a metal film such as Ru, TiN, W, Pt or Ir, or a metal oxide film such as RuO ₂ or IrO ₂ . The method according to claim 1 or 10, And the lower electrode is formed in a space from which the oxide pillar is removed. The method according to claim 1, 2, 4, 10, wherein The dielectric film, the upper electrode and / or the lower electrode is a method of manufacturing a semiconductor memory device, characterized in that formed by CVD (chemical vapor deposition) or ALD (atomic layer deposition) method.