TW523909B - Improvement of super thin conformal nitride for dynamic random access memory capacitor - Google Patents
Improvement of super thin conformal nitride for dynamic random access memory capacitor Download PDFInfo
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- 229910052757 nitrogen Inorganic materials 0.000 claims description 16
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 7
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Abstract
Description
523909523909
五、發明説明(i) 5 - 1發明領域 本發明係關於一種藉由表面感光度的改良以形成優良 的共形度(conformity)之方法。 5-2發明背景: 近來’由於電子設備的廣泛使用,使得動態隨機存取 記憶體(dynamic random access memory ; DRAM)的需 求量快速增加’特別是在資訊工業中有關於電腦硬體方""面 的應用。除了資訊工業方面的應用之外,動態隨機存取記 憶體亦必須經常地用於大型積體電路(large —scale integration ; LSI)、超大型積體電路(very large-scale integration ; VLSI)與超超大型積體電路 (ultra large-scale integration ; ULSI )之中。在下 個世紀中’動態隨機存取記憶體的製造技術仍然扮演著主 要的角色。由於電子、資訊與通訊的產品趨向輕薄短小與 快速的目標發展’因此高密度與大容量之動態隨機存取記 憶體的需求大幅增加。 一高胞(ce 1 1 )密度之記憶體元件自然具有一較高的 記憶體容量’且相對地亦具有較低的製造成本。為了增加 動態隨機存取記憶體元件中的記憶體容量,通常採取增加V. Description of the Invention (i) 5-1 Field of the Invention The present invention relates to a method for forming an excellent conformity by improving the surface sensitivity. 5-2 Background of the Invention: Recently "due to the widespread use of electronic equipment, the demand for dynamic random access memory (DRAM) has rapidly increased", especially in the information industry regarding computer hardware methods " " noodle application. In addition to applications in the information industry, dynamic random access memory must also be frequently used in large-scale integration (LSI), very large-scale integration (VLSI), and ultra-large-scale integration circuits (VLSI). Ultra-large-scale integration (ULSI). In the next century, the manufacturing technology of 'Dynamic Random Access Memory' will still play a major role. As electronics, information, and communications products tend to be thin, light, short, and rapidly developed, demand for high-density and large-capacity dynamic random-access memory has increased dramatically. A high-cell (ce 1 1) density memory element naturally has a higher memory capacity 'and relatively lower manufacturing costs. In order to increase the memory capacity in the dynamic random access memory device, it is usually taken to increase
523909523909
記憶胞密度的策略。高元件密度一般都是藉由減少積體電 路尺寸的方式來施行,如線寬(line width)、線間距距 離(line pitch distance)、電晶體閘極(transist〇r gate)或疋雙電容器(c〇Upied capacitor)。 一典型之動態隨機存取記憶體胞包含有一場效電晶體 (field-effect transistor ;FET)與一電容器,此=容 裔與場效電晶體連結在一起。一動態隨機存取記憶體元件 通常含有大量的排列在配置結構中之動態隨機存取記憶體 胞。每一個動態隨機存取記憶體胞都能夠經由一電容^的 充電狀態來儲存一個二進位資料。一充電之電容器儲&一 個二進位資料” 1 ”,而一放電之電容器則儲存一個二進位 貧料"0 ’’。其中的雙場效電晶體可經由在其汲極區域中之 電壓狀態的應用,來進行充電或是放電的動作。也能夠藉 由位元線(bit line)與字元線(word line)來選擇符曰 合需求的場效電晶體。字元線的特色是與配置在動態隨機 存取記憶體中的每個場效電晶體之閘極連結,而位元線的 特色則是與配置在動態隨機存取記憶體中的每個場效電晶 體之沒極連結。位元線提供電壓狀況給場效電晶體,而字 兀線則是用於控制場效電晶體的開/關之上。經由一對字 元線與位元線的選擇,可得到一符合需求的場效電晶體且 以=進位資料寫入雙電容器中。為了得到雙電容器的充電 狀態’也能夠藉由選擇場效電晶體與轉換位元線至比較器 電路(comparator circuit)中,來讀取已儲存之二進位Strategies for memory cell density. High component density is generally implemented by reducing the size of integrated circuits, such as line width, line pitch distance, transistor gate, or dual capacitors ( c〇Upied capacitor). A typical DRAM cell contains a field-effect transistor (FET) and a capacitor. This means that the capacitor is connected to the field-effect transistor. A dynamic random access memory element usually contains a large number of dynamic random access memory cells arranged in a configuration structure. Each DRAM cell is capable of storing a binary data via the state of charge of a capacitor ^. A charged capacitor stores & a binary data "1", and a discharged capacitor stores a binary " lean " 0 ' '. The dual field effect transistor can be charged or discharged through the application of the voltage state in its drain region. Bit line and word line can also be used to select the field effect transistor that meets the needs. The character line is connected to the gate of each field effect transistor arranged in the dynamic random access memory, and the bit line is connected to each field arranged in the dynamic random access memory. The infinite connection of the effect transistor. The bit line provides the voltage condition to the field effect transistor, while the word line is used to control the on / off of the field effect transistor. Through the selection of a pair of word lines and bit lines, a field-effect transistor that meets the requirements can be obtained and written into the double capacitor with = carry data. In order to obtain the state of charge of the dual capacitor ’, it is also possible to read the stored binary by selecting the field effect transistor and converting the bit line into a comparator circuit.
523909 五、發明說明(X> 資料。玎因而獲得已選擇之動態隨機存取 儲存之二進位資料。 "己憶體月已中的已 電容器=在其頂端電極與底端電極的 ,而此頂端電極與底端電極之間係藉 電: 端電極係連:著場效電晶體的源極。 以口 儲存電荷的總數取決於電容器的電』二:所- )。電流容量與電極表面以及介電 (Capacitance 極表面)且與頂端電極/底端電 比(如底端電 电往/低编電極之間的距離成反比。 通常為了降低元件尺寸的大小 之減小,而此方式亦減少了電 =極的表面隨 :量電;容量口㈣起許多的it例:果 位資料的内容:Π f:置與一漏電流將會造成儲存二進 通常為具有較小的電荷變化之容許度。 重新充電-段dr貧料的内容錯誤,電容器必須要 電循環時間也_ e右疋電流容量較小,則充 每個充電:=二如此更需要經常進行著充電程序。在 能。此期間:行動態隨機存取記憶體的功 容量會具有(dead tiffle),一較小的電流 能效率也合跟装政*日守間,且動態隨機存取記憶體的性 的增幅器,$脾.f 較小的電流容量需要一個更敏感 延將V致更複雜的回路與製造成本的增加。 523909 五、發明說明(4) 我們發現氮化物層的微 如其來的高阻抗’此高阻抗 neck )面積中的多晶矽晶粒 當即點的臨界尺寸減少時, 現將氮化物沉積層變薄時, 重,這很可能使得氧化作用 介面來進行。也有一些證據 化物沉積的期間減緩其表面 (storage node ; SN )與内 dielectric layer ; IP D ) 鑒於上述之種種原因, 件之製造方法以形成具有良 體。 縮將在電容器的節點中導致突 係歸因於在儲存頸(st〇rage (poly grain)之氧化作用, 此現象會越趨嚴重。我們也發 其表面感光度的·問題亦將更嚴 的路徑經由多晶矽/氧化物的 能支持上述之假設,譬如在氮 的感光度’且在儲存節點 層多晶介電層(inter~p〇iy 之間增加額外的薄氮化層。 我們更需要一種新的半導體元 好共形度之動態隨機存取記憶 5 - 3發明目的及概述: 寥於上述之發明背景中’本發明提供一種方 改良動態隨機存取記憶體電容器之护臂# w斤 次可用以 w ~溥共形氮化物。 本發明的目的是在提供一 形成優良共形度的製程方法。 種藉由表面感光度的 在半球狀餘革晶粒輿 e文良來 内層多523909 V. Description of the invention (X > data. I have thus obtained the binary data of the selected dynamic random access storage. &Quot; Capacitors already in the memory of the moon = the top and bottom electrodes, and this The top electrode and the bottom electrode are borrowed: The end electrode is connected: the source of the field effect transistor. The total amount of charge stored in the mouth depends on the capacitor ’s charge. The current capacity is inversely proportional to the electrode surface and the dielectric (Capacitance electrode surface) and the distance between the top electrode / bottom electrode ratio (such as the distance between the bottom electrode and the low electrode). Usually the size is reduced in order to reduce the size of the component And this method also reduces the surface of the electric pole. The amount of electricity is measured by the capacity. For example, the content of the data of the fruit level: Π f: placing and a leakage current will cause the storage binary. Small allowance for change in charge. The content of the recharge-segment dr lean material is wrong, the capacitor must have an electrical cycle time, too. E Right 疋 current capacity is small, then charge each charge: = 2 so more often need to be charged Program. During the period. During this period: the power capacity of the dynamic random access memory will have a dead tiffle, and a small current energy efficiency will also be combined with the installation of the system. Incremental amplifier, $ spleen. F The smaller current capacity requires a more sensitive delay to increase the complexity of the circuit and increase the manufacturing cost. 523909 V. Description of the invention (4) We find that the nitride layer is slightly different. High impedance 'this high impedance Neck) decreases the area of the polysilicon grains in the critical dimension of the point immediately, now a nitride deposited layer is thinned, the weight, it is likely that the interface to the oxidation. There is also some evidence that the surface (storage node; SN) and internal dielectric layer (IP D) during the deposition of the compound slow down due to various reasons mentioned above. The shrinkage caused in the capacitor's node is due to the oxidation at the storage neck (poly grain), this phenomenon will become more serious. We have also made its surface sensitivity and the problem more severe. The path through polycrystalline silicon / oxide can support the above assumptions, such as the sensitivity of nitrogen 'and the addition of a thin thin nitride layer between the polycrystalline dielectric layer (inter ~ poiy) of the storage node layer. We need a more New semiconductor element with good conformity of dynamic random access memory 5-3 Purpose and summary of the invention: Rarely in the above background of the invention 'The present invention provides a protective arm of a modified dynamic random access memory capacitor # WG 次It can be used as w ~ 溥 conformal nitride. The object of the present invention is to provide a process method for forming an excellent conformity. A kind of surface layer is formed on the hemispherical residual leather grains and the inner layer.
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程或:ΐ Γ二)等之更間有\共皁形氮化物可藉由快速熱氮化過 在氮化物沉積的潛伏㈡二氮=用來加以改良。所以 地減緩氧化作用的途徑,且難±、/+更緊袷,廷此夠有效 觸節點的RC。 错由此方法也能大大地改善接 产的ί 2 7步地目的是在提供-種藉由表面感光 -電晶體的底材。料υ;,供:用以形成 電層。然後在此第―:電上,:批覆式第-介 电層上形成一弟一光阻層,而此第 - $阻層係藉由定義與蝕刻的方式來形成一接觸通道( contact openi叫)。接著形成一第一導電層並填滿接觸 tf* Ϊ __ 為了形成一接觸節點,進行一蝕刻程序以便移除 f 一 v電層。所以在第一介電層與接觸節點(n〇de)上 積的方式覆蓋一第二導電層,然後在此第二導電層上 々以第一光阻層,而此第二光阻層係藉由定義與蝕刻的 二、來形成一儲存節點,而此儲存節點係用來當成電容器 ^、、頂端電極。接著在第二導電層的側壁上覆蓋形成一半 、狀的矽晶粒(hemiSpherical siHc〇n grain ;HSG), 此半球狀的矽晶粒係以快速熱氮化(rapid七“—。 r^tr^tion ; RTN )程序來處理。在快速熱氮化(RTN )程 、之後’接著在半球狀的矽晶粒與第一介電層之上,覆蓋 並/儿積一共形第二介電層。最後,在底材上形成一毯覆式Cheng or: ΐ Γ 2) and so on. The co-saponifiable nitride can be improved by rapid thermal nitriding of the latent hydrazine deposited on the nitride. Therefore, the way to slow down the oxidation is difficult, and ±, / + are more tight, so it can effectively touch the RC of the node. This method can also greatly improve the production process. The purpose of the 7-step process is to provide a substrate with a surface photo-transistor. Material υ ;, for: used to form an electrical layer. Then, a photoresist layer is formed on the first-layer: dielectric layer, and the first-layer layer is a contact channel (contact openi called by definition and etching). ). Next, a first conductive layer is formed and filled with contacts tf * Ϊ __ In order to form a contact node, an etching process is performed to remove the f-v electrical layer. Therefore, a second conductive layer is overlaid on the first dielectric layer and the contact node (node), and then a first photoresist layer is formed on the second conductive layer, and the second photoresist layer is borrowed. A storage node is formed by the two defined and etched, and this storage node is used as a capacitor ^ and a top electrode. Then, a half-shaped silicon grain (hemiSpherical siHon grain; HSG) is formed on the sidewall of the second conductive layer, and the hemispherical silicon grain is rapidly thermally nitrided (rapid seven "-" r ^ tr ^ tion; RTN) program. After the rapid thermal nitridation (RTN) process, and then on the hemispherical silicon grains and the first dielectric layer, a conformal second dielectric layer is covered and / or deposited. . Finally, a blanket covering is formed on the substrate
五、發明說明------ 第三導電舞 胃價^於用來當成電容器的頂端電極 5 - 4發明的% ]评細說明: 本發明的一 4^ 些詳細描述之一較佳實施例會詳細描述如下.,然而除了這 例中,且發明還可以廣泛地施行在其他的實施 準。 ^明的範圍不受限定,其以之後的專利範圍為 來考楚V. Description of the invention ------ The third conductive dance price is 5% of the invention used as the top electrode of the capacitor 5-4] Detailed description: One of the detailed descriptions of the present invention is a preferred implementation The regular meeting is described in detail below. However, in addition to this example, the invention can be widely implemented in other implementation standards. ^ The scope of Ming is not limited, it is based on the scope of patents
繪的是本:匕第2圖所示’ 1中的橫切面示意'圖所* 續製程中佳實施例的流程。這些圖僅顯示在$ Τ的數個關鍵性步驟。 一入第一圖,一矽底材100加上一元件,於其上形成 =]氧化半導體(metal—〇xide semic〇nduct〇r ;M〇s) 電,體。然後於矽底材丨00之上形成一多數的場氧化物ι〇2 二場氧化物之一藉金屬氧化半導體之結構與另一場氧化物 分隔開。一閘極106,一閘氧化層104與一可交換之源極\ 汲極(source\drain)區域1〇8於半導體底材100之上一起 用來形成一金屬氧化半導體電晶體。於底材J 〇 〇之中形成 一淺溝槽隔離(shallow trench isolation)結構 1〇2 以 隔離金屬氧化半導體電晶體。藉由化學氣相層積法( chemical vapor deposition ; CVD )於石夕底材 l〇〇 之上覆What is drawn is: The cross section in '1 shown in Fig. 2 shows the flow chart of the preferred embodiment in the continuation process. These figures show only a few key steps at $ Τ. As shown in the first figure, a silicon substrate 100 plus a component is formed thereon.]] Oxide semiconductors (metal-oxide semiconductors; Mos). Then a large number of field oxides are formed on the silicon substrate. One of the two field oxides is separated from the other field oxide by the structure of the metal oxide semiconductor. A gate electrode 106, a gate oxide layer 104 and an exchangeable source / drain region 108 are formed on the semiconductor substrate 100 to form a metal oxide semiconductor transistor. A shallow trench isolation structure 10 is formed in the substrate J 〇 〇 to isolate the metal oxide semiconductor transistor. A chemical vapor deposition (CVD) method was applied over the Shixi substrate 100.
第10頁 523909 五、發明說明(7) 蓋形成一批覆式内層多晶介電層(lpi)) n〇。此外,一未 顯不於圖中之光阻層覆蓋形成於批覆式内層多晶介電層 (I^D ) 1 1 〇之上,其中光阻層係藉由非等向性蝕刻的方式 來定義與姓刻並形成接觸通道丨丨2。然後在内層多晶介電 層(IPD) 110之中形成一接觸填充物(c〇ntact piUg) 112以使其與可父換之源極\汲極(s o u r c e .\ d r a i η )區域 108具有一電性連結。更進一步地,一金屬導電層(metai conductive layer)112a層積覆蓋於内層多晶介電層( IPD) 110之上並填滿接觸通道112,接著進行一蝕刻程序 以移除金屬導電層,並藉由回蝕刻的方式形成一接觸節 點此接觸節點可用來當成一電容器的底端電極。此金屬 導電層112a至少包含有下列物質之一 ··鋁(Aluminum ; Αι )銅(Copper ;Cu)、鶴(Tungsten ;W)。隨後使用 標準的低壓化學氣相層積法(1〇w pressure chemical vapor deposition ;LPCVD)的技術將第一摻質多晶矽層 114層積並覆蓋於内層多晶介電層(IpD ) 11〇與接觸節^ 11 2 a之上。 … 參考第二圖,一未顯示於圖中之第二光阻層形成於 一摻質多晶矽層11 4之上,且將主要的第一摻質多晶矽屑 1^4蝕刻後,剩餘之第一摻質多晶矽層η“可形成一儲^ 節點,此儲存節點用來當成電容器的頂端電極,如圖三予 不。摻質多晶矽層11 4a係由矽所組成。更進一步地, 一多數的成核作用散佈在摻質多晶矽層U4a之内,並在摻 523909Page 10 523909 V. Description of the invention (7) The cover forms a batch of inner polycrystalline dielectric layer (lpi)) n0. In addition, a photoresist layer not shown in the figure is formed overlying the inner polycrystalline dielectric layer (I ^ D) 1 1 0, wherein the photoresist layer is formed by anisotropic etching. Define and form a contact channel with the surname 丨 丨 2. Then, a contact filling material (conntact piUg) 112 is formed in the inner polycrystalline dielectric layer (IPD) 110 so that the contact filling source (source. \ Drai n) region 108 has a Electrical connection. Further, a metal conductive layer 112a is laminated on the inner polycrystalline dielectric layer (IPD) 110 and fills the contact channel 112. Then, an etching process is performed to remove the metal conductive layer, and A contact node is formed by etch-back. This contact node can be used as the bottom electrode of a capacitor. This metal conductive layer 112a contains at least one of the following: Aluminum (Aluminum) Copper (Cu), Tungsten (W). Subsequently, a first low-pressure chemical vapor deposition (LPCVD) technique was used to laminate the first doped polycrystalline silicon layer 114 and cover the inner polycrystalline dielectric layer (IpD) 11 with contact. Section ^ 11 2 a above. … Referring to the second figure, a second photoresist layer not shown in the figure is formed on a doped polycrystalline silicon layer 11 4, and the main first doped polycrystalline silicon chip 1 ^ 4 is etched, and the remaining first The doped polycrystalline silicon layer η "can form a storage node. This storage node is used as the top electrode of the capacitor, as shown in Figure 3. The doped polycrystalline silicon layer 11 4a is composed of silicon. Furthermore, a majority of Nucleation is dispersed in the doped polycrystalline silicon layer U4a, and the doped 523909
質多晶石夕層114a的邊牆上覆蓋形成一半球狀的矽晶粒( 。/、次,可藉由快速熱氮化過程(RTN )來處理半球 的矽晶粒(HSG ),此方式可取代在爐管中所進行之傳 =的均熱(soaking)製程。此外,在快速熱氮化過程(The semi-spherical silicon grains are formed on the side wall of the high-quality polycrystalline stone layer 114a (// times, and the hemisphere silicon grains (HSG) can be processed by a rapid thermal nitridation process (RTN)). Can replace the soaking process in the furnace tube. In addition, in the rapid thermal nitridation process (
)之後可層積一共形氮矽化物層116a覆蓋於該半球狀 的矽晶粒(HSG ) 115與内層多晶介電層(IPD ) 11〇的頂端 表面之上。該半球狀的矽晶粒(HSG ) i丨5之中的共形氮矽 化物層116a之厚度約為60埃,而且内層多晶介電層(IpD )11 0的頂端表面之上的共形氮石夕化物層11 6 a所形成之厚 度約有4 0至6 0埃。在傳統的方法中,該半球狀的矽晶粒( HSG ) 115之中的共形氮矽化物層丨丨6a之厚度約為6〇埃,但 是内層多晶介電層(IPD ) 110的頂端表面之上的共形氮矽 化物層116a所形成之厚度卻僅有約20至30埃。由於快速熱 氮化(RTN )能進行有效的氮化作用,所以在半球狀的石夕 晶粒(HSG ) 11 5之上的氮矽化物層11 6a與内層多晶介電層 (IP D ) 11 0之上的氮石夕化物層11 6 b兩者之間皆已經被有效 地改善。在快速熱氮化(RTN )之後與共形氮矽化物層形 成之前,本發明的方法更包含一均熱(soak i ng )製程。 此均熱(soaking )製程至少包含氨(ammonia ; NH3 )與 氮氣(nitrogen ; N2 ),且在溫度約為60 0 °C至850 °C之間 的氨(NH3 )與氮氣(N2 )的比例約為30至50。在爐管中僅 以氣(NH3 )進行均熱(soaking )製程並不能有效地在内 層多晶介電層(I PD )之中形成氮矽化物,且導致半球狀 的矽晶粒(HSG ) 115與内層多晶介電層(IPD ) 110之間的) After that, a conformal nitrogen silicide layer 116a can be laminated on the top surfaces of the hemispherical silicon grains (HSG) 115 and the inner polycrystalline dielectric layer (IPD) 110. The thickness of the conformal nitrogen silicide layer 116a in the hemispherical silicon grains (HSG) i5 is about 60 angstroms, and the conformal shape is above the top surface of the inner polycrystalline dielectric layer (IpD) 110. The nitrided oxide layer 11 6 a has a thickness of about 40 to 60 angstroms. In the conventional method, the thickness of the conformal nitrogen silicide layer in the hemispherical silicon grains (HSG) 115 is about 60 angstroms, but the top of the inner polycrystalline dielectric layer (IPD) 110 The thickness of the conformal nitrogen silicide layer 116a on the surface is only about 20 to 30 angstroms. Because rapid thermal nitridation (RTN) can perform effective nitriding, the nitrogen silicide layer 11 6a and the inner polycrystalline dielectric layer (IP D) on the hemispherical lithography grain (HSG) 11 5 The azolite layer 11 6 b above 110 has been effectively improved between the two. After the rapid thermal nitridation (RTN) and the formation of the conformal nitrogen silicide layer, the method of the present invention further includes a soak process. This soaking process includes at least ammonia (NH3) and nitrogen (nitrogen; N2), and the ratio of ammonia (NH3) to nitrogen (N2) at a temperature between about 60 ° C and 850 ° C. About 30 to 50. The soaking process using only gas (NH3) in the furnace tube cannot effectively form nitrogen silicide in the inner polycrystalline dielectric layer (I PD), and results in hemispherical silicon grains (HSG). Between 115 and the inner polycrystalline dielectric layer (IPD) 110
第12頁 523909 五、發明說明(9)Page 12 523909 V. Description of the invention (9)
金屬表面的氮化作用不同,且形成的氮化物之共形程度相 當的薄弱。最後,形成一毯覆式摻質多晶矽層丨丨8覆蓋於 石夕底材1 0 0之上用以當成一電容器的頂端電極。本發明之 改良共形私度的另一^實施例係在形成一半球狀的碎晶粒( HSG) 115之後,以氨(關3)與氮氣(N2)的電漿(plasma )或是遠程電漿(remote plasma)的方式來處理半球狀 的矽晶粒(HSG ) 11 5。對減少此種共形物所引起啟的問題 而言,本發明係為一最有效的氮化作用之方法。由於在形 ,一半球狀的矽晶粒(HSG ) 11 5之後,以氨(Nu3 )與氮 氣(N2)的電漿(piasma)或是遠程電漿The metal surface has different nitriding effects, and the nitride formed is relatively weak in conformity. Finally, a blanket-type doped polycrystalline silicon layer is formed over the Shixi substrate 100 to serve as a top electrode of a capacitor. Another embodiment of the improved conformal privacy of the present invention is that after forming hemispherical broken grains (HSG) 115, plasma using ammonia (Off 3) and nitrogen (N2) or remotely Plasma (remote plasma) is used to process hemispherical silicon grains (HSG) 11 5. The present invention is one of the most effective nitriding methods for reducing the problems caused by such conformals. After the shape of the semi-spherical silicon grains (HSG) 11 5, the plasma (piasma) of ammonia (Nu3) and nitrogen (N2) or remote plasma
plasma )的方式來處理半球狀的矽晶粒(HSG ) 115,半球 狀,矽晶粒(HSG) 115與内層多晶介電層(IpD) 11〇之上 、勺,化物=厚度皆相似。所以能夠有效地減緩氧化作用的 途徑,且藉由此方法也能大大地改善接觸節點的Rc。 顯然地,依照 多的修正與差異。 内加以理解,除了 地在其他的實施例 上面實施例中的描述 因此需要在其附加的 上述詳細的描述外, 中施行。 ,本發明可能有許 權利要求項之範圍 本發明還可以廣泛plasma) to treat hemispherical silicon grains (HSG) 115, hemispherical, silicon grains (HSG) 115 and the inner polycrystalline dielectric layer (IpD) above 110 °, and the thickness of the compound is similar. Therefore, it can effectively slow down the oxidation pathway, and by this method, the Rc of the contact node can be greatly improved. Obviously, there are many amendments and differences. It should be understood that, in addition to the descriptions in the other embodiments, the above embodiments need to be implemented in addition to the above detailed descriptions. The invention may have the scope of the claims, and the invention may also be broad
以限定本 示之精神 5月專利範 上述僅為本發明之較佳實施例而已,並 發明之申請專利範圍;凡其它未脫離本發明 下所完成的等效改變或修飾,均應包含在下由 圍内。 τIn order to limit the spirit of the present May patent, the above is only a preferred embodiment of the present invention, and the scope of the patent application for the invention; all other equivalent changes or modifications that do not depart from the present invention should be included in the following Within. τ
為了能讓本發明上 明顯易懂,下文特舉二之其他目的、特徵、和優點能更 砰細說明如下: 灵知例,並配合所附圖式,作 第一圖至第 造步驟之橫切面 ,圖為根據本發 示意圖。 明之 實施例之不同的製 主要部分之代表符號·· 100 102 104 106 半導體之矽底材。 場氧化物所形成、夕、咬 閘氧化層。 故溝槽隔離區域 間極。 108可交換之源極\汲極區域。 110 内層多晶介電層。 112 接觸通道。 112a 金屬導電層。 114 第一摻質多晶矽層。 114a第一摻質多晶石夕層所剩餘之摻質多晶矽層。 115 半球狀的石夕晶粒。 116a 半球狀的石夕晶粒之上的氮石夕化物層。 116b内層多晶介電層之上的氮矽化物層。 118 毯覆式摻質多晶矽層。In order to make the present invention clearly understandable, the other objects, features, and advantages of the following special enumeration 2 can be explained in more detail as follows: In the example of knowledge, and in accordance with the accompanying drawings, the first step to the first step are made horizontally. In section, the figure is a schematic diagram according to the present invention. Mingzhi Different systems of the embodiment Representative symbols of the main parts 100 102 104 106 Silicon substrates for semiconductors. Field oxides are formed by oxide oxides. Therefore, the trench isolation region is polarized. 108 exchangeable source / drain regions. 110 inner polycrystalline dielectric layer. 112 Touch the channel. 112a Metal conductive layer. 114 A first doped polycrystalline silicon layer. 114a remaining doped polycrystalline silicon layer. 115 Hemispherical Shi Xi grains. 116a Nitrogen oxide layer above hemispherical stone crystalline grains. A nitride silicide layer over the 116b inner polycrystalline dielectric layer. 118 blanket doped polycrystalline silicon layer.
第14頁Page 14
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