TW523909B - Improvement of super thin conformal nitride for dynamic random access memory capacitor - Google Patents

Abstract

A kind of method that uses surface light sensitivity improvement to form excellent conformity is disclosed in the present invention. A substrate for forming transistors is provided. The blanket-covered type first dielectric layer is deposited on the substrate. The first photoresist (PR) layer is formed on the first dielectric layer. A contact opening is formed by defining and etching the first PR layer. The first conducting layer is formed to fill up the contact opening. An etching step is conducted to remove the first conducting layer for forming a contact node. By using a deposition manner, the second conducting layer is formed to cover the first dielectric layer and the contact node. The second PR layer, which is defined and etched to form a storage node that is used as the upper electrode of the capacitor, is formed on the second conducting layer. After that, a hemispherical silicon grain (HSG) is formed to cover the sidewall of the second conducting layer, in which the hemispherical silicon grain is treated by a rapid thermal nitration (RTN) procedure. After the RTN procedure, the conformal second dielectric layer is deposited to cover the HSG and the first dielectric layer. Finally, a blanket-type third conducting layer is formed on the substrate for use as the upper electrode of the capacitor.

Description

523909

V. Description of the Invention (i) 5-1 Field of the Invention The present invention relates to a method for forming an excellent conformity by improving the surface sensitivity. 5-2 Background of the Invention: Recently "due to the widespread use of electronic equipment, the demand for dynamic random access memory (DRAM) has rapidly increased", especially in the information industry regarding computer hardware methods " " noodle application. In addition to applications in the information industry, dynamic random access memory must also be frequently used in large-scale integration (LSI), very large-scale integration (VLSI), and ultra-large-scale integration circuits (VLSI). Ultra-large-scale integration (ULSI). In the next century, the manufacturing technology of 'Dynamic Random Access Memory' will still play a major role. As electronics, information, and communications products tend to be thin, light, short, and rapidly developed, demand for high-density and large-capacity dynamic random-access memory has increased dramatically. A high-cell (ce 1 1) density memory element naturally has a higher memory capacity 'and relatively lower manufacturing costs. In order to increase the memory capacity in the dynamic random access memory device, it is usually taken to increase

523909

Strategies for memory cell density. High component density is generally implemented by reducing the size of integrated circuits, such as line width, line pitch distance, transistor gate, or dual capacitors ( c〇Upied capacitor). A typical DRAM cell contains a field-effect transistor (FET) and a capacitor. This means that the capacitor is connected to the field-effect transistor. A dynamic random access memory element usually contains a large number of dynamic random access memory cells arranged in a configuration structure. Each DRAM cell is capable of storing a binary data via the state of charge of a capacitor ^. A charged capacitor stores & a binary data "1", and a discharged capacitor stores a binary " lean " 0 ' '. The dual field effect transistor can be charged or discharged through the application of the voltage state in its drain region. Bit line and word line can also be used to select the field effect transistor that meets the needs. The character line is connected to the gate of each field effect transistor arranged in the dynamic random access memory, and the bit line is connected to each field arranged in the dynamic random access memory. The infinite connection of the effect transistor. The bit line provides the voltage condition to the field effect transistor, while the word line is used to control the on / off of the field effect transistor. Through the selection of a pair of word lines and bit lines, a field-effect transistor that meets the requirements can be obtained and written into the double capacitor with = carry data. In order to obtain the state of charge of the dual capacitor ’, it is also possible to read the stored binary by selecting the field effect transistor and converting the bit line into a comparator circuit.

523909 V. Description of the invention (X > data. I have thus obtained the binary data of the selected dynamic random access storage. &Quot; Capacitors already in the memory of the moon = the top and bottom electrodes, and this The top electrode and the bottom electrode are borrowed: The end electrode is connected: the source of the field effect transistor. The total amount of charge stored in the mouth depends on the capacitor ’s charge. The current capacity is inversely proportional to the electrode surface and the dielectric (Capacitance electrode surface) and the distance between the top electrode / bottom electrode ratio (such as the distance between the bottom electrode and the low electrode). Usually the size is reduced in order to reduce the size of the component And this method also reduces the surface of the electric pole. The amount of electricity is measured by the capacity. For example, the content of the data of the fruit level: Π f: placing and a leakage current will cause the storage binary. Small allowance for change in charge. The content of the recharge-segment dr lean material is wrong, the capacitor must have an electrical cycle time, too. E Right 疋 current capacity is small, then charge each charge: = 2 so more often need to be charged Program. During the period. During this period: the power capacity of the dynamic random access memory will have a dead tiffle, and a small current energy efficiency will also be combined with the installation of the system. Incremental amplifier, $ spleen. F The smaller current capacity requires a more sensitive delay to increase the complexity of the circuit and increase the manufacturing cost. 523909 V. Description of the invention (4) We find that the nitride layer is slightly different. High impedance 'this high impedance Neck) decreases the area of the polysilicon grains in the critical dimension of the point immediately, now a nitride deposited layer is thinned, the weight, it is likely that the interface to the oxidation. There is also some evidence that the surface (storage node; SN) and internal dielectric layer (IP D) during the deposition of the compound slow down due to various reasons mentioned above. The shrinkage caused in the capacitor's node is due to the oxidation at the storage neck (poly grain), this phenomenon will become more serious. We have also made its surface sensitivity and the problem more severe. The path through polycrystalline silicon / oxide can support the above assumptions, such as the sensitivity of nitrogen 'and the addition of a thin thin nitride layer between the polycrystalline dielectric layer (inter ~ poiy) of the storage node layer. We need a more New semiconductor element with good conformity of dynamic random access memory 5-3 Purpose and summary of the invention: Rarely in the above background of the invention 'The present invention provides a protective arm of a modified dynamic random access memory capacitor # WG 次It can be used as w ~ 溥 conformal nitride. The object of the present invention is to provide a process method for forming an excellent conformity. A kind of surface layer is formed on the hemispherical residual leather grains and the inner layer.

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Cheng or: ΐ Γ 2) and so on. The co-saponifiable nitride can be improved by rapid thermal nitriding of the latent hydrazine deposited on the nitride. Therefore, the way to slow down the oxidation is difficult, and ±, / + are more tight, so it can effectively touch the RC of the node. This method can also greatly improve the production process. The purpose of the 7-step process is to provide a substrate with a surface photo-transistor. Material υ ;, for: used to form an electrical layer. Then, a photoresist layer is formed on the first-layer: dielectric layer, and the first-layer layer is a contact channel (contact openi called by definition and etching). ). Next, a first conductive layer is formed and filled with contacts tf * Ϊ __ In order to form a contact node, an etching process is performed to remove the f-v electrical layer. Therefore, a second conductive layer is overlaid on the first dielectric layer and the contact node (node), and then a first photoresist layer is formed on the second conductive layer, and the second photoresist layer is borrowed. A storage node is formed by the two defined and etched, and this storage node is used as a capacitor ^ and a top electrode. Then, a half-shaped silicon grain (hemiSpherical siHon grain; HSG) is formed on the sidewall of the second conductive layer, and the hemispherical silicon grain is rapidly thermally nitrided (rapid seven "-" r ^ tr ^ tion; RTN) program. After the rapid thermal nitridation (RTN) process, and then on the hemispherical silicon grains and the first dielectric layer, a conformal second dielectric layer is covered and / or deposited. . Finally, a blanket covering is formed on the substrate

V. Description of the invention ------ The third conductive dance price is 5% of the invention used as the top electrode of the capacitor 5-4] Detailed description: One of the detailed descriptions of the present invention is a preferred implementation The regular meeting is described in detail below. However, in addition to this example, the invention can be widely implemented in other implementation standards. ^ The scope of Ming is not limited, it is based on the scope of patents

What is drawn is: The cross section in '1 shown in Fig. 2 shows the flow chart of the preferred embodiment in the continuation process. These figures show only a few key steps at $ Τ. As shown in the first figure, a silicon substrate 100 plus a component is formed thereon.]] Oxide semiconductors (metal-oxide semiconductors; Mos). Then a large number of field oxides are formed on the silicon substrate. One of the two field oxides is separated from the other field oxide by the structure of the metal oxide semiconductor. A gate electrode 106, a gate oxide layer 104 and an exchangeable source / drain region 108 are formed on the semiconductor substrate 100 to form a metal oxide semiconductor transistor. A shallow trench isolation structure 10 is formed in the substrate J 〇 〇 to isolate the metal oxide semiconductor transistor. A chemical vapor deposition (CVD) method was applied over the Shixi substrate 100.

Page 10 523909 V. Description of the invention (7) The cover forms a batch of inner polycrystalline dielectric layer (lpi)) n0. In addition, a photoresist layer not shown in the figure is formed overlying the inner polycrystalline dielectric layer (I ^ D) 1 1 0, wherein the photoresist layer is formed by anisotropic etching. Define and form a contact channel with the surname 丨 丨 2. Then, a contact filling material (conntact piUg) 112 is formed in the inner polycrystalline dielectric layer (IPD) 110 so that the contact filling source (source. \ Drai n) region 108 has a Electrical connection. Further, a metal conductive layer 112a is laminated on the inner polycrystalline dielectric layer (IPD) 110 and fills the contact channel 112. Then, an etching process is performed to remove the metal conductive layer, and A contact node is formed by etch-back. This contact node can be used as the bottom electrode of a capacitor. This metal conductive layer 112a contains at least one of the following: Aluminum (Aluminum) Copper (Cu), Tungsten (W). Subsequently, a first low-pressure chemical vapor deposition (LPCVD) technique was used to laminate the first doped polycrystalline silicon layer 114 and cover the inner polycrystalline dielectric layer (IpD) 11 with contact. Section ^ 11 2 a above. … Referring to the second figure, a second photoresist layer not shown in the figure is formed on a doped polycrystalline silicon layer 11 4, and the main first doped polycrystalline silicon chip 1 ^ 4 is etched, and the remaining first The doped polycrystalline silicon layer η "can form a storage node. This storage node is used as the top electrode of the capacitor, as shown in Figure 3. The doped polycrystalline silicon layer 11 4a is composed of silicon. Furthermore, a majority of Nucleation is dispersed in the doped polycrystalline silicon layer U4a, and the doped 523909

The semi-spherical silicon grains are formed on the side wall of the high-quality polycrystalline stone layer 114a (// times, and the hemisphere silicon grains (HSG) can be processed by a rapid thermal nitridation process (RTN)). Can replace the soaking process in the furnace tube. In addition, in the rapid thermal nitridation process (

) After that, a conformal nitrogen silicide layer 116a can be laminated on the top surfaces of the hemispherical silicon grains (HSG) 115 and the inner polycrystalline dielectric layer (IPD) 110. The thickness of the conformal nitrogen silicide layer 116a in the hemispherical silicon grains (HSG) i5 is about 60 angstroms, and the conformal shape is above the top surface of the inner polycrystalline dielectric layer (IpD) 110. The nitrided oxide layer 11 6 a has a thickness of about 40 to 60 angstroms. In the conventional method, the thickness of the conformal nitrogen silicide layer in the hemispherical silicon grains (HSG) 115 is about 60 angstroms, but the top of the inner polycrystalline dielectric layer (IPD) 110 The thickness of the conformal nitrogen silicide layer 116a on the surface is only about 20 to 30 angstroms. Because rapid thermal nitridation (RTN) can perform effective nitriding, the nitrogen silicide layer 11 6a and the inner polycrystalline dielectric layer (IP D) on the hemispherical lithography grain (HSG) 11 5 The azolite layer 11 6 b above 110 has been effectively improved between the two. After the rapid thermal nitridation (RTN) and the formation of the conformal nitrogen silicide layer, the method of the present invention further includes a soak process. This soaking process includes at least ammonia (NH3) and nitrogen (nitrogen; N2), and the ratio of ammonia (NH3) to nitrogen (N2) at a temperature between about 60 ° C and 850 ° C. About 30 to 50. The soaking process using only gas (NH3) in the furnace tube cannot effectively form nitrogen silicide in the inner polycrystalline dielectric layer (I PD), and results in hemispherical silicon grains (HSG). Between 115 and the inner polycrystalline dielectric layer (IPD) 110

Page 12 523909 V. Description of the invention (9)

The metal surface has different nitriding effects, and the nitride formed is relatively weak in conformity. Finally, a blanket-type doped polycrystalline silicon layer is formed over the Shixi substrate 100 to serve as a top electrode of a capacitor. Another embodiment of the improved conformal privacy of the present invention is that after forming hemispherical broken grains (HSG) 115, plasma using ammonia (Off 3) and nitrogen (N2) or remotely Plasma (remote plasma) is used to process hemispherical silicon grains (HSG) 11 5. The present invention is one of the most effective nitriding methods for reducing the problems caused by such conformals. After the shape of the semi-spherical silicon grains (HSG) 11 5, the plasma (piasma) of ammonia (Nu3) and nitrogen (N2) or remote plasma

plasma) to treat hemispherical silicon grains (HSG) 115, hemispherical, silicon grains (HSG) 115 and the inner polycrystalline dielectric layer (IpD) above 110 °, and the thickness of the compound is similar. Therefore, it can effectively slow down the oxidation pathway, and by this method, the Rc of the contact node can be greatly improved. Obviously, there are many amendments and differences. It should be understood that, in addition to the descriptions in the other embodiments, the above embodiments need to be implemented in addition to the above detailed descriptions. The invention may have the scope of the claims, and the invention may also be broad

In order to limit the spirit of the present May patent, the above is only a preferred embodiment of the present invention, and the scope of the patent application for the invention; all other equivalent changes or modifications that do not depart from the present invention should be included in the following Within. τ

In order to make the present invention clearly understandable, the other objects, features, and advantages of the following special enumeration 2 can be explained in more detail as follows: In the example of knowledge, and in accordance with the accompanying drawings, the first step to the first step are made horizontally. In section, the figure is a schematic diagram according to the present invention. Mingzhi Different systems of the embodiment Representative symbols of the main parts 100 102 104 106 Silicon substrates for semiconductors. Field oxides are formed by oxide oxides. Therefore, the trench isolation region is polarized. 108 exchangeable source / drain regions. 110 inner polycrystalline dielectric layer. 112 Touch the channel. 112a Metal conductive layer. 114 A first doped polycrystalline silicon layer. 114a remaining doped polycrystalline silicon layer. 115 Hemispherical Shi Xi grains. 116a Nitrogen oxide layer above hemispherical stone crystalline grains. A nitride silicide layer over the 116b inner polycrystalline dielectric layer. 118 blanket doped polycrystalline silicon layer.

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Claims (1)

523909 _Case No. 891080% _Year Month Day ~ 一 " '---_ Amendment 6. The scope of patent application ___ soaking) process is performed before the formation of rapid thermal nitridation (RTn) nitrogen silicide layer.彳 人形 形 second 3 · The dynamic random storage manufacturing method described in item 2 of the scope of the patent application, wherein the above-mentioned soak process (soak in ng) is as small as ％, body cell 〇3) and nitrogen (team) And the temperature of this process is about 600 ℃ inclusive ammonia. 4 to 850 ° C · The dynamic random access manufacturing method described in the first item of the patent application scope, wherein the first dielectric The layer includes at least the inner layer, called the layer of cells (IPD). 9 Diri dielectrics 5. The dynamic random access memory manufacturing method described in item 4 of the patent application scope, wherein the inner polycrystalline dielectric layer (IPD) ) To JII, silicon oxide (Si02). Already — 6 · The method for manufacturing a dynamic random access memory as described in item 1 of the scope of patent application, wherein the above-mentioned second dielectric layer includes at least Nitrogen silicon ^ 7 ^ The method for manufacturing a dynamic random access memory cell as described in item 1 of the scope of the patent application, wherein the above-mentioned contact node contains at least one of the following materials: aluminum (Alumiruim; Α1), copper ( C〇pper; Cu) and tungsten (Tungsten; W) ° Page 16 523909 _Case No. 89108096_Year Month Date__ VI. Application for Patent Scope 8. The manufacturing method of the dynamic random access memory cell as described in Item 1 of the patent application scope, wherein the above storage node contains at least Doped polycrystalline silicon. 9. The method for manufacturing a dynamic random access memory cell as described in item 1 of the scope of the patent application, wherein the third conductive layer includes at least doped polycrystalline silicon. 1 ◦ The method for manufacturing a dynamic random access memory cell as described in item 1 of the scope of the patent application, wherein the first conductive layer, the second conductive layer, and the third conductive layer are formed by chemical vapor deposition ( CVD). _ 1 1. The method for manufacturing a dynamic random access memory cell as described in item 1 of the scope of patent application, wherein at least one of the steps of patterning the first dielectric layer (pa 11 erning) in order to form the contact channel is at least Contains anisotropic epiphany mode. 1 2. The method for manufacturing a dynamic random access memory cell as described in item 1 of the scope of patent application, wherein the step of forming the hemispherical silicon grain (HSG) includes at least Shi Xi. I 13. A method for manufacturing a dynamic random access memory cell, comprising at least the following steps: providing a substrate; laminating a blanket-type first dielectric layer on the substrate; forming a first photoresist layer on the substrate; The blanket over the first dielectric layer, wherein the ' Page 17 523909 ----- 89⑽dqr__Year Month, Day 6 、 Scope of patent application " " '----- — The first photoresist layer is formed by means of definition and etching — forming a first The conductive layer fills the contact channel and touches the channel; the procedure is to remove the first conductive layer to form a contact node; perform an etching " consolidate a second conductive layer on the first dielectric layer and kiss; A second photoresist layer is formed on the contact node on the second conductive layer, and the resist layer is formed by defining and etching. The second optical storage node is used as a top electrode of a capacitor. P anvil, and this reservoir forms a semi-spherical silicon crystal grain (HSG) on the second;-the side wall of the V electrical layer, the hemispherical silicon crystal grain (HSG) is treated with a plasma (丨 treatment; Plasma ) Process comes after the plasma (p 1 asma) process, > W, Dan-shaped eighth "on the hemispherical silicon grain (HSG) and the first dielectric layer on top of one electrical layer A blanket-type third conductive layer is formed on the substrate, and a top electrode of the capacitor. Recalling the soaking of the body cell (second nitrogen silicide 14. The manufacturing method of dynamic random storage as described in item 13 of the scope of patent application, further including a soaking process, the soaking process is performed in the plasma (piaSma) It is then performed before the formation of the conformal layer. 15. The manufacturing method of the dynamic random access memory described in item 13 of the scope of patent application, wherein the above soaking process = somatic cell contains ammonia Page 18, Shen Jing's patent scope (NH, case number 8910), and nitrogen (n2), and the temperature of this system is about 60 ° C to 85 (rc 16 The dynamic random access memory cell fabrication method according to item 13, wherein the first dielectric layer includes at least an inner layer of multiple electrical layers (IPD). 1 ·· The dynamics as described in item 13 of the scope of patent application Random access memory cell I. Manufacturing method, wherein the above-mentioned inner polycrystalline dielectric layer (IPD) is at least human-silicon dioxide (Si02) 0 3 1 8 · As described in item 13 of the scope of patent application A method for manufacturing a dynamic random access memory, wherein the second dielectric layer includes at least a nitrogen silicide ^ 19. The dynamic random access memory cell described in item 3 of the patent application scope The method, wherein the above-mentioned contact egg point contains at least one of the following substances: aluminum (Aluminum; A1), copper (COPPPer; Cu), and tungsten (Tungsten 20. The dynamic random storage according to item 13 of the scope of patent application A method for manufacturing a memory cell, wherein the storage node described above includes at least doped silicon. 21 · Dynamic random access memory cell as described in item 13 of the scope of patent application Page 19 The manufacturing method, wherein the aforementioned third conductive layer includes at least doped polycrystalline silicon 22. The dynamic random storage, the manufacturing method, as described in item 丨 3 of the patent application scope, the first / conductive layer and the second conductive layer described above; The cell layer is formed by chemical vapor deposition (CVD). -23. The method for manufacturing a dynamic random access memory cell as described in item 13 of the scope of patent application, wherein the step of patterning the electrical layer in order to form the contact channel includes at least # 等 向Sexual etching. 2 4. The method for manufacturing a dynamic random access memory cell as described in item 13 of the scope of the patent application, wherein the step of forming the hemispherical silicon grain (HSG) includes at least Shi Xi. 2 5. The method for manufacturing a dynamic random access memory cell as described in item 13 of the scope of the patent application, wherein the plasma process described above further includes a remote plasma process. 26. A method for manufacturing a dynamic random access memory cell, comprising at least the following steps: providing a silicon substrate on which a transistor is formed; and laminating a blanket-type first dielectric layer on the substrate; Forming a first photoresist layer on the blanket-type first dielectric layer, wherein the Page 20 y23909 _ Case No. 89108096 VI. Scope of patent application ___ The first photoresist layer is formed by definition and etching-a metal conductive layer and fills the contact channel, = contact channel; private sequence: remove the metal A conductive layer is formed to form a contact node, a point; a first doped polycrystalline silicon layer is deposited on the p-point, and a second photoresist is formed on the contact layer and the contact layer. The layer in the first doped second photoresist layer is defined by the square dagger; ^ in this and this storage node is used as one of a capacitor: end; the side of the staggered storage point == Spherical Hexagonal Grains (HSG) are formed in the first polycrystalline stone, and hemispherical silicon grains (HSG) are processed by rapid thermal nitridation; κ 1 w) After the nitriding (RTN) process, a conformal cylinder layer is deposited on the hemispherical silicon grains (HSG) and the first dielectric layer, and a blanket second doped polycrystalline silicon layer is formed. On the silicon substrate ', and ^ are used as a top electrode of the capacitor. 27. The method for manufacturing a dynamic random access memory cell as described in item 26 of the scope of the patent application, further comprising a soaking process, which is based on rapid thermal nitriding RTN) is performed before formation of the conformal second dielectric layer. 1 28. The method for manufacturing a dynamic random access memory cell as described in item 26 of the scope of patent application, wherein the above soaking process includes at least ammonia and nitrogen, and 523909 _____ Case No. 89108096 _ ^^^ ----- 1 | ^ __ 6. Scope of patent application The temperature of this process is about 6 0 0 ΐ: to 8 5 0 ° C. 29. The method for manufacturing a dynamic random access memory cell according to item 26 of the scope of the patent application, wherein the above-mentioned inner polycrystalline dielectric layer (IPD) includes at least silicon dioxide (Si02). 30. The method for manufacturing a dynamic random access memory cell as described in item 26 of the scope of the patent application, wherein the above contact nodes include at least one of the following: aluminum (Aluminum; A1), copper (Copper; Cu) And tungsten (Tu ten; W). The method for manufacturing a dynamic random access memory cell as described in item 26 of the scope of the patent application, wherein the contact channel is formed to form the inner layer, the crystal interlayer, and the layer (IPD). ) The patterning step includes at least a non-climatic etching method. / Dagger 3 non 4 33 · A dynamic random access sequence steps: The manufacturing method of the memory cell includes at least the following on the Shi Xi substrate The first photoresist layer is formed on the blanket-type inner polycrystalline dielectric layer (IPD contact). The first photoresist layer is formed by definition and engraving to form a process for moving In addition to depositing a node; a metal conductive layer fills the contact channel, and an etching is performed on the metal conductive layer to form a contact node; a first doped polycrystalline silicon layer is formed on the first polycrystalline silicon layer and the The contact formation of the Chu I / ... Di Er photoresist layer on the first doped polycrystalline silicon layer, where the Le-Photo P and JSr 乂 么 # A and the $ system is a storage node formed by the way of definition and money engraving, The storage point is used as a top electrode of a capacitor; ^ forming a semi-spherical silicon grain (HSG) on the side wall of the first doped polycrystalline silicon layer; the side hemispherical silicon grain (HSG) is Plasma process is used for processing. After the plasma (p 1 asma) process, a plutonium conformal azolite layer is deposited on the far hemispherical silicon grains (HSG) and the inner polycrystalline dielectric layer. ; And forming a blanket second doped polycrystalline silicon layer on the silicon substrate; It is used as a top electrode of the capacitor. 34. The manufacturing method of the dynamic random access memory cell as described in item 33 of the patent application scope further includes a soaking process, which is soaking The process is performed after the plasma (piaSma) and before the formation of the conformal nitrogen silicide layer. Page 23 523909 Case No. 89108096 Modified on June 6, Patent Application Scope 35. The method for manufacturing a dynamic random access memory cell as described in Item 34 of the Patent Application Scope, wherein the above-mentioned soaking process is at least It contains ammonia (NH3) and nitrogen (N2), and the temperature of this cake is about 600. 0 to 85 (TC. 36. The method for manufacturing a dynamic random access memory cell as described in item 33 of the scope of the patent application, wherein the above-mentioned inner polycrystalline dielectric layer (IPD) includes at least S i 02). 37. The method for manufacturing a dynamic random access memory cell as described in item 33 of the scope of the patent application, wherein the above-mentioned gold-gold conductive layer includes at least one of the following: aluminum (Aluminum; A1), copper (Copper 'Cu) and tungsten (Tungsten; W) ° 38. The method for manufacturing a dynamic random access memory cell as described in item 33 of the patent application scope, wherein the above-mentioned metal conductive layer, the first The doped polycrystalline polycrystalline layer and the polycrystalline polycrystalline polycrystalline layer are formed by chemical vapor deposition (CVD) method. 39. The dynamic random access memory cell described in item 33 of the scope of patent application The manufacturing method, wherein the step of forming the contact channel and patterning the inner polycrystalline dielectric layer (IPD) includes at least an anisotropic etching method. 523909 _Case No. 89108096_ Year Month Date__ VI. Patent Application Range 40. The method for manufacturing a dynamic random access memory cell as described in Item 33 of the patent application range, wherein the aforementioned hemispherical silicon crystal grains The (HSG) formation step includes at least silicon. 41. The method for manufacturing a dynamic random access memory cell as described in Item 33 of the scope of the patent application, wherein the above plasma process (plasma) includes at least ammonia (NH3) and nitrogen (N2). 42. The method for manufacturing a dynamic random access memory cell as described in item 33 of the scope of the patent application, wherein the above-mentioned pi asma process further includes a remote plasma process. Page 25