TW427003B - Manufacturing method of crown type DRAM capacitor - Google Patents

Abstract

A manufacturing method of crown type DRAM capacitor is introduced. This method adds a silicon oxide spacer formed by thermal oxidation process on the sidewall of the second contact in the second insulated layer. Because the insulation of the silicon oxide formed by the thermal oxidation method is superior than the silicon oxide formed by conventional CVD process, the electrical isolation between capacitors is effectively raised and the capacitor leakage decreased. Then better data storage capability is reached.

Description

5. Description of the invention (1) The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a crown capacitor of a dynamic random access memory. Dynamic random access memory is a widely used integrated circuit component, especially in today's information electronics industry. As the technology evolves, 'most common DRAM memory cells on the production line are composed of a transistor T and a capacitor C' as shown in the circuit diagram in Figure 1. The source of the transistor T is connected to a corresponding bit line (BL) and the drain is connected to the bottom electrode of a capacitor c, and the gate is The top electrode connected to a corresponding word line (WL) 'capacitor C is connected to a fixed voltage source (eg, ground), and a dielectric layer is separated between the lower electrode and the upper electrode. Capacitor C is used to store electronic information. It should have a sufficiently large capacitance. In traditional DRAM processes with less than one million bits (1 MB), two-dimensional capacitors are often used to store data, which is also known as a planar-type capacitor. However, planar capacitors need to use a relatively large area of the substrate to form the lower electrode in order to provide a sufficient amount of capacitance ', so they are not suitable for the current process requirements for increasingly highly integrated DRAM devices. Generally, a 'highly integrated DRAM requires a three-dimensional space capacitor structure', such as a stack-type capacitor memory element. In the memory elements of various stacked capacitors, the 'electrode has a crown-type capacitor structure that protrudes upwards. Since its inner and outer surfaces can provide an effective capacitance area, it is quite suitable for manufacturing highly integrated elements.

Page 4 5. Description of the invention (2) Pieces', especially memory elements larger than 64 MB bits. Therefore, many technologies are modified for this form of crown capacitor to achieve the purpose of ensuring sufficient capacitance when the component size is reduced. For a clearer explanation, please refer to FIGS. 2A to 2C to describe a conventional manufacturing process of a crown capacitor of a dynamic random access memory cell. As shown in FIG. 2A, a field oxide layer 211 is formed on a semiconductor substrate 21o to define an active region. Then a gate structure Uate eiectrode) G is formed. The gate structure G is then used as a mask, and impurities are implanted into the semiconductor substrate 210 to form a lightly doped source / drain region. A spacer 212 is formed on the sidewall of the gate structure G by a deposition and etch-back process. Then the gate structure G and the spacer 2 1 2 are used as a mask, and a higher concentration of impurities is implanted into the semiconductor substrate 210. A source / drain region 214 with a lightly doped drain (LDD) design is formed, and thus a transistor device process is completed. Next, "deposit an insulating layer 216 overlying the surface of the transistor element" and then planarize the insulating layer 2 1 6 to form a flat surface which is favorable for subsequent processes. Then, a first contact opening 217 is formed in the insulating layer 216 by photolithography and a post-etching process, and the first contact opening 217 is communicated with a part of the source / inverter region 214. Then, a conductive plug 21 8 ′ is formed in the contact opening 217 to form an electrical connection with a part of the source / drain region 2 1 4. After that, a silicon oxide layer 220 is formed on the insulating layer 216 and the conductive plug 218. The silicon oxide layer 220 is mostly a silicon oxide layer formed by a chemical vapor deposition method. Then, referring to FIG. 2B, the silicon oxide layer 2 2 0 is defined as silicon oxide.

Second contact opening α 221 427 0 03 V. Description of the invention (3) The layer 220 ′ ′ is formed to communicate with the conductive plug 218. Next, referring to FIG. 2C, first form a lower electrode 222 on the second contact opening surface. . After that, a dielectric layer 226 and an upper electrode 228 are sequentially formed on the lower electrodes 222 and 220 to complete the capacitor structure. In the conventional corona capacitor structure mentioned above, usually only the silicon oxide layer 22 formed by the phase deposition method is used to provide electronic semiconductors between the capacitors. The fabrication of semiconductor devices is increasingly accumulated, and the oxide layer 22 ° is gradually thinner so that the electrons Easy to run f. Therefore, the use of only 20% of the oxidized stone oxide layer 22 0 is enough to provide electrical isolation between the capacitors; because of the marginal nature, it is known that there is leakage between the capacitors and the properties of the 7L parts are damaged. In view of this, the purpose of the present invention is to solve the above-mentioned problematic method of manufacturing a crown capacitor of a random access memory = manufacturing the above-mentioned capacitor method on the base of a semi-conductive vessel of the component to manufacture the following steps: a dynamic random access memory The method is suitable for a semiconductor substrate with a switching element. The manufacturing method includes the following steps: forming a conductive layer in the first contact opening to the first contact opening of the switching element in the half layer; A second insulating layer is formed on the conductive plug; an internal layer is formed to connect a second connection of the conductive plug, a silicon oxide layer in the opening 221 is formed on the L insulating layer and the second contact opening; It is known that the crown shape is used for chemical gas isolation, and the thickness is also provided by the vapor deposition method, which cannot provide the foot shape, so that the problem is provided. It is suitable for the first manufacture of the above-mentioned conductor substrate on a rectangular capacitor. Insulated in the first and second contact openings; in a polycrystalline silicon

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Page 6 zi / υ u __ Case No. 88〗 nQQiK V. Description of the invention (4) Layer: Thermal oxidation method, 丨 鲦 class \ ί > Turn the above-mentioned flip-chip into silicon oxide layer every s

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Ai, i-Λ, ,,, «---- ----, and also a hole 1ϋ π / w, return /, to form a silicon layer to a second insulating layer to form silicon oxide on the second contact opening 1 J A spacer; forming a bottom jade in the second contact opening, forming a dielectric layer on the lower electrode; and forming an upper electrode on the dielectric layer. It is preferable that the thickness of the above-mentioned polycrystalline silicon layer is between 200 and 500 angstroms, and the implementation temperature of the above It thermal oxidation method is between 8Q0 and. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, hereinafter, a preferred embodiment is described in detail with the accompanying drawings, and the detailed description is as follows: It is a schematic circuit diagram of a general dynamic random access memory unit; FIGS. 2A to 2C are cross-sectional schematic diagrams, which are used to explain the manufacturing process of a conventional capacitor for manufacturing a dynamic random access memory unit. 3A to 3H are schematic cross-sectional views for explaining a manufacturing process according to a preferred embodiment of the present invention. Symbol description 210 & 310 ~ semiconductor substrate; 211 & 31 field oxide layer; g & G '~ gate structure; 212 & 320 ~ gate spacer; 21 4 & 3 2 2 ~ source / drain region; 216 , 220, 324 & 328 ~ insulation layer; 218 & 326 ~ conductive plug; 332 ~ multicrystalline silicon layer; 334 ~ silicon oxide layer; 334 '~ silicon oxide spacer; 222' & 336 '~ lower electrode; 226 & 340 ~ dielectric layer; 228 & 342 ~ upper electrode. Example Manufacturing of a Crown Capacitor of the Dynamic Random Access Memory of the Present Invention

No. 7 I 2000. 08.21.007 4270 03 V. Description of the invention (5) The method can be implemented on a semiconductor element, for example, a metal oxide semiconductor field effect transistor (MOSFET) with an N-channel. However, the method for manufacturing the crown capacitor of the dynamic random access memory described in the present invention can also be applied to a MOSFET device with a P channel. First, “Please refer to FIG. 3A” to form a field oxide layer 311 on a semiconductor substrate 31 to define a device region. Next, a gate oxide layer 31 2, a gate electrode 31 4, a silicided metal layer 3 1 6 and a gate shielding layer 31 8 are sequentially formed on the substrate 31 ′ using lithography and anisotropy. The etching process defines a scheme for each of the above layers to form a gate structure G ′. The gate oxide layer 31 2 may be a silicon oxide layer, for example, formed by a high-temperature oxidation method in an environment where oxygen is present. The gate electrode 314 may be a conductively doped polycrystalline silicon layer. The metal layer 316 may be a tungsten silicide layer and the gate shielding layer 318. Generally, a silicon nitride layer is used. Next, a gate structure G 'is used as a mask, and ions are implanted on the substrate ′ on both sides to form a lightly doped region. Then, a spacer 320 is formed on the sidewall of the gate structure. The spacer 320 is formed by depositing and etching back an insulating layer. Generally, materials such as nitride or oxide can be selected. Next, the gate structure G and the gate spacer 320 are used as a mask, and more concentrated ions are implanted into the substrate 310 and deep and below the lightly doped region to complete the source / drain region 322 with the LDD design. Complete the process of a transistor element. Next, "deposit an insulating layer 3 2 4 overlying the surface of the transistor element" and then planarize the insulating layer 32 4 to form a flat surface which is favorable for subsequent processes. A lithography technique and an etching process are then used to form a first contact opening 325 in the insulating layer 3 2 4, which is connected to a portion of the source / drain regions 322. Pick up

427003 Faming Ming '~ ~ Deposit a conductive layer on the first insulating layer 324' and fill the first contact opening 325 ', and then remove the above conductive layer on the first insulating layer 324 by an etch-back procedure. The above-mentioned conductive layer in the first contact opening 325 forms a conductive plug 326 that communicates with a portion of the source / drain region 314. The conductive plug 326 may be conductively doped polycrystalline silicon or metal tungsten. After that, a second insulating layer 328 is formed on the insulating layer 324 and the conductive plug 326. The second insulating layer 328 is preferably made of silicon oxide formed by a chemical vapor deposition method. After that, referring to FIG. 3B, the second insulating layer 328 is defined by a lithography technique and an etching process to form a patterned second insulating layer 328, and a second contact opening 330 communicating with the conductive plug 326. Next, referring to FIG. 3C, a conductively doped thin polycrystalline silicon layer 332 is formed on the second insulating layer 328, and in the second contact opening. The thickness of the thin polycrystalline silicon layer 332 is preferably between 200 and 500 angstroms. After that, please refer to FIG. 3D, apply the high temperature thermal oxidation method to the polycrystalline silicon layer 332 to make it react with oxygen to transform into the silicon oxide layer 334 β. The implementation temperature of the above thermal oxidation method is from 800 to 1 It is preferably between 00 ° C. Then referring to FIG. 3E, an etch-back process is performed to etch the silicon oxide layer 3 3 4 to the top surface of the insulating layer 3 2 8 to form a silicon oxide spacer 334 on the side wall of the second contact opening 3 3 0. , And the top surface of the conductive plug 326 is exposed. Next, referring to FIG. 3F, a conductive layer 336 is formed on the first insulating layer 324, the second insulating layer 328, the conductive plug 326, and the silicon oxide spacer 334. A protective layer 338 is then formed on the conductive layer 336, which fills the second contact opening 330. The conductive layer 336 can be a conductively doped complex

V. Description of the invention (7)-The silicon and the protective layer 338 may be a photoresist material. Next, referring to FIG. 3G, a planarization step such as an etch-back process is performed, and the conductive layer 3 36 and the protective layer 338 on the second insulating layer 328 'are removed, leaving the protective layer 338 in the second contact opening 330. , And a conductive layer 336, (for the lower electrode). The planarization process may be a chemical mechanical polishing (CMp) method. After that, the protective layer 33 8 'is removed, and then, referring to FIG. 3 (a), a dielectric layer 340 is formed on the second insulating layer 3 2 8, the oxide spacer 334', and the lower electrode 336 '. Then, an upper electrode 342 is formed on the dielectric layer 340 to complete the crown capacitor structure of the dynamic random access memory of the present invention. [Wherein the dielectric layer 340 may be a silicon oxide / silicon nitride / silicon oxide layer (ONO: oxide / nitride / oxide), oxide group (Ta205), silicon oxide or silicon nitride with high dielectric constant insulation layer. The upper electrode 342 may be a conductively doped polycrystalline silicon layer. Therefore, the method of the present invention is mainly to add a silicon oxide spacer formed by thermal oxidation on the side wall of the second contact opening in the second insulating layer. 3 34, 'The silicon oxide formed by the thermal oxidation method is insulating. The performance is better than the traditional oxidative debris formed by chemical vapor deposition, so it can effectively improve the electrical insulation between capacitors, reduce the leakage between capacitors, and achieve better data storage results. At the same time, those skilled in the art should understand that the material materials available in the present invention are not limited to the traditional dynamic random access memory cited in the embodiments, but also applicable to embedded dynamic random access memory, and can be used by Replaced by various materials and forming methods with the same characteristics, and the structural space of the present invention is not limited to the dimensions cited in the examples.

Claims (1)

^ 27003 I A manufacturing method of dynamic random access memory, suitable for:-on a semiconductor substrate with a switching element: the above capacitor is manufactured, and the above manufacturing method includes the following steps: the first connection to the switching element is formed on the semiconductor with a A first insulating layer contacting the opening; forming a conductive plug in the first contact opening; forming a second insulating layer on the first insulating layer and the conductive plug; forming a communicable in the second insulating layer A second contact opening of the conductive plug; forming a polycrystalline dream layer on the second insulating layer and inside the second contact opening; and performing a thermal oxidation method to convert the polycrystalline silicon layer into a silicon oxide layer etch back The silicon oxide layer to the second insulating layer ′ to form a silicon oxide spacer on a side wall of the second contact opening; forming a lower electrode in the second contact opening; forming a dielectric layer on the lower electrode; and An upper electrode is formed on the dielectric layer. 2. The method according to item 丨 of the patent application scope, wherein the dynamic random access memory system is an embedded dynamic random access memory. 3. The method according to item 丨 in the scope of the patent application, wherein the thickness of the above-mentioned polycrystalline silicon layer is between 200 and 50 angstroms. 4. The method according to item 丨 of the scope of patent application, wherein the implementation temperature of the thermal oxidation method is between 800 and 1000. (:between. Page 12 --- 427093 VI. Application for Patent Π. The method described in item 1 of the patent application, wherein the above dielectric layer is selected from silicon oxide / silicon nitride / silicon oxide, tantalum oxide, and oxide. Substances in the family of silicon and silicon nitride. 12. The method according to item 1 of the scope of patent application, wherein the lower electrode is a conductively doped polycrystalline silicon layer. Page 14