KR0180784B1 - Method for forming semiconductor capacitor - Google Patents
Method for forming semiconductor capacitor Download PDFInfo
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- KR0180784B1 KR0180784B1 KR1019950050431A KR19950050431A KR0180784B1 KR 0180784 B1 KR0180784 B1 KR 0180784B1 KR 1019950050431 A KR1019950050431 A KR 1019950050431A KR 19950050431 A KR19950050431 A KR 19950050431A KR 0180784 B1 KR0180784 B1 KR 0180784B1
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- oxide film
- film
- forming
- electrode
- conductive oxide
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000003990 capacitor Substances 0.000 title claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 27
- 238000003860 storage Methods 0.000 claims abstract description 14
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000004020 conductor Substances 0.000 claims abstract description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 9
- 239000010936 titanium Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 19
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 18
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims description 6
- 229910000457 iridium oxide Inorganic materials 0.000 claims description 6
- 239000002887 superconductor Substances 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 3
- 230000007704 transition Effects 0.000 claims description 3
- 230000010354 integration Effects 0.000 abstract description 10
- 238000005516 engineering process Methods 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 description 8
- 239000007789 gas Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910010252 TiO3 Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910003446 platinum oxide Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로, 하부 절연층이 형성된 반도체기판의 예정된 부분에 접속되는 콘택플러그를 형성하고 전체표면상부에 티타늄막/티타늄질화막을 일정두께 형성한 다음, 그 상부에 전도성 산화막을 형성하고 그 상부에 반구형 도전체를 형성한 다음, 이 방성식각공정으로 요철이 형성된 전도성산화막을 형성하고 저장전극마스크를 이용한 식각공정으로 캐패시터의 하부전극인 저장전극을 형성한 다음, 전체표면상부에 강유전성의 유전체막과 캐패시터의 상부전극인 플레이트전극을 순차적으로 형성하여 반도체소자의 고집적화에 충분한 정전용량을 갖는 캐패시터를 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device, wherein a contact plug is formed to be connected to a predetermined portion of a semiconductor substrate on which a lower insulating layer is formed, and a titanium film / titanium nitride film is formed on the entire surface, and then a thickness is formed thereon. A conductive oxide film is formed, a hemispherical conductor is formed thereon, a conductive oxide film having unevenness is formed by this anisotropic etching process, and a storage electrode, which is a lower electrode of the capacitor, is formed by an etching process using a storage electrode mask. A ferroelectric dielectric film and a plate electrode, which are the upper electrodes of the capacitor, are sequentially formed on the surface to form a capacitor having a capacitance sufficient for high integration of the semiconductor device, thereby improving the characteristics and reliability of the semiconductor device and thereby increasing the integration of the semiconductor device. It is a technology that makes it possible.
Description
제1a도 내지 제1f도는 본 발명의 실시예에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도.1A to 1F are cross-sectional views showing a capacitor forming method of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체기판 13 : 하부절연층11: semiconductor substrate 13: lower insulating layer
15 : 콘택홀 17 : 다결정 실리콘막15 contact hole 17 polycrystalline silicon film
19 : 티타늄막 21 : 티타늄질화막19: titanium film 21: titanium nitride film
23 : 루테늄산화막 25 : 반구형 다결정실리콘막23 ruthenium oxide film 25 hemispherical polysilicon film
29 : 감광막패턴 31 : 유전체막29 photosensitive film pattern 31 dielectric film
33 : 플레이트전극33: plate electrode
본 발명은 반도체소자인 캐패시터 형성방법에 관한 것으로, 특히 초고집적화된 반도체소자에 충분한 정전용량을 확보할 수 있도록 하부전극, 유전체막 및 상부전극의 캐패시터를 형성하여 디렘(DRAM)이나 비휘발성 메모리소자의 고집적화를 가능하게 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor, which is a semiconductor device. In particular, a capacitor of a lower electrode, a dielectric film, and an upper electrode is formed to secure sufficient capacitance in an ultra-highly integrated semiconductor device. It relates to a technology that enables high integration.
반도체소자가 고집적화되어 셀 크기가 감소됨에 따라 저장전극의 표면적에 비례하는 정전용량을 충분히 확보하기가 어려워지고 있다.As semiconductor devices are highly integrated and cell sizes are reduced, it is difficult to secure a capacitance that is proportional to the surface area of the storage electrode.
특히, 단위셀이 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게하면서, 면적을 줄이는 것이 디램 소자의 고집적화에 중요한 요인이 된다.In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, it is important to reduce the area while increasing the capacitance of a capacitor that occupies a large area on a chip, which is an important factor for high integration of the DRAM device.
그래서, (Eo X Er X A) / T(단, 상기 Eo 는 진공유전율, 상기 Er은 유전막의 유전율, 상기 A 는 캐패시터의 면적 그리고 상기 T는 유전막의 두께)로 표시되는 캐패시터의 정전용량 C를 증가시키기 위하여, 하부전극인 저장전극의 표면적을 증가시켜 캐패시터를 형성하였다. 그러나, 제조공정이 복잡하고 단차를 증가시켜 반도체소자의 고집적화를 어렵게 하였다. 그리하여, 유전상수 Er 이 높은 강유전성의 BST ((Ba, Sr)TiO₃)막 또는 PZT(Pb(Zr₁-xTix)O₃)(단, X, Y 는 조성비)막으로 상기 수식에서 유전체막의 두께를 나타내는 상기 T의 두께를 얇게하여 고유전율을 갖는 유전체막을 형성함으로써 반도체소자의 고집적화를 가능하게 하였다. 그러나, 종래기술에서 캐패시터를 형성하는 하부전극 표면에 발생되는 힐룩( hillock) 및 핀홀(pin hole)로 인해 전기적 소자인 경우에 있어서, 전기적 특성의 불안정성 및 재현성의 부족한 단점을 갖고 있다.Thus, the capacitance C of the capacitor represented by (Eo X Er XA) / T (wherein Eo is the vacuum dielectric constant, Er is the dielectric constant of the dielectric film, A is the area of the capacitor and T is the thickness of the dielectric film) is increased. In order to increase the surface area of the storage electrode, which is a lower electrode, a capacitor was formed. However, the manufacturing process is complicated and the step height is increased, making high integration of semiconductor devices difficult. Thus, the ferroelectric BST ((Ba, Sr) TiO₃) film or PZT (Pb (Zr₁-xTix) O₃) film (where X and Y are the composition ratio) films having a high dielectric constant Er may be used to express the thickness of the dielectric film in the above formula. The thickness of T was reduced to form a dielectric film having a high dielectric constant, thereby enabling high integration of semiconductor devices. However, in the prior art, in the case of an electrical device due to hillocks and pin holes generated on the surface of the lower electrode forming the capacitor, there is a disadvantage of instability and reproducibility of electrical characteristics.
그래서, 상기 단점을 해결하기 위하여 상기 하부전극 및 상부전극으로 루테늄산화막(RuO₂), 백금(Pt), 이리듐산화막(IrO₂)또는 YBaCuO3계 초전도계를 사용하여 캐패시터를 형성하고 이를 안정화시켜 사용하였다.Thus, in order to solve the above disadvantages, a capacitor was formed using a ruthenium oxide film (RuO₂), platinum (Pt), an iridium oxide film (IrO₂), or a YBaCuO3-based superconductor and stabilized as the lower electrode and the upper electrode.
그러나, 상기 루테늄산화막, 백금, 이리듐산화막 또는 YBaCuO3계 초전도체를 전극으로 사용하되, 종래와 같이 스택형(stack type)으로 캐패시터를 형성하는 경우는 4 기가디램(giga DRAM)급 이상의 메모리소자에서는 충분한 정전용량을 확보할 수 없어 반도체소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.However, when the ruthenium oxide film, platinum, iridium oxide film, or YBaCuO 3 based superconductor is used as an electrode, in the case of forming a capacitor in a stack type as in the prior art, a sufficient electrostatic discharge in a 4 giga DRAM or more memory device is achieved. There is a problem in that the capacity cannot be secured, thereby deteriorating the characteristics and reliability of the semiconductor device and consequently making the semiconductor device highly integrated.
따라서, 본 발명은 종래기술의 문제점을 해결하기 위하여, 스택형의 하부전극 상측면에 요철을 형성하여 표면적을 증가시킴으로써 반도체소자의 고집적화에 충분한 정전용량을 갖는 캐패시터를 형성하여 반도체소자의 신뢰성 및 생산성을 향상시키고 그에 따른 바도체소자의 고집적화를 가능하게 하는 반도체소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the problems of the related art, the present invention provides a capacitor having a capacitance sufficient for high integration of semiconductor devices by increasing the surface area by forming irregularities on the upper surface of the stacked lower electrodes, thereby increasing the reliability and productivity of the semiconductor devices. It is an object of the present invention to provide a method for forming a capacitor of a semiconductor device that improves the performance of the semiconductor device and thereby enables high integration of the semiconductor device.
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 캐패시터 형성방법에 특징은,Features of the capacitor forming method of a semiconductor device according to the present invention to achieve the above object,
반도체기판 상부에 하부절연층이 형성되는 공정과,Forming a lower insulating layer on the semiconductor substrate;
캐패시터 콘택마스크를 이용한 식각공정으로 상기 반도체기판의 예정된 부분을 노출시키는 콘택홀이 형성되는 공정과,Forming a contact hole exposing a predetermined portion of the semiconductor substrate by an etching process using a capacitor contact mask;
상기 예정된 부분에 접속되는 콘택플러그가 형성되는 공정과,Forming a contact plug connected to the predetermined portion;
전체표면상부에 티타뉴막과 티타늄질화막이 순차적으로 일정두께 형성되는 공정과,Forming a titanic film and a titanium nitride film sequentially on the entire surface;
상기 티타늄질화막 상부에 전도성산화막이 일정두께 형성되는 공정과,Forming a conductive oxide film a predetermined thickness on the titanium nitride film;
상기 전도성산화막 상부에 반구형 도전체를 형성하는 공정과,Forming a hemispherical conductor on the conductive oxide film;
식각비를 이용한 이방성식각공정으로 상기 반구형 도전체와 전도성산화막을 식각하여 요철이 형성된 전도성산화막이 형성되는 공정과,Forming a conductive oxide film having irregularities by etching the hemispherical conductor and the conductive oxide film by an anisotropic etching process using an etching ratio;
저장전극마스크를 이용한 식각공정으로 상기 전도성산화막, 티타늄 질화막 및 티타늄막을 순차적으로 식각함으로써, 저장전극을 형성하는 공정과,Forming a storage electrode by sequentially etching the conductive oxide film, the titanium nitride film, and the titanium film by an etching process using a storage electrode mask;
전체표면상부에 유전체막과 플레이트전극을 순차적으로 형성하는 공정을 포함하는데 있다.It includes a step of sequentially forming a dielectric film and a plate electrode on the entire surface.
여기서, 상기 하부절연층은 비.피.에스.지(BPSG : Boro Phoshop Silicate Glass, 이하세서 BPSG라 함)와 같이 유동성이 우수한 절연물질로 형성되는 것과,Here, the lower insulating layer is formed of an insulating material having excellent fluidity, such as B.P.S. paper (BPSG: Boro Phoshop Silicate Glass, hereinafter referred to as BPSG),
상기 콘택플러그는 다결정실리콘으로 형성되는 것과,The contact plug is formed of polycrystalline silicon,
상기 전도성산화막은 루테늄산화막으로 형성되는 것과,The conductive oxide film is formed of a ruthenium oxide film,
상기 전도성산화막은 백금으로 형성되는 것과,The conductive oxide film is formed of platinum,
상기 전도성산화막과 플레이트전극은 이리듐산화막으로 형성되는 것과,The conductive oxide film and the plate electrode is formed of an iridium oxide film,
상기 전도성산화막과 플레이트전극은 YBaCuO3계 초전도체로 형성되는 것과,The conductive oxide film and the plate electrode is formed of a YBaCuO3-based superconductor,
상기 전도성산화막은 스퍼터링(sputtering)방법으로 형성되는 것과, 상기 전도성산화막은 화학기상증착(CVD : Chemical Vapor Deposition, 이하에서 CVD라 함)방법으로 형성되는 것과,The conductive oxide film is formed by a sputtering method, the conductive oxide film is formed by a chemical vapor deposition (CVD: CVD) method,
상기 전도성산화막은 3000 내지 6000Å두께로 형성되는 것과,The conductive oxide film is formed to a thickness of 3000 to 6000Å,
상기 반구형도전체는 500 내지 1000Å두께로 형성되는 것과,The hemispherical conductor is formed to a thickness of 500 to 1000Å,
상기 반구형도전체는 비정질과 결정질의 변이온도에서 형성되는 것과,The hemispherical conductor is formed at a transition temperature between amorphous and crystalline,
상기 이방성식각공정은 상기 전도성산화막과 반구형도전체와의 식각비를 1 내지 30 : 1호 하여 실시되는 것과,The anisotropic etching process is performed by the etching ratio of the conductive oxide film and the hemispherical conductor 1 to 30: 1,
상기 이방성식각공정은 탄소-불소 계열의 가스를 식각가스로 하여 실시되는 것과,The anisotropic etching process is performed by using a carbon-fluorine-based gas as an etching gas,
상기 유전체막은 BST 나 PZT와 같은 강유전성의 절연막으로 형성되는 것과, 상기 유전체막은 500 내지 1000Å두께로 형성되는 것과,The dielectric film is formed of a ferroelectric insulating film such as BST or PZT, the dielectric film is formed of a thickness of 500 to 1000 Å,
상기 플레이트전극은 2000 내지 5000 Å두께로 형성되는 것이다.The plate electrode is formed to have a thickness of 2000 to 5000 mW.
이상의 목적을 달성하기 위한 본 발명의 원리는, 저장전극, 즉 하부전극의 표면적을 증가시킴으로써 정전용량을 증가시키는 것으로, 강유전성의 유전체막에 절연막으로하는 상, 하부전극을 루테늄산화막, 백금, 이리듐산화막 또는 YBaCuO3계 초전도체로 형성하되, 상부면에 요철이 형성된 스택형으로 형성함으로써 4기가디램급 이상의 메모리소자에서 충분한 정전용량을 확보하는 것이다.The principle of the present invention for achieving the above object is to increase the capacitance by increasing the surface area of the storage electrode, i.e., the lower electrode, wherein the upper and lower electrodes which serve as an insulating film for the ferroelectric dielectric film are ruthenium oxide film, platinum, and iridium oxide film. Or formed of a YBaCuO3-based superconductor, but by forming a stack type with irregularities on the upper surface to ensure sufficient capacitance in the memory device of more than 4 gigabytes-class DRAM.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1f도는 본 발명의 실시예에 따른 반도체소자의 캐패시터 형성공정을 도시한 단면도이다.1A to 1F are cross-sectional views showing a capacitor forming process of a semiconductor device according to an embodiment of the present invention.
제1a도를 참조하면, 반도체기판(11)상부에 하부절연층(13)을 형성한다. 이때, 상기 하부절연층(13)은 소자분리절연막(도시안됨), 게이트산화막(도시안됨)그리고 게이트전극(도시안됨)을 형성하고 상부를 평탄화시키는 절연막이 형성된 것이다. 여기서, 상기 게이트전극 형성후에 비트라인(도시안됨)을 형성할 수도 있다. 그리고, 상기 절연막은 BPSG와 같이 유동성이 우수한 절연물질로 형성된 것이다. 그 다음에, 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 하부절연층(13)을 부분식각하여 상기 반도체기판(11)의 예정된 부분, 즉 불순물 접합영역(도시안됨)을 노출시키는 콘택홀(15)을 형성한다. 그리고, 상기 예정된 부분에 접속되며 상기 콘택홀(15)이 매립되도록 다결정실리콘막(17)으로 콘택플러그를 형성한다.Referring to FIG. 1A, a lower insulating layer 13 is formed on the semiconductor substrate 11. In this case, the lower insulating layer 13 is an insulating film for forming a device isolation insulating film (not shown), a gate oxide film (not shown), and a gate electrode (not shown) and planarize the top. Here, a bit line (not shown) may be formed after the gate electrode is formed. The insulating film is formed of an insulating material having excellent fluidity such as BPSG. Subsequently, the lower insulating layer 13 is partially etched by an etching process using a contact mask (not shown) to expose a predetermined portion of the semiconductor substrate 11, that is, a contact hole (not shown). 15). A contact plug is formed of the polysilicon layer 17 to be connected to the predetermined portion and to fill the contact hole 15.
제1b도를 참조하면, 제1a도의 공정후에 전체표면상부에 티타늄막(19)과 티타늄질화막(21)을 순차적으로 각각 일정두께 형성한다. 이때, 상기 티타늄 막(19)은 100 내지 300Å두께로 형성된 것이다. 그리고, 상기 티타늄질화막(21)은 200 내지 400Å두께로 증착된 것이다. 그리고, 상기 티타늄막(19)과 티타늄질화막(21)은 스퍼터링방법이나 CVD 방법으로 형성된 것으로, 후속공정에서 형성된 유전체막(도시안됨)과 상기 다결정실리콘막(17)사이의 산소확산을 방지하고 상기 다결정실리콘막(17)과 전도성산화막(도시안됨)과의 접착력을 증대시키기 위한 것이다. 이때, 상기 전도성산화막은 상부 및 하부전극으로 사용되는 것이다.Referring to FIG. 1B, after the process of FIG. 1A, a titanium film 19 and a titanium nitride film 21 are sequentially formed on the entire surface, respectively. At this time, the titanium film 19 is formed to a thickness of 100 ~ 300Å. In addition, the titanium nitride film 21 is deposited to a thickness of 200 to 400 kPa. The titanium film 19 and the titanium nitride film 21 are formed by a sputtering method or a CVD method to prevent oxygen diffusion between the dielectric film (not shown) and the polysilicon film 17 formed in a subsequent process. This is to increase the adhesion between the polysilicon film 17 and the conductive oxide film (not shown). In this case, the conductive oxide film is used as the upper and lower electrodes.
그 다음에, 상기 티타늄질화막(21) 상부에 루테늄산화막(23)을 일정두께 형성한다. 이때, 상기 루테늄산화막(23)은 3000 내지 6000Å두께로 형성된 것이다. 그리고, 상기 루테늄산화막(23)은 스퍼터링방법이나 CVD 방법으로 형성된 것이다. 여기서, 상기 루테늄산화막(23)은 루테늄 타켓(target)에 산소 가스와 아르곤가스를 사용하여 형성된 것이다. 참고로, 상기 루테늄산화막(23)은 백금, 이리듐산화막 또는 YBaCuO3 계 초전도체를 대신 사용할 수 있다.Next, a ruthenium oxide film 23 is formed on the titanium nitride film 21 at a predetermined thickness. At this time, the ruthenium oxide film 23 is formed to have a thickness of 3000 to 6000 Å. The ruthenium oxide film 23 is formed by a sputtering method or a CVD method. Here, the ruthenium oxide film 23 is formed by using oxygen gas and argon gas in the ruthenium target. For reference, the ruthenium oxide layer 23 may use platinum, iridium oxide layer or YBaCuO3-based superconductor instead.
제1c도를 참조하면 상기 루테늄산화막(23) 상부에 반구형 다결정실리콘막(25)을 형성한다. 이때, 상기 반구형 다결정실리콘막(25)은 비정질과 결정질의 변이온도(transition temperature)에서 형성된 것으로, 일반적인 LPCVD방법은 사이렌(SiH4, silane)가스를 사용하여 570내지 600℃의 온도에서 증착온도가 결정되며 증착두께는 500 내지 1000Å이다.Referring to FIG. 1C, a hemispherical polysilicon film 25 is formed on the ruthenium oxide film 23. In this case, the hemispherical polysilicon layer 25 is formed at a transition temperature of amorphous and crystalline, and a general LPCVD method uses a siren (SiH 4 , silane) gas to deposit a temperature of 570 to 600 ° C. And the deposition thickness is 500 to 1000 mW.
제1d도를 참조하면, 상기 제1c도의 공정후에 상기 반구형 다결정 실리콘막(25)을 이방성식각공정으로 상기 루테늄산화막(23)을 소정두께 식각하여 요철이 형성된 루테늄산화막(23)을 형성한다. 이때, 상기 이방성식각공정은 상기 루테늄산화막(23)과 반구형 다결정실리콘막(25)의 식각선택비가 1 내지 10 : 1 이 되도록 하고 식각가스는 탄소-불소(C-F) 계열의 가스가 사용된 것이다. 여기서, 상기 식각선택비가 10 : 1이고 상기 반구형 다결정실리콘막(25)의 두께가 500Å 두께인 경우, 상기 루테늄산화막(23)에 형성되는 요철은 1000Å정도의 높이로 형성된다.Referring to FIG. 1D, after the process of FIG. 1C, the ruthenium oxide film 23 is etched by a predetermined thickness by anisotropic etching of the hemispherical polycrystalline silicon film 25 to form a ruthenium oxide film 23 having irregularities. In this case, the anisotropic etching process is such that the etching selectivity of the ruthenium oxide film 23 and the hemispherical polysilicon film 25 is 1 to 10: 1 and the etching gas is a carbon-fluorine (C-F) -based gas. In this case, when the etching selectivity is 10: 1 and the thickness of the hemispherical polysilicon film 25 is 500 mW, the unevenness formed in the ruthenium oxide film 23 is formed to a height of about 1000 mW.
참고로, 상기 반구형 다결정 실리콘막(25)은 상기 제1d도의 공정으로 제거된다.For reference, the hemispherical polycrystalline silicon film 25 is removed by the process of FIG. 1d.
제1e도를 참조하면, 상기 요철이 형성된 루테늄산화막(23)상부에 감광막패턴(29)을 형성한다. 이때, 상기 감광막패턴(29)은 캐패시터의 하부전극, 즉 저장전극을 형성하기 위한 저장전극마스크(도시안됨)를 이용한 노광 및 형상공정으로 형성된 것이다.Referring to FIG. 1E, a photosensitive film pattern 29 is formed on the ruthenium oxide film 23 having the unevenness. In this case, the photoresist layer pattern 29 is formed by an exposure and a shape process using a storage electrode mask (not shown) for forming a lower electrode of the capacitor, that is, a storage electrode.
제1f도를 참조하면, 상기 감광막패턴(29)을 마스크로하여 상기 요철이 형성된 루테늄산화막(23), 티타늄질화막(21) 및 티타늄막(19)을 순차적으로 식각하여 저장전극을 형성한다. 그리고, 상기 감광막패턴(29)을 제거한다. 그 다음에, 전체표면상부에 유전체막(31)을 일정두께 형성한다. 이때, 상기 유전체막(31)은 강유전성의 절연막으로서, BST 또는 PZT 가 사용된 것이다. 그리고, 상기 유전체막(31)은 500 내지 1000Å두께로 형성된 것이다. 그 다음에, 전체표면상부에 상부전극인 플레이트전극(33)을 형성한다. 이때, 상기 플레이트전극(33)은 상기 하부전극인 저장전극과 같은 물질로 형성된 것이다. 그리고 상기 플레이트전극(33)은 2000 내지 5000Å두께로 형성된 것이다.Referring to FIG. 1f, the ruthenium oxide layer 23, the titanium nitride layer 21, and the titanium layer 19 having the unevenness are sequentially etched using the photoresist pattern 29 as a mask to form a storage electrode. Then, the photoresist pattern 29 is removed. Then, a dielectric film 31 is formed on the entire surface at a constant thickness. At this time, the dielectric film 31 is a ferroelectric insulating film, BST or PZT is used. The dielectric film 31 is formed to have a thickness of 500 to 1000 mW. Then, the plate electrode 33 serving as the upper electrode is formed on the entire surface. In this case, the plate electrode 33 is formed of the same material as the storage electrode as the lower electrode. In addition, the plate electrode 33 is formed to a thickness of 2000 to 5000Å.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 캐패시터 형성방법은, 강유전성 유전체막과 전도성산화막의 상, 하부전극으로 구성된 캐패시터를 형성하되, 저장전극인 상기 하부전극의 상측면에 요철을 형성함으로써 표면적을 증가시켜 반도체소자의 고집적화에 충분하 정전용량을 갖는 캐패시터를 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, in the method of forming a capacitor of a semiconductor device according to the present invention, a capacitor including a top electrode and a bottom electrode of a ferroelectric dielectric film and a conductive oxide film is formed, and surface areas are formed by forming irregularities on the top surface of the bottom electrode as a storage electrode. By increasing the number of capacitors to form a capacitor having a capacitance sufficient for high integration of the semiconductor device has the advantage of improving the characteristics and reliability of the semiconductor device and thereby high integration of the semiconductor device.
Claims (17)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR19980016024A (en) * | 1996-08-26 | 1998-05-25 | 김주용 | Method for forming capacitor of semiconductor device |
| KR100431811B1 (en) * | 2001-12-12 | 2004-05-17 | 주식회사 하이닉스반도체 | A method for forming a capacitor of a semiconductor device |
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| JP3169866B2 (en) * | 1997-11-04 | 2001-05-28 | 日本電気株式会社 | Thin film capacitor and method of manufacturing the same |
| US20030020122A1 (en) * | 2001-07-24 | 2003-01-30 | Joo Jae Hyun | Methods of forming integrated circuit electrodes and capacitors by wrinkling a layer that includes a noble metal oxide, and integrated circuit electrodes and capacitors fabricated thereby |
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1995
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR19980016024A (en) * | 1996-08-26 | 1998-05-25 | 김주용 | Method for forming capacitor of semiconductor device |
| KR100431811B1 (en) * | 2001-12-12 | 2004-05-17 | 주식회사 하이닉스반도체 | A method for forming a capacitor of a semiconductor device |
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