KR100424389B1 - Method for manufacturing a contact/via electrode of semiconductor device - Google Patents
Method for manufacturing a contact/via electrode of semiconductor device Download PDFInfo
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- KR100424389B1 KR100424389B1 KR10-2001-0037353A KR20010037353A KR100424389B1 KR 100424389 B1 KR100424389 B1 KR 100424389B1 KR 20010037353 A KR20010037353 A KR 20010037353A KR 100424389 B1 KR100424389 B1 KR 100424389B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체 장치의 콘택/비아 제조방법에 관한 것으로, 특히 반도체 기판 상부에 층간 절연막을 형성하고 층간 절연막에 콘택/비아홀을 형성하고, 층간 절연막 상부에 Ti막과 제1 TiN막이 적층된 장벽 금속막을 형성하고, 장벽 금속막이 형성된 구조물의 제1 TiN막 표면을 N2 플라즈마 처리하여 고에너지 상태로 만들고, 제1 TiN막 표면을 N2 어닐링하여 제1 TiN막 상부에 균일한 막질의 제2 TiN막을 형성하고, 제2 TiN막 및 장벽 금속막이 형성된 콘택/비아홀에 도전체를 매립하고 CMP로 평탄화하여 콘택/비아를 형성하는 단계를 포함한다. 그러므로, 본 발명은 N2 플라즈마에 의해 제1 TiN막이 표면처리되어 고에너지 상태가 되고, N2 어닐링 공정에 의해 균일한 막질을 갖는 제2 TiN막이 추가 형성되기 때문에 콘택/비아홀에 텅스텐의 증착시 사용되는 WF6 가스의 플루오린 침투를 방지할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact / via in a semiconductor device. In particular, a barrier metal in which an interlayer insulating film is formed on a semiconductor substrate, a contact / via hole is formed on the interlayer insulating film, and a Ti film and a first TiN film are stacked on the interlayer insulating film. A film is formed, the surface of the first TiN film of the structure on which the barrier metal film is formed is subjected to N2 plasma treatment to make a high energy state, and the surface of the first TiN film is N2 annealed to form a uniform film-like second TiN film on the first TiN film. And embedding a conductor in the contact / via hole in which the second TiN film and the barrier metal film are formed and planarizing the CMP to form the contact / via. Therefore, the present invention is used in the deposition of tungsten in the contact / via hole because the first TiN film is surface-treated by N2 plasma to become a high energy state, and a second TiN film having a uniform film quality is further formed by the N2 annealing process. It is possible to prevent fluorine penetration of WF6 gas.
Description
본 발명은 반도체 제조방법에 관한 것으로서, 특히 Ti과 실리콘/금속 배선이 접촉되는 콘택(contact)/비아(via)를 형성할 때 사용하는 장벽 금속막(barrierlayer)의 안정화를 달성하는 반도체 장치의 콘택/비아 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor, and in particular, a contact of a semiconductor device for achieving stabilization of a barrier metal layer used when forming a contact / via in which Ti and a silicon / metal wiring contact. / Via manufacturing method.
현재 반도체 소자가 고집적화, 소형화됨에 따라 디자인 룰이 감소되고 콘택홀 또는 비아의 에스팩트 비율(aspect ratio)은 증가하는 추세에 따라 시정수(RC) 지연이 반도체 소자의 동작 속도를 결정하는 중요한 요인이 되고 있으며 다층 배선 구조를 채택하고 있다. 이에 따라 고집적화에 따른 미세한 콘택/비아의 형성은 반도체 소자의 제조 공정에 있어서 중요한 요소이다.With increasing integration and miniaturization of semiconductor devices, design rules are decreasing and the aspect ratio of contact holes or vias is increasing, so the time constant (RC) delay is an important factor that determines the operation speed of semiconductor devices. And adopts a multilayer wiring structure. Accordingly, formation of fine contacts / vias due to high integration is an important factor in the manufacturing process of semiconductor devices.
도 1 내지 도 4는 종래 기술에 의한 반도체 장치의 콘택/비아 제조방법을 순차적으로 나타낸 공정 순서도로서, 여기에서는 다층 구조의 배선을 수직으로 연결하는 비아의 제조 공정에 대해 설명한다.1 to 4 are process flowcharts sequentially illustrating a method of manufacturing a contact / via of a semiconductor device according to the prior art, and a process of manufacturing a via for vertically connecting wires having a multilayer structure will be described.
먼저 도 1에 도시된 바와 같이, 반도체 기판(10)에 소자 공정을 실시하고 금속 배선(12)을 형성한다. 그리고 금속 배선(12)이 형성된 반도체 기판(10)의 구조물에 층간 절연막(14)을 형성하고 배선들사이의 전기적 연결 통로인 비아홀(16)을 형성한다.First, as shown in FIG. 1, an element process is performed on the semiconductor substrate 10, and the metal wiring 12 is formed. The interlayer insulating layer 14 is formed in the structure of the semiconductor substrate 10 on which the metal wiring 12 is formed, and the via hole 16, which is an electrical connection path between the wirings, is formed.
이어서 도 2에 도시된 바와 같이, 비아홀(16)이 형성된 층간 절연막(14) 상부에 장벽 금속막(18)으로서 Ti막(18a) 및 TiN막(18b)을 적층해서 형성한다. 이때, 장벽 금속막(18)은 물리적기상증착(Physical Vapor Deposition : 이하 PVD라 함) 공정 또는 화학적기상증착(Chemical Vapor Deposition : 이하 CVD라 함) 공정으로 진행될 수 있으나 대개 PVD인 스퍼터링(sputtering) 방식으로 형성된다.Subsequently, as shown in FIG. 2, the Ti film 18a and the TiN film 18b are laminated | stacked and formed as the barrier metal film 18 on the interlayer insulation film 14 in which the via hole 16 was formed. In this case, the barrier metal film 18 may be a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process, but is usually a PVD sputtering method. Is formed.
그 다음 도 3에 도시된 바와 같이, 장벽 금속막(18)이 형성된 비아홀(16)에 도전체 물질로서 텅스텐(W)(20)을 CVD로 증착하여 비아홀(16)을 매립한다.3, tungsten (W) 20 is deposited by CVD as a conductive material in the via hole 16 in which the barrier metal film 18 is formed, and the via hole 16 is buried.
그리고나서 도 4에 도시된 바와 같이, 화학적기계적연마(Chemical Mechanical Polishing: 이하 CMP라 함) 공정으로 텅스텐(20) 및 장벽 금속막(18)을 연마해서 텅스텐 플러그(W plug:)(20')을 형성한다. 이때 CMP 공정은 층간 절연막(14) 표면이 드러날 때까지 진행한다. 여기서, 텅스텐 플러그(20')는 비아를 구성하는 것으로 비아홀에 매립되는 텅스텐을 일컫는 것이다.Then, as shown in FIG. 4, the tungsten 20 and the barrier metal film 18 are polished by a chemical mechanical polishing (CMP) process to make a tungsten plug (W plug :) 20 '. To form. At this time, the CMP process proceeds until the surface of the interlayer insulating film 14 is exposed. Here, the tungsten plug 20 'refers to tungsten embedded in the via hole as a part of the via.
종래 기술에 의한 제조 공정에 있어서, 텅스텐(20)의 증착은 일반적으로 화학기상증착법(Chemical Vapor Deposition : 이하 CVD라 함)으로 진행한다. 텅스텐을 CVD로 증착할 때 가스는 수소(H), 사일렌(SiH4), 텅스텐 헥사플로라이드(WF6)을 사용하고 대개 2단계로 증착 공정을 진행한다. 첫 번째는 WF6와 사일렌 가스를 이용하여 핵생성을 하는 단계이며 이후로 이루어지는 실질적인 텅스텐 증착의 전 단계이다. 두 번째는 수소와 WF6를 이용하여 텅스텐을 증착하는 단계이다.In the manufacturing process according to the prior art, the deposition of tungsten 20 generally proceeds by chemical vapor deposition (hereinafter referred to as CVD). When tungsten is deposited by CVD, the gas uses hydrogen (H), xylene (SiH4), tungsten hexafluoride (WF6) and is usually carried out in two steps. The first step is to nucleate using WF6 and xylene gas, followed by the actual preliminary steps of tungsten deposition. The second step is to deposit tungsten using hydrogen and WF6.
그런데, 이와 같은 종래 기술에 의해 콘택홀 또는 비아홀에 텅스텐을 CVD로 증착할 경우 WF6 가스에 함유되어 있는 플루오린(F)이 실리콘 기판 또는 불균일하게 증착된 장벽 금속막의 Ti과 반응성이 매우 좋아 쉽게 반응 생성물(TiF3, TiF4, SiFx 및 WSix 등)이 형성된다. 이에 따라, 종래 기술은 텅스텐 증착 공정시 장벽 금속막(18)으로서 Ti막(18a) 상부에 TiN막(18b)을 적층함으로써 추가된 TiN막에 의해 플루오린(F)의 침투를 막아줌과 동시에 텅스텐(W)과의 접촉성을 증가시킨다.However, according to the conventional technique, when tungsten is deposited in contact holes or via holes by CVD, fluorine (F) contained in the WF6 gas is highly reactive with Ti of a silicon substrate or a non-uniformly deposited barrier metal film, and thus reacts easily. Products (TiF3, TiF4, SiFx and WSix, etc.) are formed. Accordingly, the prior art prevents penetration of fluorine (F) by the added TiN film by laminating the TiN film 18b on the Ti film 18a as the barrier metal film 18 during the tungsten deposition process. Increases contact with tungsten (W).
하지만, 장벽 금속막(18)의 TiN(18b)은 주상 구조(columnar structure)를 갖기 때문에 밀도가 치밀(dense)하지 못하게 된다. 이에 콘택홀/비아홀에서 불균일하게 증착될 경우 결정립을 통해서 WF6의 플루오린(F)이 용이하게 침투하게 된다.도 4와 같이, 텅스텐 플러그(20')와 금속 배선(12) 사이에서 TiFx 등과 같은 반응 생성물(24)을 형성하게 되고, 이러한 반응 생성물(24)은 콘택/비아의 접촉 저항을 증가시키거나 후속 열공정시 팽창해서 콘택/비아 오픈 또는 접촉 불량의 문제점을 야기시키게 된다.However, since the TiN 18b of the barrier metal film 18 has a columnar structure, the density is not dense. Therefore, when unevenly deposited in the contact hole / via hole, fluorine (F) of WF6 easily penetrates through the grains. As shown in FIG. 4, the TiFx or the like is interposed between the tungsten plug 20 'and the metal wire 12. Reaction products 24 are formed, and these reaction products 24 increase the contact resistance of the contacts / vias or expand during subsequent thermal processes, causing problems with contact / via openings or poor contact.
현재, WF6 가스와 TiN막의 금속 반응으로 생성된 반응물을 제거하고자 여러 가지 기술이 연구 및 개발되고 있다. 예를 들면, 적정한 TiN막의 두께를 두께를 찾아서 적용하는 한편, PVD장비의 타겟과 스테이지간의 거리를 넓혀서 균일한 TiN막을 확보하거나, 콜리메이터(collimator)를 사용하여 원하지 않는 방향으로 증착되는 것을 방지하거나, 장비에 바이어스를 인가하여 증착되는 원자의 방향성을 증가시켜 TiN막의 증착 균일성을 향상시킨다.Currently, various techniques have been researched and developed to remove reactants generated by metal reaction of WF6 gas and TiN film. For example, by applying the appropriate thickness of the TiN film to find the thickness, while increasing the distance between the target and the stage of the PVD equipment to ensure a uniform TiN film, or to prevent deposition in an unwanted direction by using a collimator (collimator), A bias is applied to the equipment to increase the orientation of the deposited atoms to improve the deposition uniformity of the TiN film.
하지만, 상술한 종래 기술에서는 장벽 역할을 하는 TiN막의 증착 균일성을 향상시키는데 한계가 있고 이로 인해 텅스텐 증착시 플루오린(F)의 침투를 완벽하게 차단할 수 없어 콘택/비아의 전기적 특성 및 신뢰성을 저하시키는 문제점이 있었다.However, in the above-described prior art, there is a limit in improving the deposition uniformity of the TiN film serving as a barrier, and thus, it is impossible to completely block the penetration of fluorine (F) during tungsten deposition, thereby deteriorating the electrical properties and reliability of the contact / via. There was a problem letting.
본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위하여 콘택홀/비아홀에 텅스텐을 매립하기 전에 N2 플라즈마 처리(plasma treatment)와 N2 어닐링(annealing) 공정을 실시함으로써 장벽 금속막의 TiN막을 표면처리하여 고에너지 상태로 만들고 그 표면에 균일한 TiN막을 추가함으로써 이후 텅스텐 증착시 사용되는 WF6 가스의 플루오린 침투를 방지할 수 있는 반도체 장치의 콘택/비아 제조방법을 제공하는데 있다.An object of the present invention is to surface-treat the TiN film of the barrier metal film by performing an N2 plasma treatment and an N2 annealing process before embedding tungsten in the contact hole / via hole to solve the problems of the prior art. The present invention provides a method for manufacturing a contact / via of a semiconductor device capable of preventing high fluorine penetration of WF6 gas used in tungsten deposition by making a high energy state and adding a uniform TiN film on its surface.
이러한 목적을 달성하기 위하여 본 발명은 도전 패턴 또는 도전 영역을 포함한 반도체 기판 상부에 층간 절연막을 형성하고 층간 절연막에 콘택/비아홀을 형성하는 단계와, 콘택/비아홀이 형성된 층간 절연막 상부에 Ti막과 제1 TiN막이 적층된 장벽 금속막을 형성하는 단계와, 장벽 금속막이 형성된 구조물의 제1 TiN막 표면을 N2 플라즈마 처리하여 고에너지 상태로 만드는 단계와, 표면이 고에너지 상태로 된 제1 TiN막 표면을 N2 어닐링하여 제1 TiN막 상부에 균일한 막질의 제2 TiN막을 형성하는 단계와, 제2 TiN막 및 장벽 금속막이 형성된 콘택/비아홀에 도전체를 매립하고 CMP로 평탄화하여 콘택/비아를 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of forming an interlayer insulating film over a semiconductor substrate including a conductive pattern or a conductive region and forming a contact / via hole in the interlayer insulating film, and forming a Ti film and a second interlayer insulating film on the contact / via hole. Forming a barrier metal film in which a TiN film is laminated; making a surface of the first TiN film of the structure on which the barrier metal film is formed by N 2 plasma treatment to make a high energy state; and a surface of the first TiN film having a high energy state. Annealing N2 to form a second TiN film having a uniform film quality on the first TiN film, and filling a contact / via hole in the contact / via hole where the second TiN film and the barrier metal film are formed and planarizing the contact / via by CMP; Steps.
도 1 내지 도 4는 종래 기술에 의한 반도체 장치의 콘택/비아 제조방법을 순차적으로 나타낸 공정 순서도,1 to 4 are process flowcharts sequentially showing a contact / via manufacturing method of a semiconductor device according to the prior art;
도 5 내지 도 9는 본 발명에 따른 반도체 장치의 콘택/비아 제조방법을 순차적으로 나타낸 공정 순서도.5 to 9 are process flowcharts sequentially showing a method for manufacturing a contact / via of a semiconductor device according to the present invention.
＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
100 : 반도체 기판 102 : 도전체 패턴100 semiconductor substrate 102 conductor pattern
104 : 층간 절연막 106 : 비아홀104: interlayer insulating film 106: via hole
108 : 장벽 금속막 108a : Ti막108: barrier metal film 108a: Ti film
108b : 제1TiN막 110 : 제 2TiN막108b: 1st TiN film 110: 2nd TiN film
112 : 갭필막 112' : 비아112: gap fill film 112 ': via
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 5 내지 도 9는 본 발명에 따른 반도체 장치의 콘택/비아 제조방법을 순차적으로 나타낸 공정 순서도이다. 본 발명의 실시예는 다층 구조의 배선을 수직으로 연결하는 비아의 제조 공정을 예로 든다.5 through 9 are process flowcharts sequentially illustrating a method of manufacturing a contact / via of a semiconductor device according to the present invention. Embodiments of the present invention exemplify a manufacturing process of vias that vertically connect wiring of a multilayer structure.
도 5에 도시된 바와 같이, 반도체 기판(100)에 소자 공정을 실시하고 금속 배선(102)을 형성한다. 그리고 금속 배선(102)이 형성된 반도체 기판(100)의 구조물에 층간 절연막(104)을 형성하고 층간 절연막(104)을 식각해서 배선들사이의 전기적 연결 통로인 비아홀(106)을 형성한다.As shown in FIG. 5, an element process is performed on the semiconductor substrate 100 and the metal wiring 102 is formed. The interlayer insulating film 104 is formed on the structure of the semiconductor substrate 100 on which the metal wiring 102 is formed, and the interlayer insulating film 104 is etched to form the via hole 106, which is an electrical connection path between the wirings.
이어서 도 6에 도시된 바와 같이, 비아홀(106)을 갖는 층간 절연막(104)에 장벽 금속막(108)으로서 Ti막(108a) 및 제1 TiN막(108b)을 적층해서 형성한다. 이때, 장벽 금속막(108)의 Ti막(108a) 및 제1 TiN막(108b)은 PVD 또는 CVD에 의해 증착된다. 본 실시예에서는 Ti막(108a)의 두께를 200Å∼500Å, 제1 TiN막(108b)의 두께를 100Å∼500Å으로 한다.6, the Ti film 108a and the 1st TiN film 108b are laminated | stacked and formed as the barrier metal film 108 in the interlayer insulation film 104 which has the via hole 106. As shown in FIG. At this time, the Ti film 108a and the first TiN film 108b of the barrier metal film 108 are deposited by PVD or CVD. In this embodiment, the thickness of the Ti film 108a is 200 kPa to 500 kPa, and the thickness of the first TiN film 108b is 100 kPa to 500 kPa.
그 다음 도 7에 도시된 바와 같이, 장벽 금속막(108)이 형성된 비아홀(106)에 N2 플라즈마 표면처리와 N2 어닐링을 순차적으로 실시한다. 여기서, N2 플라즈마 표면처리는 N2 가스량을 50∼150sccm으로 하고 플라즈마의 전원을 DC 또는 RF를 사용하거나 바이어스를 인가한다. 그리고 N2 어닐링은 100% N2 램프업(ramp-up) 가스 상태에서 진행하고 N2 분위기에서 500℃∼800℃, 30∼90분동안 실시한다.Then, as shown in FIG. 7, N2 plasma surface treatment and N2 annealing are sequentially performed on the via hole 106 in which the barrier metal film 108 is formed. Here, in the N2 plasma surface treatment, the amount of N2 gas is set to 50 to 150 sccm, and the DC power source is applied to DC or RF or bias is applied. The N2 annealing is performed in a 100% N2 ramp-up gas state and is performed at 500 ° C to 800 ° C for 30 to 90 minutes in an N2 atmosphere.
이에 따라, 본 발명에서 주상 구조를 갖는 TiN막(108b) 표면은 N2 플라즈마에 의해 표면처리되어 고에너지 상태가 된다. 그리고 N2 어닐링 공정에 의해 장벽 금속막(108)의 제1 TiN막(108b) 상부에 균일한 막질을 갖는 제2 TiN막(110)이 추가 형성된다.Accordingly, in the present invention, the surface of the TiN film 108b having the columnar structure is surface-treated by N2 plasma to be in a high energy state. A second TiN film 110 having a uniform film quality is further formed on the first TiN film 108b of the barrier metal film 108 by the N2 annealing process.
그 다음 도 8에 도시된 바와 같이, N2 플라즈마 및 N2 어닐링 공정이 실시되어 제2 TiN막(110) 및 장벽 금속막(108)이 형성된 비아홀(106)에 도전체 물질로서 텅스텐(W)(112)을 CVD로 증착하여 비아홀(106)을 텅스텐(112)으로 매립한다. 이때 증착되는 텅스텐(112)의 두께는 3000Å∼7000Å으로 한다.Then, as shown in FIG. 8, tungsten (W) 112 as a conductor material is formed in the via hole 106 in which the N2 plasma and N2 annealing processes are performed to form the second TiN film 110 and the barrier metal film 108. ) Is deposited by CVD to fill the via hole 106 with tungsten 112. At this time, the thickness of the tungsten 112 deposited is 3000 kPa to 7000 kPa.
그리고나서 도 9에 도시된 바와 같이, CMP 공정으로 텅스텐(112), 제2 TiN막(110), 및 장벽 금속막(108)을 층간 절연막(104) 표면이 드러날 때까지 연마해서 텅스텐 플러그(112')을 형성하여 본 발명에 따른 비아 제조 공정을 완료한다.Then, as shown in FIG. 9, the tungsten 112, the second TiN film 110, and the barrier metal film 108 are polished by the CMP process until the surface of the interlayer insulating film 104 is exposed. ') Is formed to complete the via manufacturing process according to the present invention.
이상 설명한 바와 같이, 본 발명은 Ti/TiN의 장벽 금속막 상부에 N2 플라즈마 처리와 N2 분위기에서 어닐링함으로써 제1 TiN막 표면이 N2 플라즈마에 의해 표면처리되어 고에너지 상태가 되고, N2 어닐링 공정에 의해 장벽 금속막의 제1 TiN막 상부에 균일한 막질을 갖는 제2 TiN막이 추가 형성된다.As described above, in the present invention, the surface of the first TiN film is surface-treated by the N2 plasma to be in a high energy state by annealing in an N2 atmosphere and an N2 plasma treatment on the Ti / TiN barrier metal film, and by the N2 annealing process. A second TiN film having a uniform film quality is further formed on the first TiN film of the barrier metal film.
그러므로, 본 발명은 텅스텐의 CVD 공정시 WF6 가스 사용으로 장벽 금속막에 플루오린(F)이 침투하더라도 N2 플라즈마와 N2 어닐링 공정에 의해 N2 표면처리된 제1 TiN막과 균질한 막질을 갖는 제2 TiN막에 의해 TiFx 등의 반응 생성물이 생성되지 않는다.Therefore, in the present invention, even though fluorine (F) penetrates into the barrier metal film by using WF6 gas during the CVD process of tungsten, the second Ti film having a homogeneous film quality with the first TiN film treated with N2 by N2 plasma and N2 annealing process No reaction product such as TiFx is produced by the TiN film.
따라서, 본 발명은 장벽 금속막과 콘택/비아 사이의 반응 생성물로 인해 발생하는 접촉 불량을 미연에 방지하여 콘택/비아의 접촉 저항을 낮추고 반도체 장치의 수율 및 신뢰성을 높일 수 있다.Therefore, the present invention can prevent the contact failure caused by the reaction product between the barrier metal film and the contact / via in advance, thereby lowering the contact resistance of the contact / via and increasing the yield and reliability of the semiconductor device.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1187272A (en) * | 1997-09-04 | 1999-03-30 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR19990059087A (en) * | 1997-12-30 | 1999-07-26 | 김영환 | Metal wiring formation method of semiconductor device |
| KR19990074372A (en) * | 1998-03-10 | 1999-10-05 | 윤종용 | Barrier film formation method of semiconductor device and metal wiring formation method using same |
| KR20000043053A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Metalization of semiconductor device |
| US6146991A (en) * | 1999-09-03 | 2000-11-14 | Taiwan Semiconductor Manufacturing Company | Barrier metal composite layer featuring a thin plasma vapor deposited titanium nitride capping layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH1187272A (en) * | 1997-09-04 | 1999-03-30 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR19990059087A (en) * | 1997-12-30 | 1999-07-26 | 김영환 | Metal wiring formation method of semiconductor device |
| KR19990074372A (en) * | 1998-03-10 | 1999-10-05 | 윤종용 | Barrier film formation method of semiconductor device and metal wiring formation method using same |
| KR20000043053A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Metalization of semiconductor device |
| US6146991A (en) * | 1999-09-03 | 2000-11-14 | Taiwan Semiconductor Manufacturing Company | Barrier metal composite layer featuring a thin plasma vapor deposited titanium nitride capping layer |
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