KR20040080573A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20040080573A KR20040080573A KR1020030015421A KR20030015421A KR20040080573A KR 20040080573 A KR20040080573 A KR 20040080573A KR 1020030015421 A KR1020030015421 A KR 1020030015421A KR 20030015421 A KR20030015421 A KR 20030015421A KR 20040080573 A KR20040080573 A KR 20040080573A
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- forming
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- semiconductor device
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- layer
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- E—FIXED CONSTRUCTIONS
- E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
- E02B—HYDRAULIC ENGINEERING
- E02B3/00—Engineering works in connection with control or use of streams, rivers, coasts, or other marine sites; Sealings or joints for engineering works in general
- E02B3/04—Structures or apparatus for, or methods of, protecting banks, coasts, or harbours
- E02B3/12—Revetment of banks, dams, watercourses, or the like, e.g. the sea-floor
- E02B3/14—Preformed blocks or slabs for forming essentially continuous surfaces; Arrangements thereof
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- E—FIXED CONSTRUCTIONS
- E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
- E02B—HYDRAULIC ENGINEERING
- E02B15/00—Cleaning or keeping clear the surface of open water; Apparatus therefor
- E02B15/04—Devices for cleaning or keeping clear the surface of open water from oil or like floating materials by separating or removing these materials
- E02B15/08—Devices for reducing the polluted area with or without additional devices for removing the material
- E02B15/0835—Devices for reducing the polluted area with or without additional devices for removing the material fixed to permanent structure, e.g. harbour wall or river bank
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- E—FIXED CONSTRUCTIONS
- E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
- E02D—FOUNDATIONS; EXCAVATIONS; EMBANKMENTS; UNDERGROUND OR UNDERWATER STRUCTURES
- E02D29/00—Independent underground or underwater structures; Retaining walls
- E02D29/02—Retaining or protecting walls
Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히, 배리어층, 접착층 및 비트라인/비트라인 콘택 형성을 위한 도전층을 형성한 후 그 상부를 CMP 공정에 의하여 모두 제거함으로써 배리어층의 두께를 감소시켜 비트라인의 정전 용량을 감소시키며 공정을 단순화하는 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the barrier layer, the adhesive layer, and the conductive layer for forming the bit line / bit line contact are formed, and then the upper part is removed by CMP process to reduce the thickness of the barrier layer. A method of manufacturing a semiconductor device that reduces the capacitance of a bit line and simplifies the process.
반도체 소자의 집적도가 증가하면서, RC 지연에 의한 소자의 동작 속도 저하를 유발하는 비트라인의 저항 및 정전 용량이 문제시된다. 이러한 RC 지연을 감소시키기 위하여, 비트라인의 정전 용량과 저항을 감소시켜야 하므로, 현재 100nm급 DRAM에서는 텅스텐을 이용하여 비트라인과 비트라인 콘택을 동시에 형성하는 공정이 이용되고 있다.As the degree of integration of semiconductor devices increases, the resistance and capacitance of the bit lines, which cause the operation speed of the devices to decrease due to the RC delay, are problematic. In order to reduce the RC delay, the capacitance and resistance of the bit line must be reduced, and thus, a process of simultaneously forming bit line and bit line contact using tungsten is used in 100 nm DRAM.
상기 텅스텐을 이용한 비트라인 및 비트라인 콘택 형성 공정을 설명하면 다음과 같다.A bit line and bit line contact forming process using tungsten will be described below.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자 제조 방법을 도시한 단면도들이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 1a를 참조하면, 반도체 기판(10) 상부에 게이트 산화막 및 게이트 전극의 적층 구조(20) 및 그 측벽에 스페이서를 형성한 후 불순물 주입 영역(30)을 형성한다. 도 1b를 참조하면, 전체 표면 상부에 불순물 주입 영역(30)을 노출시키는 콘택홀(50)을 구비한 층간 절연막(40)을 형성한다. 도 1c를 참조하면, 콘택홀(50)의 내부를 포함하는 구조물 전면에 배리어층인 Ti막(60) 및 접착층인 TiN막(70)을 순차적으로 형성한다. 도 1d를 참조하면, 콘택홀(50)을 매립하는 텅스텐층(80)을 전체 표면 상부에 형성한다.Referring to FIG. 1A, a spacer is formed on the stacked structure 20 of the gate oxide film and the gate electrode and a sidewall thereof, and then the impurity implantation region 30 is formed on the semiconductor substrate 10. Referring to FIG. 1B, an interlayer insulating layer 40 having a contact hole 50 exposing the impurity implantation region 30 is formed over the entire surface. Referring to FIG. 1C, the Ti film 60, which is a barrier layer, and the TiN film 70, which is an adhesive layer, are sequentially formed on the entire structure including the inside of the contact hole 50. Referring to FIG. 1D, a tungsten layer 80 filling the contact hole 50 is formed on the entire surface.
상기 종래 기술에 따른 반도체 소자의 제조 방법에서는, 텅스텐을 비트라인 및 비트라인 콘택 재료로 사용하므로 배리어층 및 접착층을 반드시 형성하여야 하는데 이로 인하여 배리어층, 접착층 및 텅스텐층 전체의 두께가 증가하게 되어 이웃하는 비트라인 간의 정전 용량은 크게 증가하게 된다는 문제점이 있다. 또한, 정전 용량을 감소시키기 위하여 텅스텐층의 두께를 감소시키면 표면 스캐터링 효과(surface scattering effect)에 의하여 저항이 크게 증가하는 문제가 있다.In the method of manufacturing a semiconductor device according to the prior art, since tungsten is used as a bit line and a bit line contact material, a barrier layer and an adhesive layer must be formed. As a result, the thickness of the entire barrier layer, the adhesive layer, and the tungsten layer is increased. There is a problem that the capacitance between the bit lines is greatly increased. In addition, if the thickness of the tungsten layer is reduced in order to reduce the capacitance, there is a problem in that the resistance is greatly increased by the surface scattering effect.
상기 문제점을 해결하기 위하여, 배리어층, 접착층 및 비트라인/비트라인 콘택 형성을 위한 도전층을 형성한 후 그 상부를 CMP 공정에 의하여 모두 제거함으로써 배리어층의 두께를 감소시켜 비트라인의 정전 용량을 감소시키며 공정을 단순화하는 반도체 소자 제조 방법을 제공하는 것을 그 목적으로 한다.In order to solve the problem, the barrier layer, the adhesive layer, and the conductive layer for forming the bit line / bit line contact are formed, and then the upper part is removed by CMP process to reduce the thickness of the barrier layer to reduce the capacitance of the bit line. It is an object of the present invention to provide a method for fabricating a semiconductor device, which reduces and simplifies the process.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자 제조 방법을 도시한 단면도들.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2f는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도들.2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
본 발명에 따른 반도체 소자의 제조 방법은 반도체 기판 상부에 상기 반도체 기판의 소정 영역을 노출시키는 콘택홀을 구비한 층간 절연막을 형성하는 단계와, 상기 콘택홀의 저부 및 측벽을 포함하는 구조물 전면에 Ti/TiN의 적층 구조를 형성하는 단계와, 상기 콘택홀을 매립하는 제1 금속층을 전체 표면 상부에 형성하는 단계와, 상기 층간 절연막이 노출되도록 평탄화 공정을 수행하여 콘택 플러그를 형성하는 단계 및 상기 콘택 플러그와 전기적으로 접속되는 접착층 및 제2 금속층의 적층 구조를 전체 표면 상부에 형성하는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention includes forming an interlayer insulating film having a contact hole exposing a predetermined region of the semiconductor substrate on a semiconductor substrate, and forming Ti / in front of a structure including a bottom portion and a sidewall of the contact hole. Forming a contact plug by forming a stacked structure of TiN, forming a first metal layer filling the contact hole on the entire surface, and planarizing a process to expose the interlayer insulating film, and forming the contact plug. And forming a laminated structure of an adhesive layer and a second metal layer electrically connected to each other over the entire surface.
이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.
도 2a 내지 도 2f는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도들이다.2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 2a를 참조하면, 반도체 기판(100) 상부에 게이트 산화막 및 게이트 전극의 적층 구조(110) 및 그 측벽에 스페이서를 형성한 후 불순물 주입 영역(120)을 형성한다.Referring to FIG. 2A, a spacer is formed on the stacked structure 110 of the gate oxide film and the gate electrode and a sidewall thereof, and then the impurity implantation region 120 is formed on the semiconductor substrate 100.
도 2b를 참조하면, 전체 표면 상부에 불순물 주입 영역(120)을 노출시키는 콘택홀(140)을 구비한 층간 절연막(130)을 형성한다.Referring to FIG. 2B, an interlayer insulating layer 130 having a contact hole 140 exposing the impurity implantation region 120 is formed over the entire surface.
도 2c를 참조하면, 콘택홀(140)의 내부를 포함하는 구조물 전면에 Ti막(150)및 TiN막(160)을 순차적으로 형성한다. Ti막(150) 및 TiN막(160) 형성 후 열처리 공정을 추가적으로 수행할 수 있다.Referring to FIG. 2C, the Ti film 150 and the TiN film 160 are sequentially formed on the entire structure including the inside of the contact hole 140. After the Ti film 150 and the TiN film 160 are formed, a heat treatment process may be additionally performed.
도 2d를 참조하면, 콘택홀(140)을 매립하는 제1 금속층(170)을 전체 표면 상부에 형성한다. 여기서, 제1 금속층(170)은 텅스텐층인 것이 바람직하며, CVD 법을 이용해서 형성할 수 있다.Referring to FIG. 2D, a first metal layer 170 filling the contact hole 140 is formed on the entire surface. Here, the first metal layer 170 is preferably a tungsten layer, and can be formed using the CVD method.
도 2e를 참조하면, 층간 절연막(130)이 노출되도록 평탄화 공정, 바람직하게는 CMP(Chemical Mechanical Polishing) 공정을 수행하여 콘택 플러그(175)를 형성한다.Referring to FIG. 2E, the contact plug 175 is formed by performing a planarization process, preferably a chemical mechanical polishing (CMP) process, to expose the interlayer insulating layer 130.
도 2f를 참조하면, 콘택 플러그(175)와 전기적으로 접속되는 접착층(180) 및 제2 금속층(190)의 적층 구조를 전체 표면 상부에 형성한다. 접착층(180) 및 제2 금속층(180)은 각각 질화텅스텐층 및 텅스텐층인 것이 바람직하며, 접착층(180)은 ALD(Atomic Layer Deposition) 방법에 의하여 형성하는 것이 바람직하다.Referring to FIG. 2F, a laminated structure of the adhesive layer 180 and the second metal layer 190 electrically connected to the contact plug 175 is formed on the entire surface. Preferably, the adhesive layer 180 and the second metal layer 180 are tungsten nitride layers and tungsten layers, respectively, and the adhesive layer 180 is preferably formed by an atomic layer deposition (ALD) method.
본 발명에 따른 반도체 소자의 제조 방법은 배리어층, 접착층 및 비트라인/비트라인 콘택 형성을 위한 도전층을 형성한 후 그 상부를 CMP 공정에 의하여 모두 제거함으로써 배리어층의 두께를 감소시켜 비트라인의 정전 용량을 감소시키며 공정을 단순화하고 소자의 특성을 향상시키는 효과가 있다.In the method of manufacturing a semiconductor device according to the present invention, the barrier layer, the adhesive layer, and the conductive layer for forming the bit line / bit line contact are formed, and then the upper part is removed by CMP process to reduce the thickness of the barrier layer. It has the effect of reducing capacitance, simplifying the process and improving device characteristics.
Claims (7)
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100687881B1 (en) * | 2005-06-30 | 2007-02-27 | 주식회사 하이닉스반도체 | Method for fabricating metal interconnect in semiconductor device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06112155A (en) * | 1992-09-25 | 1994-04-22 | Matsushita Electron Corp | Formation of contact plug |
KR20010018072A (en) * | 1999-08-17 | 2001-03-05 | 박종섭 | Method of forming a tungsten line in a semiconductor device |
JP2001085438A (en) * | 1999-09-03 | 2001-03-30 | Chartered Semiconductor Mfg Ltd | Method for forming copper interconnection during manufacture of ic device |
JP2002158190A (en) * | 2000-11-20 | 2002-05-31 | Matsushita Electric Ind Co Ltd | Method of manufacturing semiconductor device |
KR20030001036A (en) * | 2001-06-28 | 2003-01-06 | 동부전자 주식회사 | Method for manufacturing a contact/via electrode of semiconductor device |
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2003
- 2003-03-12 KR KR1020030015421A patent/KR20040080573A/en not_active Application Discontinuation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06112155A (en) * | 1992-09-25 | 1994-04-22 | Matsushita Electron Corp | Formation of contact plug |
KR20010018072A (en) * | 1999-08-17 | 2001-03-05 | 박종섭 | Method of forming a tungsten line in a semiconductor device |
JP2001085438A (en) * | 1999-09-03 | 2001-03-30 | Chartered Semiconductor Mfg Ltd | Method for forming copper interconnection during manufacture of ic device |
JP2002158190A (en) * | 2000-11-20 | 2002-05-31 | Matsushita Electric Ind Co Ltd | Method of manufacturing semiconductor device |
KR20030001036A (en) * | 2001-06-28 | 2003-01-06 | 동부전자 주식회사 | Method for manufacturing a contact/via electrode of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100687881B1 (en) * | 2005-06-30 | 2007-02-27 | 주식회사 하이닉스반도체 | Method for fabricating metal interconnect in semiconductor device |
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