JPS6251243A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device including multilayer interocnnections, which can prevent yield of hillocks effectively, by forming a first interlayer insulating film, flattening the film, and forming a second interlayer insulating film at two steps in a temperature range, in which hillocks are not yielded, and a high temperature range thereafter. CONSTITUTION:A first wiring layer 2 is formed on a semiconductor substrate 1 aftet the formation of elements thereon in a specified pattern. A first layer interlayer insulating film 4 is formed on the layer 2. Then, the interlayer insulat ing film 4 is flattened. A second interlayer insulating film is formed at two steps in a temperature range, in which hillocks are not yielded, and a high temperature range thereafer. For example, the silicon oxide film 4 and a silicon nitride film 5 are formed. Etch back is performed by an RIE method, and the flattened silicon oxide film 4'' is obtained. A silicon oxide film 11 is formed thereon to a thickness of about 3,000Angstrom in a temperature range of 200-250 deg.C by using a plasma CVD method. A silicon oxide film 12 is formed thereon similarly at a temperature of about 300 deg.C by the plasma CVD method. The total thickness of about 1.5mum is obtained. A second aluminum wiring layer 13 is formed thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to the formation of an interlayer insulating film.

[Technical background of the invention and its problems]

As semiconductor devices become more highly integrated, a single layer of wiring after element formation is no longer sufficient, and multilayer wiring is usually used.

This multilayer wiring is shown in the cross-sectional diagram of each step of the device in
First, after forming the semiconductor substrate 1, a first layer of aluminum wiring layer 2 is formed by patterning by vapor deposition and etching of aluminum, and around it, a layer of 200~
A silicon oxide film 3 with a thickness of approximately 3000 wafers is formed by plasma CVD at a relatively low temperature of 250°C (see Fig. 2(a)).
)).

Next, apply the plasma CVD method on top of this at about 300°C.
A silicon oxide film 1 is formed at a temperature of about 1 μm including the previously formed silicon oxide film 3 (FIG. 2(b)).

Next, on top of this is a silicon nitride film (S i3 N4) 5
A silicon oxide film 4' is formed by the CVD method (Fig. 2 (C)), and then roughly etched back by reactive ion etching (RTE) to obtain a flat silicon oxide film 4' (Fig. 2 (C)). (d)).

Next, a silicon oxide film 6 is formed again by the plasma CVD method, and an upper second wiring layer 7 is formed thereon by aluminum thermal bonding and patterning by photoetching (FIG. 2(e)).

The reason why the silicon oxide film of the first wiring 1'' is formed in two steps is to prevent rain from hillocks.

That is, after forming an aluminum wiring layer, a silicon oxide film for interlayer insulation was conventionally used.
When formed at a relatively high temperature of around °C, stress concentration occurs on the surface due to crystal rearrangement of aluminum and protrusions called hillocks are generated. When the film is grown to a width of 4 and reaches the aluminum wiring layer 7 formed in the upper layer, a show 1- is generated and the yield is reduced, and even if the film does not reach the show 1-, the reliability is reduced.

In order to suppress the occurrence of stress, it is possible to lower the formation temperature of the interlayer insulating film so that stress concentration does not occur. There is a problem that the coverage deteriorates, leading to disconnection when the upper second aluminum wiring layer is formed, and the interlayer insulating film formed with a low tMA has poor film quality, resulting in decreased insulation and etching failure. This results in defects such as uniformity.

Another method for suppressing the occurrence of hillocks is to form a high melting point metal such as titanium or a high melting point metal silicide such as Ti3i on the surface of the aluminum layer. However, with this method, the process of forming a high melting point metal layer increases, etching is difficult, and since there is no high melting point metal on the side surface of the aluminum wiring, hillocks may grow on the side surface. It is not effective to meet the requirements of "miniaturization".

From this point of view, the first method mentioned above is adopted, but this method also has its problems.

That is, when the silicon oxide film 4 formed on the first aluminum wiring layer is planarized, the thickness of the silicon oxide film 4 is thinner than the expected thickness, or when there is too much etching by RIE. As shown in FIG. 4, the surface of the aluminum wiring layer 2 may be exposed. If a second silicon oxide film is formed in this state under normal relatively high temperature conditions, the state shown in FIG. 3 will occur, and hillocks 8 will occur.

[Purpose of the invention]

The present invention has been made to solve this problem, and it is an object of the present invention to provide a method for manufacturing a semiconductor device including multilayer wiring, which can effectively prevent the occurrence of hillocks.

[Summary of the invention]

In order to achieve the above object, the present invention provides J: first step after device formation.
After forming a first interlayer insulating film thereon and performing a flattening process by edge back, the second interlayer insulating film is heated in a temperature range where hillocks do not occur and then at a higher temperature. The wiring layer is formed in two stages within the rti range, and a second wiring layer is further formed thereon. By forming the second interlayer insulating film on this in two steps,
Even if the surface of the first wiring layer is exposed during etchback, hillocks can be effectively prevented from occurring.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a step-by-step sectional view illustrating a method for manufacturing a semiconductor device according to the present invention, and shows how multilayer wiring is formed on a semiconductor substrate 1 after device formation.

This method is the same as the conventional method up to the edge back step. That is, the first
An aluminum wiring layer 2 is formed around the aluminum wiring layer 2 with a thickness of approximately 3.
A silicon oxide film 3 on the surface of 000 is formed by plasma CVD in a temperature range of 200 to 250°C (Fig. 1(a)).
. On top of that, a silicon oxide film 4 is formed by plasma CVD at a temperature of about 300° C. to a total thickness of about 1 μm (Fig. 1(b)), and a silicon nitride film 5 is further formed by CVD. (Figure 1 (C)).

When edge-back is performed by the RIE method, a flat 1D silicon oxide film 4'' is obtained (Fig. 1(d)).At this time, there is usually a silicon oxide film on the surface of the first layer of aluminum interconnection layer. However, in extreme cases, the surface of the first aluminum wiring layer 2 may be damaged due to insufficient thickness of the silicon/oxide film 4 formed or excessive amount of etching by RIE. Fully exposed.

The following is an explanation of the situation.

A silicon oxide film 11 is formed thereon to a thickness of about 3,000 mm using a plasma CVD method at a temperature range of 200 to 250 DEG C. (FIG. 1(e)).

Next, approximately 30% of
A silicon oxide film 12 is formed at a temperature of 0° C. to a total thickness of 1.5 μm including the previously formed silicon oxide film 11, and a second aluminum film is formed on it by vapor deposition and patterning of aluminum. A wiring layer 13 is formed.

When forming the silicon oxide film again after this etch-back, the film is first formed at a relatively low humidity where hillocks are less likely to occur, and then at a higher temperature to form a thicker layer. Even when the surface of the aluminum wiring No. 1 is exposed, hillocks are less likely to occur.

In the above embodiments, when forming a silicon oxide film, the temperature range is switched between the initial stage and the subsequent stage, but the temperature rise curve is selected so that the film thickness as described above can be obtained. Continuous temperature changes may also be performed.

In addition, in the edge back process, although a silicon nitride film is used in the embodiment, the RIE film is not limited to this.
For example, a resist or the like can be used as long as it can be etched at the same etching rate as the oxide film.

Note that the temperature change described above is a change within the same process, and there is no substantial increase in the number of processes.

〔Effect of the invention〕

As described above, according to the present invention, the interlayer insulating film formed after the planarization treatment of the interlayer insulating film is formed in two stages: the temperature range where no sagging occurs and the subsequent higher temperature rQ range. Since the upper wiring layer is provided on top, even if the lower wiring layer is exposed during the planarization process, the formation of hillocks can be prevented and an interlayer insulating film with good film quality can be obtained, improving yield and reliability. A high multilayer wiring structure can be obtained.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of each step showing an embodiment of the present invention, Fig. 2 is a cross-sectional view of each step of a conventional method, and Figs.
The figure is a diagram explaining the problems of the conventional method. 1...Substrate, 2,7...Aluminum wiring layer, 3゜6.11...Oxide film formed at low temperature, 4.6゜12
...An oxide film formed at high temperatures.

Claims (1)

[Claims] 1. A step of forming a first wiring layer in a predetermined pattern on a semiconductor substrate after forming an element, and a step of forming a first interlayer insulating film on the first wiring layer. , a step of flattening the interlayer insulating film, and a step of forming a second interlayer insulating film thereon in two stages: in a temperature range where hillocks do not occur and then in a higher temperature range. Method of manufacturing the device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is a silicon oxide film. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the interlayer insulating film is formed by plasma CVD. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the first interlayer insulating film is formed in two steps: a temperature range in which hillocks do not occur and a subsequent temperature range at a higher temperature. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the planarization process is performed by etch-back using reactive ion etching. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second wiring layers are patterned aluminum layers. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the formation of the second interlayer insulating film is performed under continuous temperature rise.