JPH0817928A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make the thickness of an organic SOG film constant by using a second insulating film having a recessed part as a mask, forming a wiring continuity part, and ashing and eliminating a photoresist film forming the recessed part before the organic SOG film is exposed. CONSTITUTION:On a semiconductor substrate 1, aluminum wirings 2a, 2b of a first wiring layer are formed, and thereon a silicon oxide film 3 as a first insulating film, an organic SOG film 4, and a silicon oxide film 5 as a second insulating film are formed in order. Photoresist 6 is used as a mask, and a recessed part 8 which does not reach the organic SOG film 4 is formed in the silicon oxide film 5 by anisotropic etching. The photoresist is eliminated by ashing, and the silicon oxide film 5 having a recessed part 8 is used as a mask. By anisotropic dry etching, a wiring continuity part 9 is formed. Thereby the thickness of the organic SOG film 4 can be made constant, and the load in the case of designing a substratum pattern can be remarkably reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and is particularly suitable for manufacturing a semiconductor device having an organic SOG film as an interlayer insulating film or the like.

[0002]

2. Description of the Related Art In recent years, with the high integration of semiconductor devices,
From the viewpoint of maintaining the reliability of wiring, it is becoming important to flatten the surface. As this flattening technique, especially when flattening a wiring having a relatively low melting point such as aluminum wiring, a silicon compound such as silanol (H _n Si (OH) _4-n ) and an additive are used as an organic solvent. A so-called SOG (Spin On Glass) method is used in which a dissolved SOG solution is spin-coated on a wafer and heat-treated at a low temperature to form a film (SOG film) containing silicon dioxide as a main component. As described above, an inorganic material such as silanol has been used as a raw material source of the SOG solution, but an SOG film (inorganic SOG film) formed by using the inorganic material has poor crack resistance, and therefore a thick film is formed. Therefore, it is not suitable for sufficient flattening. In addition, inorganic SO
The G film causes a strong heat shrinkage stress during annealing, and thus has a problem of reducing the reliability of the wiring.

[0003] Therefore, using the substituted material part of silanol hydroxyl groups (-OH) in thermally stable alkyl (-C _n H _{2n + 1)} as a raw material source for SOG solution, organic S
Forming an OG film is beginning to be adopted. Organic SO
Since the G film has good crack resistance because the alkyl group is thermally stable and is suitable for thickening the film, it has characteristics that strong thermal contraction stress does not occur during annealing. It is more suitable for use in a planarization technique than an inorganic SOG film. An example of a method of manufacturing a semiconductor device using this organic SOG film as an interlayer insulating film for planarization will be described with reference to FIG.

First, as shown in FIG. 2A, aluminum wirings 102a and 102b are patterned on a semiconductor substrate 101. After that, a silicon oxide film 103 is formed on the entire surface.

Next, as shown in FIG. 2B, an organic SOG solution is spin-coated on the entire surface of the silicon oxide film 103,
The organic SOG film 104 is formed by annealing and baking. As a result, the substrate surface is considerably flattened.

Next, as shown in FIG. 2 (c), organic SO
The entire surface of the G film 104 is etched back. This is to suppress the phenomenon in which the organic SOG film 104 exposed in the wiring conducting portion 108 recedes during the ashing step shown in FIG.

Next, as shown in FIG. 2D, a silicon oxide film 105 is formed on the entire surface. Therefore, the organic SOG film 104 is sandwiched between the silicon oxide films 103 and 105 from above and below, and the aluminum wirings 102a and 102b and the aluminum wiring 109 formed later are prevented from directly contacting the organic SOG film 104.

Next, as shown in FIG. 2E, a photoresist 106 is applied to the entire surface, and then aluminum wiring 102a is formed.
The upper photoresist 106 is removed by photolithography to form a conductive pattern 107.

Next, as shown in FIG. 2F, isotropic wet etching is performed using the photoresist 106 as a mask to remove the region corresponding to the conductive pattern 107 and the upper portion of the silicon oxide film 105 in the vicinity thereof. Then, a part of the wiring conducting portion 108 is formed. As a result, the upper portion of the silicon oxide film 105 is etched with an inclination,
Upper layer wiring 109 formed in a later step (see FIG. 2I)
It is possible to improve the step coverage of (step coverage).

Next, as shown in FIG. 2G, anisotropic dry etching is performed using the photoresist 106 as a mask to form the organic SOG film under the silicon oxide film 105 in the region corresponding to the conductive pattern 107. 104 and the silicon oxide film 103 are removed to form a wiring conducting portion 108 which is an opening reaching the aluminum wiring 102a.

Next, as shown in FIG. 2H, an ashing process is performed to remove the photoresist 106. At this time, the organic SOG film 104 is also etched, and the recessed portion 1
04a is formed.

Next, as shown in FIG. 2I, an upper wiring 109 is formed of a metal such as aluminum so as to be connected to the aluminum wiring 102a exposed at the bottom of the wiring conducting portion 108.

[0013]

However, in manufacturing a semiconductor device having an organic SOG film as an interlayer insulating film by the above method, the following problems have occurred. That is, since a large amount of organic component remains in the organic SOG film 104, the organic SOG film 1 is formed in the wiring conducting portion 108.
When 04 is exposed, the organic SOG film 104 recedes at the same time when the photoresist 106 is ashed, and the receding portion 10
4a is formed. Then, when the organic SOG film 104 recedes, the step coverage of the upper layer wiring 109 decreases, and the upper layer wiring 109 recedes 10 as shown in FIG. 2I, for example.
Since the wire breaks at 4a, the reliability of the wiring is significantly reduced.

Therefore, in the method described above, in the step shown in FIG. 2C, the organic SOG film exposed on the wiring conducting portion 108 is reduced or removed by etching back the entire surface of the organic SOG film 104. Photoresist 10
The phenomenon that the organic SOG film 104 recedes when performing the ashing of No. 6 was suppressed as much as possible. However, in reality, the film thickness of the organic SOG film 104 depends on the underlying pattern of the aluminum wiring 102 and the like, and varies depending on the location. Therefore, the thickness of the exposed organic SOG film 104 is set to be equal to that of all the wiring conducting portions 10.
In order to sufficiently reduce or remove the organic SOG film 8 at 8, the organic SOG film 104 should be formed at all positions where the wiring conducting portion 108 is formed.
It is necessary to devise the design rule of the underlying pattern so that the film thicknesses of the two are almost the same, and there is a problem that the constraint on the design rule becomes large.

Therefore, it is an object of the present invention to provide a method of manufacturing a semiconductor device having an organic SOG film, in which the organic SOG film does not recede in a wiring conduction portion when manufacturing the semiconductor device.

[0016]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first wiring layer on a semiconductor substrate, and thereafter a first wiring layer over the entire surface.
Step of sequentially forming an insulating film, an organic SOG film, and a second insulating film, and etching is performed by using the photoresist film having the conductive pattern of the first wiring layer as a mask to form a recess in the second insulating film. A step of removing the photoresist film by ashing, and etching the entire surface using the second insulating film having the concave portion as a mask to form the second insulating film in the concave portion,
A step of penetrating the organic SOG film and the first insulating film to form a wiring conducting portion reaching the first wiring layer;
And a step of forming a second wiring layer connected to the first wiring layer while covering at least the inner surface of the wiring conduction portion.

[0017]

Since the wiring conductive portion is formed by etching using the second insulating film having the concave portion as a mask, the photoresist film for forming the concave portion can be removed by ashing before the organic SOG film is exposed. Yes, organic S
It is possible to form a wiring conduction portion in which the OG film does not recede.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. 1A to 1C are sectional views showing the manufacturing method of this embodiment in the order of steps.

First, as shown in FIG. 1A, aluminum wirings 2a and 2b having a film thickness of about 0.6 μm are patterned on a semiconductor substrate 1. Thereafter, a silicon oxide film 3 having a thickness of about 0.3 μm is formed on the entire surface by plasma CVD method, thermal CVD method or the like. Instead of aluminum wiring, aluminum alloy wiring in which silicon or copper is added may be formed in aluminum, and a barrier metal such as titanium, titanium nitride, or titanium tungsten, or a cap metal may be formed above or below either of them. It is also possible to use a composite wiring by using a composite wiring. A silicon nitride film may be used instead of the silicon oxide film 3.

Next, as shown in FIG. 1B, on the silicon oxide film 3, for example, "OCD T- manufactured by Tokyo Ohka Kogyo Co., Ltd."
7 1000-T ”(trade name) or the like, spin coated with an organic SOG solution, annealed and baked to a film thickness of 0.3 μm.
The organic SOG film 4 having a certain degree is formed. This significantly flattens the wafer surface. At this time, although the etch back of the organic SOG film 4 is not necessary, the etch back may be performed to adjust the overall film thickness.

Next, as shown in FIG. 1C, a silicon oxide film 5 having a thickness of about 1.2 μm is formed on the entire surface by plasma CVD.
Method or thermal CVD method. In this way, organic S
By sandwiching the OG film 4 between the silicon oxide films 3 and 5 from above and below, the organic SOG film 4 is made into aluminum wirings 2a and 2b.
Also, direct contact with an upper layer wiring 10 (see FIG. 1H) described later is prevented. This is because the organic SOG film 4 contains a large amount of impurities.
If it comes into direct contact with the aluminum wirings 2a, 2b, etc., it may cause a decrease in reliability of the aluminum wirings 2a, 2b, etc.

Next, as shown in FIG. 1D, a photoresist 6 is applied to the entire surface, and then the photoresist 6 on the aluminum wiring 2a is removed by photolithography to form a conductive pattern 7.

Next, as shown in FIG. 1 (e), anisotropic dry etching is performed using the photoresist 6 as a mask to form the silicon oxide film 5 in the region corresponding to the conductive pattern 7.
Is excavated to a depth of about 1.0 μm to form a recess 8.
That is, the etching of the silicon oxide film 5 is performed by the organic SOG.
It is finished before reaching the film 4, and the organic SOG film 4 is left covered with the silicon oxide film 5. At this time, as the etching conditions, a parallel plate type RF etcher is used,
The pressure is about 300 Pa, the RF output is about 400 W, and the CF ₄ flow rate is about 100 sccm. In addition to CF ₄ gas, fluorocarbon (C _x H
may be mixed with _y F _z) based gas or the like. Before performing this step, as described in FIG. 2F, isotropic wet etching is performed with buffered hydrofluoric acid or the like to form a region above the silicon oxide film 5 in the region corresponding to the conductive pattern 7 and in the vicinity thereof. By removing the portion, the step coverage of the upper layer wiring 10 (see FIG. 1H) formed in a later step may be improved.

Next, as shown in FIG. 1F, an ashing process is performed to remove the photoresist 6. This time,
Since the organic SOG film 4 is covered with the silicon oxide film 5, the organic SOG film 4 is not etched.

Next, as shown in FIG. 1G, the entire surface is anisotropically dry-etched by CF ₄ gas to a thickness of about 0.6 μm using the silicon oxide film 5 having a recess 8 which is opened halfway as a mask. By this etching, the silicon oxide film 5, the organic SOG film 4, and the silicon oxide film 3 in the recess 8 are formed.
Is removed to form the wiring conducting portion 9, and the silicon oxide film 5 other than the concave portion 8 is removed by about 0.6 μm.
At this time, the etching conditions are a parallel plate type RF etcher, a pressure of about 300 Pa, and an RF output of 400 W.
The CF ₄ flow rate is about 100 sccm. Incidentally, the anisotropic dry etching, in place of CF ₄ gas, may be used fluorocarbon (C _x H _y F _z) based gas such as alone or in combination. In addition, since the upper corner of the silicon oxide film 5 is chamfered by this step, the isotropic etching step for improving the step coverage as described in FIG. 2F or 1E is performed. You don't have to.

Next, as shown in FIG. 1H, an upper layer wiring 10 of about 1.0 μm thick made of metal such as aluminum is connected to the aluminum wiring 2a exposed at the bottom of the wiring conducting portion 8. To form. Also in this case, the aluminum wiring 2a, 2b
As in the case of 1, the aluminum alloy wiring in which silicon or copper is added may be formed in aluminum, and barrier metal such as titanium, titanium nitride, or titanium tungsten may be formed above or below or either of them alone or in combination. Can also be used as a composite wiring.

As described above, in this embodiment, since the organic SOG film 4 does not recede, the step coverage of the upper layer wiring 10 does not decrease when the upper layer wiring 10 is formed, and the reliability of the upper layer wiring 10 is reduced. Significantly improved.

[0028]

According to the present invention, since the wiring conductive portion is formed by etching using the insulating film having the concave portion as a mask, the photoresist film is removed by ashing while the organic SOG film is covered with the insulating film. When forming the wiring layer, the step coverage of the wiring layer does not decrease due to the receding of the organic SOG film. Therefore, there is no restriction on the design rule of the underlying pattern that devises the design rule of the underlying pattern so that the film thickness of the organic SOG film is constant, and the burden at the time of design is greatly reduced. Further, in order to reduce the receding of the organic SOG film when the photoresist film is removed by ashing, the entire surface of the organic SOG film is etched back to remove the organic SOG film.
It is not necessary to sufficiently reduce or remove the OG film, and the number of steps in manufacturing a semiconductor device can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device in the order of steps.

[Explanation of symbols]

 1 Semiconductor Substrate 2a, 2b Aluminum Wiring 3, 5, 9 Silicon Oxide Film 4 Organic SOG Film 6 Photoresist 7 Conduction Pattern 8 Recess 9 Wiring Conduction 10 Upper Layer Wiring

Claims (1)

[Claims] 1. A step of forming a first wiring layer on a semiconductor substrate, after which a first insulating film, an organic SOG film and a second film are formed on the entire surface.
The step of sequentially forming an insulating film, the step of forming a recess in the second insulating film by etching using the photoresist film having the conduction pattern of the first wiring layer as a mask, and the photoresist film By ashing, and by etching the entire surface using the second insulating film having the recess as a mask, the second portion in the recess is removed.
Forming a wiring conducting portion reaching the first wiring layer by penetrating the insulating film, the organic SOG film and the first insulating film, and at least covering an inner surface of the wiring conducting portion and And a step of forming a second wiring layer connected to the wiring layer.