JPH04123458A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the productivity of a semiconductor device by etching a layer composed of a flat film and a first insulating film until the top of a conductor column is exposed, resulting in fewer steps. CONSTITUTION:A second insulating film 67 is formed on a first aluminum wiring layer 65 of a silicon substrate 61 and etched selectively to open a contact hole 71. A third aluminum wiring layer is formed on the second insulating film 67 and etched selectively to form a conductor column 77. A first insulating film 79 is formed on the surface of this structure, and positive resist 81 is applied in such a manner that a flat top surface is obtained. The resist and the first insulating film etched until the top of the conductor column 77 is exposed. A second aluminum wiring layer 83 is formed overall on the surface and etched into an interconnection.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of connecting lower layer wiring and upper layer wiring.

[Prior art] An example of the conventional method of connecting lower layer wiring and upper layer wiring is shown in the second example.
This will be explained using Figures A to 2G.

As shown in FIG. 2A, a silicon substrate 1 is prepared.

As shown in FIG. 2B, a silicon oxide film 3, a first aluminum wiring layer 5,
Interlayer insulating film 7 made of silicon oxide film, photoresist 9
form.

As shown in FIG. 2C, the photoresist 9 is patterned in a predetermined manner.

As shown in FIG. 2D, isotropic etching is performed on the interlayer insulating film 7 using the photoresist 9 as a mask. When the interlayer insulating film 7 has been etched to a predetermined depth, the etching is stopped.

As shown in FIG. 2E, using the photoresist 9 as a mask, the interlayer insulating film 7 is anisotropically etched to complete the contact hole 11.

As shown in FIG. 2F, the photoresist 9 is removed. Then, a second aluminum wiring layer 13 is formed over the entire main surface of the silicon substrate 1.

As shown in FIG. 2G, the second aluminum wiring layer 13 is patterned in a predetermined manner.

A portion of the second aluminum wiring layer 13 on the interlayer insulating film 7 is an upper layer wiring. The first aluminum wiring layer 5 is the lower layer wiring.

As shown in FIG. 2G, the upper part of the side wall of the contact hole 11 is oblique. This is to improve adhesion of the second aluminum wiring layer 13 to the side wall of the contact hole 11.

By the way, when the aspect ratio of the contact hole (depth of the contact hole/lateral dimension of the contact hole) becomes high, there is a possibility that the connection between the upper layer wiring and the lower layer wiring becomes poor. This will be explained using FIGS. 3 and 4.

FIG. 3 is a cross-sectional view showing a connecting portion between an upper layer wiring and a lower layer wiring when the aspect ratio is 1 or less. The dimension indicated by A is the lateral dimension of the contact hole. The dimension indicated by B is the depth of the contact hole. When the aspect ratio is 1 or less, the electrical connection between the second aluminum wiring layer 13, which is the upper layer wiring, and the first aluminum wiring layer 5, which is the lower layer wiring, is well established. However, when the aspect ratio is larger than 1, as shown in FIG. 4, the electrical connection between the second aluminum wiring layer 13, which is the upper layer wiring, and the first aluminum wiring layer 5, which is the lower layer wiring, cannot be made well. Sometimes. This means that before the bottom of the contact hole 11 is clogged with aluminum, the contact hole 11
This is because the mouth of the contact hole 11 is closed by the aluminum deposited on the upper side wall of the contact hole 11.

As semiconductor devices become more highly integrated, the lateral dimensions of contact holes are becoming smaller. On the other hand, the thickness of the interlayer insulating film cannot be less than a predetermined value in consideration of the risk of pinholes.

For this reason, the aspect ratio tends to increase.

As a method for ensuring electrical connection between the upper layer wiring and the lower layer wiring even when the aspect ratio increases, there is a method in which the electrical connection between the upper layer wiring and the lower layer wiring is made using metal formed by selective CVD. This method will be explained using FIGS. 5A to 5G.

As shown in FIG. 5A, a silicon substrate 15 is prepared.

As shown in FIG. 5B, a silicon oxide film 17, a first aluminum wiring layer 19, an interlayer insulating film 21 made of a silicon oxide film, and a photoresist 23 are formed in this order over the entire main surface of the silicon substrate 15.

As shown in FIG. 5C, the photoresist 23 is patterned in a predetermined manner.

As shown in FIG. 5D, anisotropic etching is performed on the interlayer insulating film 21 using the photoresist 23 as a mask to form a contact hole 25.

As shown in Figure 5E, CVD (Chemical
Tungsten 27 is selectively formed in the contact hole 25 by a vapor deposition method. The reason why tungsten 27 is selectively formed only in the contact hole 25 is because the raw material gas containing tungsten reacts with aluminum and is less likely to react with the silicon oxide film. Since the source gas containing tungsten and the silicon oxide film do not react at all, a thin film made of tungsten 27 is formed on the main surface of the interlayer insulating film 21.

As shown in FIG. 5F, the ringsten 27 on the interlayer insulating film 21 is removed by etching.

As shown in FIG. 5G, a second aluminum wiring layer 29 is formed on the interlayer insulating film 21. Then, as shown in FIG. Then, the second aluminum wiring layer 29 is patterned in a predetermined manner.

For example, documents disclosing selective CVD methods include:
IEEE June 13-14. 1988
There are p125 to p134.

However, the selective CVD method is still in the research stage and has not yet reached the stage of producing semiconductor devices using the selective CVD method.

As something that can solve the problems of the above two examples,
There is a method disclosed in Japanese Unexamined Patent Publication No. 116834/1983. This method will be explained using FIGS. 6A to 6F.

As shown in FIG. 6A, field oxide films 33 are formed on both ends of the main surface of the substrate 31. As shown in FIG. Near the main surface of substrate 31 sandwiched between field oxide films 33, a source region 37 and a drain region 39 are formed with a gap therebetween. An insulating film 43 is formed on the main surface of substrate 31 between source region 37 and drain region 39 . A gate electrode 41 is formed on the insulating film 43.

On one field oxide film 33, a polysilicon layer 3
5 is formed. A buffer oxide layer 45 is formed over the entire main surface of the substrate 31 . Polysilicon layer 3
A contact hole 47a is formed in the buffer oxide layer 45 overlying the contact hole 47a. A contact hole 47b is formed in the buffer oxide layer 45 overlying the source region 37. A contact hole 47c is formed in the buffer oxide layer 45 overlying the drain region 39.

As shown in FIG. 6B, a first
An aluminum wiring layer 49 is formed. A photoresist 51 is formed on the first aluminum wiring layer 49.

As shown in FIG. 6C, the photoresist 51 is patterned in a predetermined manner. Using the photoresist 51 as a mask, the first aluminum wiring layer 49 is selectively etched away to form conductive pillars 53a153b.

Form 53c.

As shown in FIG. 6D, phosphor glass 55 and resist 57 are formed in this order over the entire main surface of substrate 31.

As shown in the sixth EIK, the resist 57 is ashed. Ashing are conductive pillars 53a and 53b.

This process is continued until the phosphor glass 55 on 53c is exposed.

Then, using the resist 57 as a mask, the interlayer insulating film 55a on the conductive pillar 53a and the interlayer insulating film 55a on the conductive pillar 53b are
The interlayer insulating film 55c on the b1 conductive pillar 53c is selectively etched away. After that, the remaining resist 57 is removed.

As shown in FIG. 6F, a second layer is formed on the entire main surface of the substrate 31.
An aluminum wiring layer 59 is formed. Then, the second aluminum wiring layer 59 is patterned in a predetermined manner.

As shown in FIG. 6C, by changing the lateral dimension of the resist 51 serving as a mask, the conductive pillars 53 a, 5
The lateral dimensions of 3b and 53c can be adjusted freely. For this reason, even if semiconductor devices become highly integrated,
Electrical connection between the upper layer wiring and the lower layer wiring can be established reliably.

Further, since the electrical connection between the upper layer wiring and the lower layer wiring is made using general-purpose technology, it is possible to immediately produce semiconductor devices.

[Problems to be Solved by the Invention] There are also problems with the method disclosed in Japanese Patent Application Laid-open No. 116834/1983. This will be explained below. As shown in FIG. 6E, the conductive pillar 53 a N
The head of 53 b s 53 c is exposed.

■ Interlayer insulating film 55a1 on conductive column 53a, conductive column 53b
Upper interlayer insulating film 55b1 Interlayer insulating film 5 on conductive pillar 53c
Ashing is performed on the resist 57 until 5c is exposed.

■ Using the resist 57 as a mask, the interlayer insulating film 55a,
55b and 55c are removed by etching, and the conductive pillar 53a is removed.
Expose the head of s 53 b s 53 c.

■Remove the remaining resist 57.

In this method, the head of the conductive column 53 a N 53 b % 53 c is exposed through three steps. Therefore, it takes time and effort to electrically connect the upper layer wiring and the lower layer wiring.

This invention was made to solve these conventional problems. An object of the present invention is to provide a method that allows easy electrical connection between lower layer wiring and upper layer wiring.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes a step of forming a second interlayer insulating film on a first conductive layer, and selectively etching away the second interlayer insulating film. a step of forming a contact hole and exposing a part of the first conductive layer; a step of forming a third conductive layer on the second interlayer insulating film including the exposed first conductive layer; A step of selectively etching away the third conductive layer to form a conductive pillar made of the third conductive layer electrically connected to the first conductive layer over the contact hole, and removing the second interlayer insulating film including the conductive pillar. a step of forming a first interlayer insulating film on the first interlayer insulating film; a step of forming a planarizing film on the first interlayer insulating film whose surface after formation is flatter than the surface of the first interlayer insulating film; and a step of forming a planarizing film on the first interlayer insulating film. and a step of etching back the layer consisting of the first interlayer insulating film to expose the head of the conductive pillar, and forming a second conductive layer electrically connected to the conductive pillar on the exposed head of the conductive pillar. It has a process of

[Operation] In the method for manufacturing a semiconductor device according to the present invention, the layer consisting of the planarizing film and the first interlayer insulating film is etched back to expose the head of the conductive pillar. Therefore, compared to the method disclosed in Japanese Patent Application Laid-open No. 116834/1983, in which the interlayer insulating film on the conductive column is removed using a resist as a mask to expose the head of the conductive column, the present invention requires fewer steps. The head of the conductive pole can be exposed.

[Example] An example of the method for manufacturing a semiconductor device according to the present invention is as follows.
This will be explained using FIGS. 1A to 1K.

As shown in FIG. 1A, a silicon substrate 61 was prepared.

As shown in FIG. 1B, a silicon oxide film 63 was formed over the entire main surface of a silicon substrate 61 by CVD. A first aluminum wiring layer 65 was formed on the silicon oxide film 63 by sputtering. A thin TE01 (tetrae
A second interlayer insulating film 67 made of a (thyl orthosilicate) film was formed. The reason why the TE01 film was used is that the film can be formed at a temperature below the melting point of aluminum, and deterioration of the first aluminum wiring layer 65 can be prevented.

A photoresist 69 was formed on the second interlayer insulating film 67. Then, the photoresist 69 was patterned in a predetermined manner.

As shown in FIG. 1C, using the photoresist 69 as a mask, the second interlayer insulating film 67 is selectively removed by etching.
A contact hole 71 was formed.

Then, the photoresist 69 was removed.

As shown in FIG. 1D, a third aluminum wiring layer 73 was formed on the second interlayer insulating film 67 by sputtering.

As shown in FIG. 1E, a photoresist 75 was formed on the third aluminum wiring layer 73 and patterned in a predetermined manner.

As shown in FIG. 1F, the third aluminum wiring layer 73 was selectively etched away using the photoresist 5 as a mask to form conductive pillars 77.

As shown in FIG. 1G, the photoresist 5 on the conductive pillar 77 was removed.

As shown in FIG. 1H, a first interlayer insulating film 79 made of a TEOS film was formed over the entire main surface of the silicon substrate 61. The reason why the first interlayer insulating film 79 is made of TE01 film is that
This is the same as the case of the interlayer insulating film 67. Then, a positive resist 81 was formed over the entire main surface of the silicon substrate 61. The surface of the positive resist 81 was made to be flatter than the surface of the first interlayer insulating film 79. This is because if the surface of the positive resist 81 is not flatter than the surface of the first interlayer insulating film 79, the first aluminum wiring layer 65 may be exposed before the conductive pillars 77 are exposed. In order to make the surface of the positive resist 81 flatter than the surface of the first interlayer insulating film 79, a positive resist 81 having a lower viscosity than the first interlayer insulating film 79 is used.
I set it to 1.

As shown in FIG. 1I, a layer consisting of the positive resist 81 and the first interlayer insulating film 79 is coated using a mixed gas consisting of SF6 gas, CH2F2 gas and C12 gas until the top of the conductive column 77 is exposed. I had sex back. The gas flow rate ratio is as follows.

SF6 :CH2F2 :Cl2 =1:0. 6:0. 7 Then, the positive resist 81 remaining on the first interlayer insulating film 79 was removed.

As shown in FIG. 1J, a second aluminum wiring layer 83 was formed over the entire main surface of the silicon substrate 61 by sputtering. On the second aluminum wiring layer 83,
A photoresist 85 was formed and predetermined patterning was performed.

As shown in FIG. 1K, the second aluminum wiring layer 83 was selectively etched away using the photoresist 85 as a mask. Then, the photoresist 85 on the second aluminum wiring layer 83 was removed.

With the above, one embodiment of the method for manufacturing a semiconductor device according to the present invention has been completed.

The thickness of the second interlayer insulating film 67 shown in FIG. 1K is 1000 mm.
A or higher is preferable. The thickness of the second interlayer insulating film 67 is 10
This is because if the number is smaller than 00, pinholes may occur in the second interlayer insulating film 67.

The aspect ratio of the contact hole 71 shown in FIG. 1K is preferably 1 or less. contact hole 71
This is because if the aspect ratio is larger than 1, a connection failure may occur between the conductive pillar 77 and the first aluminum wiring layer 65. Conductive pillar 77 and first aluminum wiring layer 6
The reason why connection failure occurs with 5 is the same as the reason stated on page 5.

It is preferable that the conductive column 77 is formed so that the side wall 78 of the conductive column 77 shown in FIG. 1K is located on the second interlayer insulating film 67. This is because the conductive column 77 is formed so that the side wall 78 of the conductive column 77 does not rest on the second interlayer insulating film 67.
This is because, as shown in FIG. 1L, a portion of the first aluminum wiring layer 65 is eroded by etching. The eroded portion is represented by an eroded portion 87.

In this embodiment, as shown in FIG. 1K, the material of the upper layer wiring, lower layer wiring and conductive pillars is aluminum. However, the present invention is not limited to this, and other conductive members (for example, polysilicon) may be used.

A TE01 film is used for the second interlayer insulating film 67 and the first interlayer insulating film 79 shown in FIG. 1K.

However, the present invention is not limited to this, and any film may be used as long as it can be formed at a temperature below the melting point of aluminum.

For example, there are a plasma nitride film, a plasma oxide film, a spin-on glass film, and the like.

[Effects] In the method for manufacturing a semiconductor device according to the present invention, the layer consisting of the planarization film and the first interlayer insulating film is etched back to expose the head of the conductive pillar. Therefore, the head of the conductive column can be exposed in fewer steps than in the conventional method.

Therefore, according to the method of manufacturing a semiconductor device according to the present invention, the productivity of semiconductor devices can be improved.

[Brief explanation of the drawing]

FIGS. 1A to 1K are cross-sectional views showing step-by-step an embodiment of a method for manufacturing a semiconductor device according to the present invention. FIG. 1L is a cross-sectional view showing a state in which a portion of the aluminum wiring is eroded. FIGS. 2A to 2G are cross-sectional views showing an example of a conventional method for connecting lower layer wiring and upper layer wiring in order of steps. FIG. 3 is a cross-sectional view showing a connecting portion between an upper layer wiring and a lower layer wiring when the aspect ratio is 1 or less. FIG. 4 is a cross-sectional view showing a connection between an upper layer wiring and a lower layer wiring when the aspect ratio is greater than 1. FIGS. 5A to 5G are cross-sectional views showing another example of the conventional method of connecting lower layer wiring and upper layer wiring in order of steps. FIGS. 6A to 6F are cross-sectional views showing the method disclosed in Japanese Patent Application Laid-Open No. 61-116834 in order of steps. In the figure, 65 is a first aluminum wiring layer, 67 is a second interlayer insulating film, 71 is a contact hole, 73 is a third aluminum wiring layer, 77 is a conductive column, 79 is a first interlayer insulating film, 81 is a positive resist, Reference numeral 83 indicates a second aluminum wiring layer.

Claims (1)

Claims: A first conductive layer, a first interlayer insulating film formed on the first conductive layer, and a first conductive layer formed on the first interlayer insulating film and electrically connected to the first conductive layer. a second conductive layer connected to the semiconductor device, the method comprising: forming a second interlayer insulating film on the first conductive layer; and selectively forming the second interlayer insulating film. forming a contact hole by etching away and exposing a part of the first conductive layer; and forming a third conductive layer on the second interlayer insulating film, including the exposed first conductive layer. and selectively etching and removing the third conductive layer, and forming a layer on the contact hole.
forming a conductive pillar made of the third conductive layer electrically connected to the first conductive layer; and depositing the first interlayer insulating film on the second interlayer insulating film, including the conductive pillar. forming a planarizing film on the first interlayer insulating film, the surface of which after formation is flatter than the surface of the first interlayer insulating film; and the planarizing film and the first interlayer insulating film. etching back a layer consisting of a film to expose the head of the conductive column; and forming the second conductive layer electrically connected to the conductive column on the exposed head of the conductive column. A method for manufacturing a semiconductor device, comprising a process.