JPS60115234A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPS60115234A JPS60115234A JP22356883A JP22356883A JPS60115234A JP S60115234 A JPS60115234 A JP S60115234A JP 22356883 A JP22356883 A JP 22356883A JP 22356883 A JP22356883 A JP 22356883A JP S60115234 A JPS60115234 A JP S60115234A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- bias
- resist film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 8
- 239000012530 fluid Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 22
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 21
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052782 aluminium Inorganic materials 0.000 abstract description 12
- 238000001020 plasma etching Methods 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- SVONRAPFKPVNKG-UHFFFAOYSA-N 2-ethoxyethyl acetate Chemical compound CCOCCOC(C)=O SVONRAPFKPVNKG-UHFFFAOYSA-N 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 238000009499 grossing Methods 0.000 abstract 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 18
- 239000007789 gas Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000008267 milk Substances 0.000 description 2
- 210000004080 milk Anatomy 0.000 description 2
- 235000013336 milk Nutrition 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 206010041235 Snoring Diseases 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000790 scattering method Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に係り、特に半導体基
板上の細溝が形成された表面に平坦に絶縁膜を形成する
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an insulating film flat on a surface of a semiconductor substrate in which narrow grooves are formed.
半導体装置の多層配線、特にアルミニウム配線を用いた
多層配線構造においては、眉間絶縁膜を約５００℃以下
の温度で平坦に形成する必要がある。また、半導体集積
回路の高密度化に対して、配線の超微細化が必須である
。配線間の距離が約１．５μｍ以下となるデザインルー
ルにより表面に細溝が形成される場合、ＣＶＤ法により
形成した絶縁膜を平坦化する方法では、ＣＶＤ膜自身の
段差部での被覆性が悪いため、十分に細溝を埋込むこと
ができず平坦性が得られない。このため、絶縁膜を形成
しなから細溝を十分に埋込み、かつ平坦化できる特徴を
もつバイアスス・やツタ法により層間絶縁膜を形成する
必要があった。In a multilayer wiring structure of a semiconductor device, particularly in a multilayer wiring structure using aluminum wiring, it is necessary to form a flat glabella insulating film at a temperature of about 500° C. or lower. Further, ultra-fine wiring is essential for increasing the density of semiconductor integrated circuits. When thin grooves are formed on the surface due to a design rule in which the distance between wirings is approximately 1.5 μm or less, the method of flattening an insulating film formed by CVD method may result in poor coverage of the stepped portions of the CVD film itself. Because of this, the thin grooves cannot be filled sufficiently and flatness cannot be obtained. For this reason, it was necessary to form an interlayer insulating film by the bias or ivy method, which has the characteristics of sufficiently filling the narrow grooves and flattening the trenches without forming an insulating film.
しかしながら、このバイアススパッタ法にも問題がある
。第１図は、シリコン基板１１上に酸化シリコン膜１２
を形成し、このようにアルミニウム配線ｘｓ（ｘｓｌ
、１３．）を形成しり後、バイアススパッタ法により酸
化シ！Ｊ：７ン膜１４を形成して、この上に接続孔形成
用のレジストパターン１５を形成した状態を示している
。図のようにノ々イアス条件により、配線幅の狭い配線
１３１上の酸化シリコン膜１４は完全に平坦にできるが
、配線幅の広い配線１３．上の酸化シリコン酸１４はバ
イアス条件によらず傾斜部をもち、配線１３．の中央部
での酸化シリコン膜１４は配線１３．上に比べて厚く形
成される。このため、酸化シリコン膜１４に接続孔を設
ける際、配線１３１と１３．上ではエツチング時間が大
幅に異なり、素子製造の信頼性を低下させる。また、層
間絶縁膜は完全に平坦にならないため、後の工程での信
頼性も低下するという欠点があった。However, this bias sputtering method also has problems. FIG. 1 shows a silicon oxide film 12 on a silicon substrate 11.
In this way, the aluminum wiring xs (xsl
, 13. ) is formed, oxidation is performed using bias sputtering method. J: A state in which a 7-layer film 14 is formed and a resist pattern 15 for forming connection holes is formed thereon is shown. As shown in the figure, the silicon oxide film 14 on the narrow wiring 131 can be completely flattened under the noisy conditions, but the wide wiring 13. The upper silicon oxide 14 has a slope regardless of the bias conditions, and the wiring 13. The silicon oxide film 14 at the center of the wiring 13. It is thicker than the top. Therefore, when forming connection holes in the silicon oxide film 14, the wirings 131 and 13. The etching time differs significantly between the two, reducing the reliability of device fabrication. Furthermore, since the interlayer insulating film is not completely flat, there is a drawback that reliability in subsequent steps is also reduced.
本発明の目的は、細溝を有する表面に絶縁膜を完全に平
坦に形成でき、半導体装置の信頼性向上および配線層の
断線防止等を図り得る半導体装置の製造方法を提供する
ことにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that can form a completely flat insulating film on a surface having narrow grooves, improve reliability of the semiconductor device, and prevent disconnection of wiring layers.
上記目的を達成するための本発明の特徴は、基板表面の
細溝が完全に埋まるに必要な弱いバイアス条件下でバイ
アススパッタ法により絶縁膜を形成し、さらに従来の表
面平坦化技術を用いてバイアススツヤツタ法で形成され
た絶縁膜表面の凹凸をなくすようにしたことにある。To achieve the above object, the present invention is characterized by forming an insulating film by bias sputtering under weak bias conditions necessary to completely fill the narrow grooves on the substrate surface, and by using conventional surface planarization technology. The purpose is to eliminate unevenness on the surface of the insulating film formed by the bias scattering method.
本発明によれば、微小間隔をもって配線幅の異なる種々
の配線層が形成された半導体基板上にも絶縁膜を完全に
平坦に形成でき、絶縁膜に配線接続のだめの接続孔を設
ける際のエツチング時間が場所に依らず一定となるため
、素子製造の信頼性が大幅に向上する。特に本発明は、
半導体集積回路の高密度多層配線の眉間絶縁膜の形成に
極めて有効となる。According to the present invention, it is possible to form a completely flat insulating film even on a semiconductor substrate on which various wiring layers with different wiring widths are formed at minute intervals, and it is possible to form a completely flat insulating film even when forming connection holes for wiring connections in the insulating film. Since the time is constant regardless of location, the reliability of device manufacturing is greatly improved. In particular, the present invention
It is extremely effective for forming glabellar insulating films for high-density multilayer wiring in semiconductor integrated circuits.
第２図（ａ）から（ｄ）は本発明の第１の実施例を示す
工程断面図である。まず（ａ）に示す如く、素子形成さ
れたシリコン基板２１上に例えば酸化シリコン膜２２を
形成し、この酸化シリコン膜２２上に配線層として例え
ば膜厚０．８μｍのアルミニウム配線層２３（２３１，
２３，・・・）を形成する。アルミニウム配線層、２３
は、アルミニウム膜をスパッタ法等により形成した後、
マスクとして例えばホトレジストを塗布し、ノ母ターニ
ングを行な４い、そして、例えば、ＣＣ７４とＣｉ！と
の混合ガスを用いた反応性イオンエツチング法によりア
ルミニウム膜を選択エツチングして形成する。なお、配
線層２３．．２３．の幅は１．５μ乳、２３３の幅は２
３．．２３．に比べて十分に大きく（５〜１００μ乳）
、また配線間隔、即ち細溝の幅は１．５μｍである。FIGS. 2(a) to 2(d) are process cross-sectional views showing the first embodiment of the present invention. First, as shown in (a), for example, a silicon oxide film 22 is formed on a silicon substrate 21 on which elements are formed, and on this silicon oxide film 22, as a wiring layer, for example, an aluminum wiring layer 23 (231, 231,
23,...) are formed. Aluminum wiring layer, 23
After forming an aluminum film by sputtering method etc.,
For example, photoresist is applied as a mask, mother turning is performed, and then, for example, CC74 and Ci! The aluminum film is selectively etched using a reactive ion etching method using a gas mixture with the aluminum film. Note that the wiring layer 23. ．． 23. The width of is 1.5μ milk, the width of 233 is 2
3. ．． 23. (5-100μ milk)
, and the wiring interval, that is, the width of the narrow groove, is 1.5 μm.
次に、例えばスパッタ用ターゲットとして高純度石英ガ
ラス（ｓｔｏｗ）を用い、またスノｆツタリングガスと
して例えばアルゴン（Ａｒ）を用いたＲＦバイアススパ
ッタ法により、（ｂ）に示すようにアルミニウム配線層
２３上に酸化シリコン膜２４を厚さ約０．８μｍ形成す
る。／４イアススノ＋ツタ条件は、Ａｒ圧力を１０ ＠
Ｔｏｒｒ、ターゲットおよび基板側に発生する直流電
圧をそれぞれ一１２００Ｖ 、−１００Ｖとして、５０
分間スノクツタリングを行った。基板側に生じるノ々イ
アス電圧により膜生成と同時に逆ス／ＩＰツタ現象が起
こるため、膜の断面形状は図示のようになる。なお、こ
の基板バイアス条件では、酸化シリコン膜２４は、アル
ミニウム配線層間の細溝は完全に埋まるが、配線層２３
上の膜厚はいずれも０．８μ九となる。即ち細い配線層
２３□ 。Next, an RF bias sputtering method using, for example, high-purity quartz glass (stow) as a sputtering target and, for example, argon (Ar) as a snoring gas, is performed to form an aluminum wiring layer 23 as shown in (b). A silicon oxide film 24 with a thickness of about 0.8 μm is formed thereon. /4 Iasuno + ivy condition is Ar pressure 10 @
Torr, the DC voltages generated on the target and substrate sides are -1200V and -100V, respectively, and 50
Spent a minute snoktutting. Because the reverse voltage/IP ivy phenomenon occurs simultaneously with film formation due to the noisy voltage generated on the substrate side, the cross-sectional shape of the film becomes as shown in the figure. Note that under this substrate bias condition, the silicon oxide film 24 completely fills the narrow grooves between the aluminum wiring layers, but
The thickness of the upper layer is 0.8μ9 in both cases. That is, the thin wiring layer 23□.
２３、上でも平坦化はされず、細溝の段差部上に傾斜面
が残る状態となる。23, the surface is not flattened either, and an inclined surface remains on the stepped portion of the narrow groove.
次に（ｃ）に示すように、基板・ぐイアスが０■の条件
、即ち通常のスパッタリング法、あるいはノラズマＣＶ
Ｄ法や減圧ＣＶＤ法等により例えば酸化シリコン膜２５
を厚さ約０．８μｍ形成した後、例えばエチルセロソル
ブアセテートを主成分とした熱流動性の高いデジレジス
ト膜２６を塗布し、１４０℃で３０分間熱処理を行う。Next, as shown in FIG.
For example, a silicon oxide film 25 is formed by D method or low pressure CVD method.
After forming a film with a thickness of about 0.8 μm, a digiresist film 26 with high thermofluidity mainly composed of, for example, ethyl cellosolve acetate is applied and heat treated at 140° C. for 30 minutes.
これによりレジスト膜２６の表面はほぼ平坦になる。This makes the surface of the resist film 26 substantially flat.
次に、例えばＣＦ４ガスを用いた反応性イオンエツチン
グ法により、例えばＲＦパワー１５０ Ｗ％！ｘ圧力３
０ ｍ Ｔｏｒｒとして、レジスト膜２６と酸化シリコ
ン膜２５のエツチング速度を同一にして（〜５００紗ｍ
１ｎ ）、（ａ）に示すようにレジスト膜２６が全て除
去されるまでエツチングをする。この後は図示しないが
、接続孔をあけて第２層目のアルミニウム配線層を形成
する。Next, a reactive ion etching method using, for example, CF4 gas is applied to, for example, an RF power of 150 W%! x pressure 3
The resist film 26 and the silicon oxide film 25 were etched at the same etching rate at 0 m Torr (~500 m Torr).
1n), etching is performed until the resist film 26 is completely removed as shown in (a). After this, although not shown, connection holes are made and a second aluminum wiring layer is formed.
この実施例によれば、従来のＣＶＤによる絶縁膜堆積と
エツチングによる平坦化法では完全に埋められない細溝
を完全に埋めることができ、しかもバイアススフ９ツタ
法のみでは平坦化できない基板表面を完全に平坦化する
ことができる。According to this example, it is possible to completely fill the narrow grooves that cannot be completely filled with the conventional planarization method of insulating film deposition and etching using CVD, and also completely fill the substrate surface that cannot be planarized using only the bias 9 vine method. It can be flattened to
従ってこの上に更に配線層を形成する場合、接続孔のエ
ツチング深さが場所によらず一定となり、多層配線の信
頼性が向上する。Therefore, when a wiring layer is further formed on top of this, the etching depth of the connection hole becomes constant regardless of the location, improving the reliability of the multilayer wiring.
第３図（ａｌから（ｄ）は本発明の第２の実施例を示す
工程断面図である。（ａ）は先の実施例で述べた第２図
（ａ）と同じである。次に（ｂ）に示すように、先の実
施例と同様の条件のバイアスス・ぐツタ法により、膜厚
０．８μｍの酸化シリコン膜２４を形成した後、例えば
エチルセロソルブアセテートを主成分とした熱流動性の
高いポジレジスト膜２６を直接塗布し、１４０℃で３０
分間熱処理を行う。これにより、レジスト膜２６の表面
は平坦になる。3(a) to 3(d) are process sectional views showing the second embodiment of the present invention.(a) is the same as FIG. 2(a) described in the previous embodiment.Next, As shown in (b), after forming a silicon oxide film 24 with a film thickness of 0.8 μm by the Biassus Guttu method under the same conditions as in the previous example, a thermal fluid film containing, for example, ethyl cellosolve acetate as a main component is formed. A positive resist film 26 with high properties is applied directly and heated at 140°C for 30°C.
Perform heat treatment for a minute. As a result, the surface of the resist film 26 becomes flat.
次に、例えば前述したＣＦ、ガスを用いた反応性イオン
エツチング法により、レジスト膜２６と酸化シリコン膜
２４のエツチング速度が同一となる条件で（ｅ）に示す
ようにレジスト膜２６が全て除去されるまでエツチング
をする。そして、さらに（ｄ）に示すように酸化シリコ
ン膜２７を例えばＣＶＤ法やスパッタ法等により膜厚０
．８μｍ形成する。Next, the resist film 26 is completely removed as shown in (e) under the condition that the etching rate of the resist film 26 and the silicon oxide film 24 are the same, for example, by the aforementioned reactive ion etching method using CF or gas. Etch until it's dry. Further, as shown in (d), the silicon oxide film 27 is formed to a thickness of 0 by, for example, the CVD method or the sputtering method.
．． Form 8 μm.
この実施例によっても、酸化シリコン膜２７の表面は完
全に平坦になっており、がっ、配線層２３上の酸化シリ
コン膜２７の膜厚は等しくなっている。これにより、多
層配線の索子製造の信頼性が向上する。Also in this embodiment, the surface of the silicon oxide film 27 is completely flat, and the thickness of the silicon oxide film 27 on the wiring layer 23 is equal. This improves the reliability of manufacturing cables for multilayer wiring.
本発明は土述した実施例に限定されるものではない。上
記実施例は、バイアススフ９ツタ法により酸化シリコン
膜を形成する場合について述べたが、他に窒化シリコン
膜等でもよい。また、基板バイアスも一５０Ｖから一１
５０Ｖ程度の範囲で同じ効果が得られた。The invention is not limited to the embodiments described above. In the above embodiment, a silicon oxide film is formed by the bias suction 9 vine method, but a silicon nitride film or the like may also be used. Also, the substrate bias can be changed from -50V to -11V.
The same effect was obtained in a range of about 50V.
上記実施例では、レジストを塗布ベーキングした後、反
応性イオンエツチング法でエツチングしたが、プラズマ
エツチング、スパッタエツチング等、他のドライエツチ
ング法でもよい。In the above embodiment, the resist was applied and baked and then etched by reactive ion etching, but other dry etching methods such as plasma etching, sputter etching, etc. may also be used.
また平坦化法としては、レジストをエツチングする以外
にも、本発明者等が先に提案した反応性イオンエツチン
グ法を利用した絶縁層の平坦化法（特願昭５５−１３０
７５４号、特願昭５５−１５０１７９号）、即ち例えば
ＣＦ４とＨ７とを用いた反応性イオンエツチング法によ
り窒化シリコン膜をエツチングする際に、凹部より凸部
でエツチング速度が速くなるという平坦化現象を利用し
た方法で行ってもよい。As a planarization method, in addition to etching the resist, there is also a method for planarizing an insulating layer using a reactive ion etching method previously proposed by the present inventors (Japanese Patent Application No. 55-130).
754, Japanese Patent Application No. 55-150179), that is, when etching a silicon nitride film by a reactive ion etching method using, for example, CF4 and H7, a flattening phenomenon in which the etching rate is faster in convex parts than in concave parts. This can also be done using a method using
また、上記実施例では、配線層上の絶縁膜即ち、多層配
線の層間絶縁膜の場合について述べたが、第１層の配線
層の下の絶縁膜を平坦化する場合にも本発明は有効であ
る。Further, in the above embodiment, the case of an insulating film on a wiring layer, that is, an interlayer insulating film of a multilayer wiring was described, but the present invention is also effective when flattening an insulating film under a first wiring layer. It is.
第１図は従来例を示す断面図、第２図（ａｌ〜（ｄ）は
本発明の第１の実施例を示す工程断面図、第３図（ａ）
〜（ｄ）は第２の実施例を示す工程断面図である。
２１・・・シリコン基板、２２・・・酸化シリコン膜、
２３８，２３．．２３．・・・アルミニウム配線層、２
４・・・酸化シリコン膜（バイアススノやツタ法）、２
５．２７・・・酸化シリコン膜（通常スパッタ法又はＣ
ＶＤ法）、２６・・・レゾスト膜（流動性物質膜）。
出願人代理人 弁理士 鈴 江 武 彦第１図Fig. 1 is a sectional view showing a conventional example, Fig. 2 (al to (d)) is a process sectional view showing a first embodiment of the present invention, and Fig. 3 (a)
-(d) are process cross-sectional views showing the second embodiment. 21... Silicon substrate, 22... Silicon oxide film,
238, 23. ．． 23. ...Aluminum wiring layer, 2
4...Silicon oxide film (bias snow or ivy method), 2
5.27...Silicon oxide film (normal sputtering method or C
VD method), 26...resist film (fluid material film). Applicant's agent Patent attorney Takehiko Suzue Figure 1
Claims (4)
ススノ臂ツタ法によって前記細溝の段差部上に傾斜面が
残るような弱いバイアス条件で絶縁膜を形成する工程と
、形成された絶縁膜の表面を平坦化する工程とを備えた
ことを特徴とする半導体装置の製造方法。(1) A step of forming an insulating film on a surface on which a narrow groove is formed on a semiconductor substrate using a bias snoot method under weak bias conditions such that an inclined surface remains on the stepped portion of the narrow groove, and 1. A method for manufacturing a semiconductor device, comprising the step of planarizing a surface of an insulating film.
ＣＶＤ法または通常のスパッタ法による絶縁膜を堆積し
、その表面に流動性物質膜を塗布して、これら流動性物
質膜とその下の絶縁膜を両者に対してエツチング速度が
等しくなるように条件設定したドライエツチング法によ
り全面エツチングするものである特許請求の範囲第１項
記載の半導体装置の製造方法。(2) In the step of planarizing the surface, an insulating film is deposited on the insulating film by a CVD method or a normal sputtering method, and a fluid material film is applied to the surface of the insulating film, and the fluid material film and the 2. The method of manufacturing a semiconductor device according to claim 1, wherein the entire surface of the underlying insulating film is etched by a dry etching method in which conditions are set so that etching rates are equal for both.
接流動性物質膜を塗布してこの流動性物質膜と前記絶縁
膜を両者に対してエツチング速度が等しくなるように条
件設定したドライエツチング法により全面エツチングす
るものである特許請求の範囲第１項記載の半導体装置の
製造方法。(3) In the step of flattening the surface, a fluid material film is applied directly onto the insulating film, and conditions are set so that the fluid material film and the insulating film are etched at the same rate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the entire surface is etched by a dry etching method.
子形成された半導体基板に絶縁膜を介して金属配線層を
形成した表面である特許請求の範囲第１項記載の半導体
装置の製造方法。(4) The semiconductor device according to claim 1, wherein the surface on which the narrow grooves are formed on the semiconductor substrate is a surface on which a metal wiring layer is formed on the semiconductor substrate on which elements are formed through an insulating film. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22356883A JPS60115234A (en) | 1983-11-28 | 1983-11-28 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22356883A JPS60115234A (en) | 1983-11-28 | 1983-11-28 | Preparation of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60115234A true JPS60115234A (en) | 1985-06-21 |
Family
ID=16800198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22356883A Pending JPS60115234A (en) | 1983-11-28 | 1983-11-28 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60115234A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6110240A (en) * | 1984-06-20 | 1986-01-17 | Yokogawa Hewlett Packard Ltd | Manufacture of semiconductor element |
| JPS63177442A (en) * | 1987-01-16 | 1988-07-21 | Nec Corp | Manufacture of semiconductor device |
| KR970008403A (en) * | 1995-07-10 | 1997-02-24 | 김주용 | Insulation Planarization Method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5664436A (en) * | 1979-10-30 | 1981-06-01 | Fujitsu Ltd | Manufacturf of semiconductor device |
| JPS5763843A (en) * | 1980-08-22 | 1982-04-17 | Ibm | Method of forming recess dielectric region on silicon substrate |
| JPS58100435A (en) * | 1981-12-10 | 1983-06-15 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1983
- 1983-11-28 JP JP22356883A patent/JPS60115234A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5664436A (en) * | 1979-10-30 | 1981-06-01 | Fujitsu Ltd | Manufacturf of semiconductor device |
| JPS5763843A (en) * | 1980-08-22 | 1982-04-17 | Ibm | Method of forming recess dielectric region on silicon substrate |
| JPS58100435A (en) * | 1981-12-10 | 1983-06-15 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6110240A (en) * | 1984-06-20 | 1986-01-17 | Yokogawa Hewlett Packard Ltd | Manufacture of semiconductor element |
| JPS63177442A (en) * | 1987-01-16 | 1988-07-21 | Nec Corp | Manufacture of semiconductor device |
| KR970008403A (en) * | 1995-07-10 | 1997-02-24 | 김주용 | Insulation Planarization Method |
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