JPS5664436A - Manufacturf of semiconductor device - Google Patents

Manufacturf of semiconductor device

Info

Publication number
JPS5664436A
JPS5664436A JP14023179A JP14023179A JPS5664436A JP S5664436 A JPS5664436 A JP S5664436A JP 14023179 A JP14023179 A JP 14023179A JP 14023179 A JP14023179 A JP 14023179A JP S5664436 A JPS5664436 A JP S5664436A
Authority
JP
Japan
Prior art keywords
1mum
approx
thickness
wire
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14023179A
Other languages
Japanese (ja)
Inventor
Ryoji Abe
Chuichi Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14023179A priority Critical patent/JPS5664436A/en
Publication of JPS5664436A publication Critical patent/JPS5664436A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent the stepwise disconnection of a wire in a semiconductor device by forming a film of substance softened and flowed on a stepwise film thereby flattening the surface, irradiating ion beam to the entire surface thereby etching the surface and flattening the surface. CONSTITUTION:An aluminum wire 2 having a thickness of approx. 1mum is formed on an Si substrate 1, and a PSG 3 having a thickness of approx. 1mum is laminated thereon by a CVD process. When a photoresist film 4 is rotatably coated thereon thereby laminating the film 4 having a thickness of approx. 1mum, the surface become almost flat. Subsequently, Ar ion beam is irradiated to the surface thereby etching the surface. Then, the PSG surface becomes flat. Subsequently, a PSG 5 having a thickness of approx. 1mum is aganin laminated thereon, is then patterned thereby forming an electrode window, aluminum is evaporated thereon in a thickness of approx. 1mum, is then patterned, thereby forming a wire 6. Since the wire 6 is formed on the flat surface, no disconnection occurs.
JP14023179A 1979-10-30 1979-10-30 Manufacturf of semiconductor device Pending JPS5664436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14023179A JPS5664436A (en) 1979-10-30 1979-10-30 Manufacturf of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14023179A JPS5664436A (en) 1979-10-30 1979-10-30 Manufacturf of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5664436A true JPS5664436A (en) 1981-06-01

Family

ID=15263949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14023179A Pending JPS5664436A (en) 1979-10-30 1979-10-30 Manufacturf of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5664436A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS605527A (en) * 1983-06-24 1985-01-12 Agency Of Ind Science & Technol Flattening method of semiconductor device
JPS60115234A (en) * 1983-11-28 1985-06-21 Toshiba Corp Preparation of semiconductor device
JPS62224937A (en) * 1986-03-27 1987-10-02 Agency Of Ind Science & Technol Recession filling process
JPS6420623A (en) * 1987-07-16 1989-01-24 Agency Ind Science Techn Flattening method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS605527A (en) * 1983-06-24 1985-01-12 Agency Of Ind Science & Technol Flattening method of semiconductor device
JPS60115234A (en) * 1983-11-28 1985-06-21 Toshiba Corp Preparation of semiconductor device
JPS62224937A (en) * 1986-03-27 1987-10-02 Agency Of Ind Science & Technol Recession filling process
JPH0582965B2 (en) * 1986-03-27 1993-11-24 Kogyo Gijutsuin
JPS6420623A (en) * 1987-07-16 1989-01-24 Agency Ind Science Techn Flattening method

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