JPS605527A - Flattening method of semiconductor device - Google Patents
Flattening method of semiconductor deviceInfo
- Publication number
- JPS605527A JPS605527A JP11287483A JP11287483A JPS605527A JP S605527 A JPS605527 A JP S605527A JP 11287483 A JP11287483 A JP 11287483A JP 11287483 A JP11287483 A JP 11287483A JP S605527 A JPS605527 A JP S605527A
- Authority
- JP
- Japan
- Prior art keywords
- film
- inorganic
- insulating
- coating film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims abstract description 9
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000011248 coating agent Substances 0.000 claims description 48
- 238000000576 coating method Methods 0.000 claims description 48
- 239000000463 material Substances 0.000 abstract description 11
- 239000011800 void material Substances 0.000 abstract description 3
- 210000003739 neck Anatomy 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 5
- 239000004744 fabric Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000005365 phosphate glass Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、集積回路素子が形成された半導体装置の表
面を平坦化する半導体装置の平坦化方法シこ関し、導電
体の形状等に関係なく絶縁表面をほぼ平坦にできるよう
にすることを目的とする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device planarization method for planarizing the surface of a semiconductor device on which an integrated circuit element is formed. The purpose is to make it possible.
近年、高密度化、高機能化を図るために、集積回路が形
成された半導体装置を積層して構成される積層集積回路
素子や、配線を多層に重ねた構造の半導体装置の開発が
進められている。In recent years, in order to achieve higher densities and higher functionality, progress has been made in the development of multilayer integrated circuit elements, which are constructed by stacking semiconductor devices on which integrated circuits are formed, and semiconductor devices, which have a structure in which wiring is stacked in multiple layers. ing.
回路作成時の酸化膜や回路要素間を電気的に接続する配
線および電極等の導電体により、半導体装置表面に凹凸
が生じ、これらの凹凸が前記積層集積回路素子等にとり
、素子の信頼性低下の原因ともなるなど好ましく在いた
め、前記凹凸を均して半導体装置表面を平坦化すること
が行々われている。Unevenness occurs on the surface of a semiconductor device due to oxide films during circuit creation and conductors such as wiring and electrodes that electrically connect circuit elements, and these irregularities affect the laminated integrated circuit elements, reducing the reliability of the element. Therefore, it is common practice to flatten the surface of a semiconductor device by smoothing out the unevenness.
いま、回路が形成された半導体基板と、回路要素間を電
気的に接続するアルミニウムやポリシリコン等の配線用
導電体と、化学的気相成長工程あ一、−、、−ＷＥ導電
体により、前記基板表面に生じている凹凸したのち、前
記有機塗布膜表面からエツチングを行ない、当初の前記
有機塗布膜の平坦な表面を前ことや、前記絶縁膜上に絶
縁材である無機塗布膜材を塗布して無機膜を形成し、前
記無機塗布膜により前記絶縁膜表面の凹凸を滑らかにし
、あるいは前記無機塗布膜表面からエツチングして前記
絶縁膜をほぼ平坦にすることが行々われでいる。Now, with the semiconductor substrate on which the circuit is formed, the wiring conductor such as aluminum or polysilicon that electrically connects the circuit elements, and the chemical vapor deposition process A1, -,, -WE conductor, After the unevenness has occurred on the surface of the substrate, etching is performed from the surface of the organic coating film, and the initially flat surface of the organic coating film is etched. It is common practice to form an inorganic film by coating, and use the inorganic coating film to smooth out unevenness on the surface of the insulating film, or to make the insulating film substantially flat by etching the surface of the inorganic coating film.
ところで、前記絶縁膜の表面に生じる凹凸は、前記導電
体の形状や隣接する導電体間の距離等によって異なり、
前記半導体装置がたとえば第１図に示すようなものであ
ると、半導体装置（１）の半導体基板（２）と配線用導
電体（３）との境の段差部に対応する絶縁膜（４）の段
差部にくびれ（５）が発生したり、隣接する導電体（３
）間の距離すなわち配線スペースが短くなるニー１ど、
訓導電体（３）間の溝部に形成され機塗布膜を形成して
エツチングを行なうと、第２図に示すように、絶縁膜（
４）の凸部の表面は平坦になっても、′くびれ（５）
、 ＜ぼみ（６）や空隙（７）は依然とチングをするこ
とにより、絶縁１１％ｆ４）Ｋ＜ぼみ（６）や−布膜（
８）を形成すると、絶縁膜（４）の表面の凹凸はかなり
滑らかになり、くびれ（５）やくぼみ（６）π無機塗布
膜材が流れ込んでくびれ（５）やくぼみ（６）はなくな
るが、空隙（７）はそのまま残存し、前記無機塗布膜材
が凹部には溜り易く平坦部には流動して溜り難いため、
絶縁膜（４）の凹凸部および平坦部に対応して無機塗布
膜（８）の表面が波打ち、平坦にはならず即時に無機塗
布膜（８）にひび割れが生じるという欠点がある。Incidentally, the unevenness that occurs on the surface of the insulating film varies depending on the shape of the conductor, the distance between adjacent conductors, etc.
If the semiconductor device is as shown in FIG. 1, for example, an insulating film (4) corresponding to a stepped portion at the boundary between the semiconductor substrate (2) and the wiring conductor (3) of the semiconductor device (1) A constriction (5) may occur at the step part of the conductor (3), or the adjacent conductor (3)
), that is, the wiring space becomes shorter.
When a machine coated film is formed in the groove between the training conductors (3) and etched, an insulating film (
Even if the surface of the convex part in 4) becomes flat, the convex part (5)
, <The recess (6) and the void (7) are still insulated by ching, so that the insulation is 11% f4)K<the recess (6) and the -cloth film (
8), the unevenness on the surface of the insulating film (4) becomes considerably smooth, and the constrictions (5) and depressions (6) π inorganic coating film material flows in, eliminating the constrictions (5) and depressions (6). , the voids (7) remain as they are, and the inorganic coating film material tends to accumulate in the recesses, but flows and is difficult to accumulate in the flat areas.
There is a drawback that the surface of the inorganic coating film (8) is wavy in correspondence with the uneven portions and flat portions of the insulating film (4), and the inorganic coating film (8) does not become flat and cracks immediately occur.
この発明は、前記の点に留意してなされたものであり、
導電体等によって表面に凹凸が生じている半導体表面に
絶縁膜を形成する工程と、無機塗布膜を形成する工程と
、有機塗布膜を形成する工つぎに、この発明を、その１
実施例を示した第４図とともに詳細に説明する。This invention was made with the above points in mind,
Next, the present invention will be described in part 1.
This will be explained in detail with reference to FIG. 4 showing an embodiment.
第４図（ａ）に示すように、第１図に示した半導体装置
（１）の表面を平坦にする場合、第４図０））に示すよ
うに、凹凸の生じた絶縁膜（４）上に無機塗布膜材を塗
布して無機塗布膜（９）を形成し、無機塗布膜材により
くびれ（５）およびくぼみ（６）を埋めたのち、同図（
ｃ）ｒこ示すように、無機塗布膜（９）Ｌに有機塗布膜
けを塗布して表面が平坦になるように有機塗布膜ＱＯを
形成し、同図（（ｌ］）に示すように、有機塗布膜αＯ
の表面から、有機塗布膜萌、無機塗布膜（ｑ）、絶縁膜
（４）を等速エツチングする条件でエツチングを行なう
。As shown in FIG. 4(a), when the surface of the semiconductor device (1) shown in FIG. 1 is flattened, as shown in FIG. After applying an inorganic coating material on top to form an inorganic coating film (9) and filling the constrictions (5) and depressions (6) with the inorganic coating material,
c) rAs shown in the figure, apply an organic coating film to the inorganic coating film (9)L to form an organic coating film QO so that the surface is flat, and as shown in the same figure ((l)). , organic coating film αO
Etching is performed under conditions such that the organic coating film, the inorganic coating film (q), and the insulating film (4) are etched from the surface at a constant rate.
つぎに、第４図（ｄ）中の破線に示すように、工、ッチ
ングの進行面が空隙（７）の上端部に達したときにエツ
チングを終了すると、両系布膜００）、（９）ととも：
よぼ平坦になる。Next, as shown by the broken line in FIG. 4(d), when the etching is finished when the progressing surface of the etching reaches the upper end of the gap (7), the double-sided fabric films 00), (9) ) with:
It becomes fairly flat.
つぎに、前記実施例の実験結果について説明する。Next, the experimental results of the above example will be explained.
基板（２）に厚さ７０００ Ａのリンシリコンガラス（
ＰＳＧ）、すなわちホスフェイトガラス、導電体（３）
に厚さ４０００Ａの多結晶シリコンを使用し、訓導電体
（３）間の距離、す々わちスペース幅Ｗ（単位μｍ）と
各膜の表面の段差ｂ （単位Ａ）との関係を調べた結果
、絶Ｕ嘆（４）上に塗布膜を何も形成しない場合、第５
図中の○印および実線で示すようにスペース幅Ｗに無関
係にほぼ一定となり、これた有機塗布膜を形成すると、
同図中め△印および破線で示すよう罠なり、これをエツ
チングすると、同図中の口印および１点鎖線で示すよう
に、スペース幅Ｗが布膜材を１回および４回塗布してそ
れぞれ無磯塗係は、第５図中の◎印および・印にそれぞ
れ示す１ ；
、１１≠、金になり、無機塗布膜材を４回塗布すれば、
スペース幅Ｗに無関係に無機塗布膜の表面の段差ｌ〕は
零となって絶縁表面が平坦になった。これらの実験結果
から、有機塗布膜を形成する前に、第４図、Φ）に示す
ように無機塗布膜を形成する工程を挿入しても、絶縁表
面の平坦化がＯＪ能であること罠なり、積層部のストレ
スも々く、信頼性の高い積層架構回路素子の作成が可能
となる。The substrate (2) is made of 7000A thick phosphorus silicon glass (
PSG), i.e. phosphate glass, conductor (3)
Using polycrystalline silicon with a thickness of 4000 A, we investigated the relationship between the distance between the conductors (3), that is, the space width W (unit: μm), and the step b (unit: A) on the surface of each film. As a result, if no coating film is formed on the 5th layer (4),
As shown by the circle mark and the solid line in the figure, it becomes almost constant regardless of the space width W, and when such an organic coating film is formed,
A trap is formed as shown by the mark △ and a broken line in the figure, and when this is etched, the space width W becomes larger after applying the cloth film material once and four times, as shown by the mark and the dashed line in the figure. 1; , 11≠, gold, and if the inorganic coating film material is applied four times,
Regardless of the space width W, the level difference l] on the surface of the inorganic coating film became zero, and the insulating surface became flat. From these experimental results, it was found that even if a step of forming an inorganic coating film is inserted before forming an organic coating film, as shown in Fig. 4, Φ), the OJ effect is still effective in flattening the insulating surface. This makes it possible to create a highly reliable laminated frame circuit element with less stress on the laminated portion.
つぎに、無機塗布膜および有機塗布膜の特性の実験結果
について説明する。Next, experimental results regarding the characteristics of the inorganic coating film and the organic coating film will be explained.
まず、無機塗布膜Ｊ６よび有機塗布膜のスペース幅依存
性シζついて、２酸化ケイ素からなる基板（１）上の高
さ１）＝１μｍη９幅６μｍの導７Ｆ体（３）上に形成
される塗布膜の最頂部と最底部との距離をａｌｌｍとし
、訓導電体（３）間の距離す方わちスペース幅をＷｈｉ
ｍとしたときの、スペース幅Ｗと塗布膜形成後８００Ｃ
にベークしたときの塗布膜の凹凸度（−Ｘ１００％）１
〕
との関係、すなわちスペース幅依存性は第６図に示すよ
うになり、同図においで、無機塗布膜材を１回および４
回塗布してそれぞれ厚さＱ 、 ２１ｉ ｍおよび−０
，８μｍの無機塗布膜を形成した場合をＯ印および実線
と・印および破線とによりそれぞれ示し、同様に有機塗
布膜材を１回および２回塗布してそれぞれ厚さ２．３１
ｔｍおよび２．４ｐｍ （１，２７ｚｍ ｘ ２ ）の
て、無１機塗布膜材を１回および４回塗布した場合を実
線および破線によりそれぞれ示し、有機塗布膜材を１回
および２回塗布した場合を１点鎖線および２点鎖線とに
よりそれぞれ示している。First, regarding the space width dependence ζ of the inorganic coating film J6 and the organic coating film, they are formed on a conductive 7F body (3) with a height 1)=1 μmη9 and a width of 6 μm on a substrate (1) made of silicon dioxide. Let the distance between the top and bottom of the coating film be allm, and the distance between the training conductors (3), that is, the space width, be Whi.
Space width W and 800C after coating film formation when m
Roughness of coating film when baked (-X100%) 1
] The relationship, that is, the space width dependence, is shown in Figure 6, where the inorganic coating material was applied once and four times.
The thicknesses were Q, 21im and -0 by applying three coats, respectively.
, 8 μm of inorganic coating film is shown by the O mark and solid line, and the / mark and broken line, respectively. Similarly, the organic coating material is applied once and twice to a thickness of 2.31 μm, respectively.
tm and 2.4 pm (1,27 zm x 2), the cases in which the inorganic coating material was applied once and four times are shown by solid lines and broken lines, respectively, and the cases in which the organic coating material was applied once and twice are shown, respectively. The cases are shown by a dash-dot line and a dash-double line, respectively.
なお、第４図（ａ）に示す絶縁膜（４）上に有機塗布膜
を表面が平坦になるように形成したのち、前記有機塗布
膜の表面から等速エツチングし、エツチング終了後、無
機塗布膜を形成するようにしても、この発明を同様に実
施することができる。Note that after forming an organic coating film on the insulating film (4) shown in FIG. 4(a) so that the surface is flat, etching is performed from the surface of the organic coating film at a constant speed, and after the etching is completed, an inorganic coating film is formed. The present invention can be implemented in the same manner even if a film is formed.
さらに、導電体（３）を形成したのち、無機塗布膜を形
成し、前記無機塗布膜および導電体（３）上に絶縁膜を
形成し、前記絶縁膜に有機塗布膜を形成して表面から等
速エツチングし、エツチング終了後、無機塗布膜を形成
するようにしてもよい。Furthermore, after forming the conductor (3), an inorganic coating film is formed, an insulating film is formed on the inorganic coating film and the conductor (3), and an organic coating film is formed on the insulating film to form a surface. Etching may be carried out at a constant rate, and an inorganic coating film may be formed after etching is completed.
表面の凹凸度との関係図である。FIG. 3 is a relationship diagram with the degree of surface unevenness.
、（１）・半導体装置、（３）・導電膜、（４）−絶縁
膜、（９）９ （１１）・・・無機塗布膜、（１０・・
−有機塗布膜。, (1) - Semiconductor device, (3) - Conductive film, (4) - Insulating film, (9) 9 (11) - Inorganic coating film, (10 -
-Organic coating.
特許出願人 工業技術院長 川 １）裕 部第 １ 図 一１２図 弔 弔 ３ ニア： 第５図 ス ヘ０− ス中畠” −（Ｐｍ） 第 ６ 図 スヘＯ−７輻Ｗ −（Ｐｍ）Patent applicant: Director of the Agency of Industrial Science and Technology Kawa 1) Yutaka Department Figure 1 Figure 112 Condolence Condolences 3 Nia: Figure 5 Suhe0-Su Nakabatake”-(Pm) Figure 6 Suhe O-7 W -(Pm)
Claims (1)
面に絶縁膜を形成する工程と、無機塗布膜を形成する工
程と、有機塗布膜を形成する工程と、前記塗布膜を表面
からエツチングする工程とからなり、（よぼ平坦外絶縁
表面を形成することを特徴とする半導体装置の平坦化方
法。■ A process of forming an insulating film on a semiconductor surface whose surface is uneven due to a conductor, etc., a process of forming an inorganic coating film, a process of forming an organic coating film, and a process of etching the coating film from the surface. A method for planarizing a semiconductor device, comprising: forming a substantially flat insulating surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11287483A JPS605527A (en) | 1983-06-24 | 1983-06-24 | Flattening method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11287483A JPS605527A (en) | 1983-06-24 | 1983-06-24 | Flattening method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS605527A true JPS605527A (en) | 1985-01-12 |
Family
ID=14597687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11287483A Pending JPS605527A (en) | 1983-06-24 | 1983-06-24 | Flattening method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS605527A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6110240A (en) * | 1984-06-20 | 1986-01-17 | Yokogawa Hewlett Packard Ltd | Manufacture of semiconductor element |
| JPS61196555A (en) * | 1985-02-26 | 1986-08-30 | Nec Corp | Formation for multilayer interconnection |
| JPH03222426A (en) * | 1990-01-29 | 1991-10-01 | Yamaha Corp | Formation of multilayer interconnection |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5664436A (en) * | 1979-10-30 | 1981-06-01 | Fujitsu Ltd | Manufacturf of semiconductor device |
| JPS57157545A (en) * | 1981-03-25 | 1982-09-29 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5893329A (en) * | 1981-11-30 | 1983-06-03 | Toshiba Corp | Method for flattening insulating layer |
-
1983
- 1983-06-24 JP JP11287483A patent/JPS605527A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5664436A (en) * | 1979-10-30 | 1981-06-01 | Fujitsu Ltd | Manufacturf of semiconductor device |
| JPS57157545A (en) * | 1981-03-25 | 1982-09-29 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5893329A (en) * | 1981-11-30 | 1983-06-03 | Toshiba Corp | Method for flattening insulating layer |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6110240A (en) * | 1984-06-20 | 1986-01-17 | Yokogawa Hewlett Packard Ltd | Manufacture of semiconductor element |
| JPS61196555A (en) * | 1985-02-26 | 1986-08-30 | Nec Corp | Formation for multilayer interconnection |
| JPH03222426A (en) * | 1990-01-29 | 1991-10-01 | Yamaha Corp | Formation of multilayer interconnection |
| JP2518435B2 (en) * | 1990-01-29 | 1996-07-24 | ヤマハ株式会社 | Multilayer wiring formation method |
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