JPS6155943A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the formation of minute elements by levelling the surface in projecting or recessed shape by using the formation of insulating films, the etching process of insulating films by use of one surplus mask, and the usual levelling technique. CONSTITUTION:On the substrate composed of a semiconductor substrate 1, an insulating film 2, and a polycrystalline silicon wiring 3 and which has a difference in level, an insulating film 4 whose thickness is almost same as said level difference is formed. Nextly, a resist film 5 is formed with leaving a width which is slightly wider than the level difference part. Subsequently, the part where no resist exists is removed by etching. After that, the resist is removed to produce the form in which the polycrystalline silicon 3 and the insulating film 4 are present side by side with interposing grooves 6. Then an insulating film 7 is formed by bias spattering of an insulating film thereby attaining the complete levelling.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device. This article relates to flattening the insulating film on the wiring layer.

[Technical background of the invention and its problems]

In order to perform multilayer wiring, flattening the insulating film is an essential technique. Examples of flattening methods include bias sputtering and methods that utilize the viscosity of polyimide. Bias sputtering is a combination of sputtering, sputter etching, and fills in recesses by taking advantage of the fact that re-deposition is greater on recesses than on flat areas. However, regarding the convex portion, the outward angle is the same as that of the flat portion, so although the angle can be removed microscopically, flattening is not achieved macroscopically.

Also, even with the flattening method that uses viscosity, it is difficult to deal with convex portions as with bias sputtering.

It disappears, but macroscopically it does not become a flat area.

Reducing such a steep corner eliminates the step break, but it is insufficient for the purpose of flattening in relation to the depth of focus during mask alignment.

[Purpose of the invention]

This invention facilitates the formation of fine elements of semiconductor devices by 1 ct, by flattening convex surfaces or wide concave surfaces that are difficult to flatten using conventional flattening techniques.
The present invention provides a method for manufacturing a semiconductor device that improves TFC reliability.

[Summary of the invention]

The key point of the present invention is to form an insulating film, use an extra mask, perform an etching process on the insulating film, and use a conventional planarization technique. That is, by using one extra mask, the surface of the insulator, which has convexities or wide concavities, is changed to the narrow concave shape that current flattening technology is good at. Prior art planarization technique 1 For example, planarization is performed using bias sputtering or the like.

〔Effect of the invention〕

Such a technique makes it possible to flatten any surface shape and provides more flexibility in device design. Further, taking a groove as an example, if the width is wide, it is necessary to make the film thicker to make it flat, but when the present invention is applied, it becomes possible to make the groove flat by forming an appropriate film thickness.

By flattening in this way, it is possible to avoid problems caused by pattern abnormalities due to steps during resist removal, steps caused by annealing of polycrystalline silicon, etc.

[Embodiments of the invention]

The present invention will be described in detail below according to examples.

(Example 1) FIG. 1(a) shows an example of a substrate having a convex step. Here, 1 is a semiconductor substrate, 2 is an insulating film, and 3 is a polycrystalline silicon wiring. This film thickness is temporarily set to 3oooX. This is K
By LPCVD etc., the film thickness is aooooi which is the same as that of the step.
An insulating film 4 is formed (FIG. 1(b)).

Next, leave a width slightly larger than the step part and apply resist 1.
! X5 is formed (FIG. 1(C)). Subsequently, the portions without resist are removed by etching. If this process is a wet process, an NH4F-based etching solution may be used, and if the pattern is small, reactive ion etching may be used. After such etching, the resist is removed as shown in Figure 1 (@)
Shown below. Here, the previously existing polycrystalline silicon 3 and the insulating film 4 are lined up with 11116 interposed between them. Next, the insulating film 7 is formed by the bias sputtering method of the insulating film, and the insulating film 7 is completely removed. A smooth flattening is achieved (FIG. 1(e)).

(Example 2) As mentioned above, even if the step is a concave step, if the width thereof is wide, it is difficult to flatten the step. However, even in such cases, effective flattening can be achieved by applying the present invention.

FIG. 2(a) shows an example of a substrate having a wide concave step with a width K, 11 is a semiconductor substrate, and 12 is an insulating film. An insulating film 13 is formed on this entire surface (Fig. 2(b)'), and then a resist 14 is formed in a width slightly smaller than the recess of one step (Fig. 2(C)).Subsequently, this resist layer is formed. The insulating film is etched using a mask. After that, the resist is removed and the insulating film 12. An insulating film 13 is present. Here, if bias sputtering is performed as shown in Example 1 above, a particularly flat structure can be obtained.

[Other embodiments of the invention]

As shown in the above two embodiments, the present invention is achieved by modifying the surface shape of the substrate into a shape that facilitates embedding by normal bias sputtering. The appropriate width of the groove formed after etching is considered to be 1 to 2 microns. When the technical difficulty is small, the thickness is preferably 1 μm or less, which also leads to savings in bias sputtering time for flattening.

9. The above example is a polycrystalline silicon step.

This combination is not limited to this, but is also effective in eliminating steps on the insulating film covering the intermetallic layer. It can be applied without changing the invention requirements.

It goes without saying that this invention can also be applied to planarization of polycrystalline silicon itself without departing from the gist of the invention.

Although it has been explained that the final leveling is performed by bias sputtering, any conventional technique such as one using the viscosity of the resist or spin-on silica can also be applied.

[Brief explanation of drawings]

1 and 2 are cross-sectional views showing the manufacturing process of each embodiment of the present invention. 1... Semiconductor substrate, 2... Absolute T & film. 3... Polycrystalline silicon film, 4... Insulating film. 5...Resist, 6...Groove. 7... Insulating film, 11... Semiconductor substrate. 12... Insulating film, 13... Insulating film. 14...Resist, 15...Trench, 16...Insulating film. Agent: Patent attorney Kensuke Norichika (and 1 other person) Figure 1

Claims (1)

[Claims] When flattening the surface of a substrate during the manufacturing process of a semiconductor device, an insulating film or a semiconductor film is formed to the same thickness as the unevenness, and then a resist pattern that correlates with the unevenness pattern is formed. Next, after removing the convex part by etching,
A method of manufacturing a semiconductor device characterized by using bias sputtering, spin-on silica, reflow of low melting point glass, etc.