JPS61272951A - Forming method of multilayer wiring - Google Patents

Abstract

PURPOSE:To obtain an excellent flat surface by applying liquefied glass onto the surface of an inorganic insulating film coating a wiring layer and thermally treating the liquiefied glass. CONSTITUTION:An insulating film 12 is formed onto the surface of a semiconductor substrate 10 consisting of silicon, etc., and a wiring metal is applied onto the surface of the film 12 and patterned, thus shaping a first wiring layer 14. An inorganic insulating film 16 is formed onto the whole surface on the substrate 10. Liquefied glass is applied flatly onto the surface of the film 16. The liquefied glass is baked and treated, thus acquiring a glass coating 18. The films 18, 16 are etched at approximately equal etching rates, thus flatly leaving the film 16. An inter-layer insulating film 20 is shaped onto the film 16. A contact holes is formed to the film 20, and a second wiring layer 22 is shaped.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming multilayer wiring in a semiconductor device such as an LSI, and particularly relates to an improvement in a process for planarizing multilayer wiring.

[Summary of the invention]

In this invention, when liquid glass is applied to the surface of an inorganic insulating film such as silicon oxide, which is formed to fill a wiring step, and then heat treated, a glass film is formed in a nearly flat shape, and this glass film and inorganic The insulating film t was dry-etched at approximately the same etch rate and pressured to planarize the wiring surface. According to this invention, etching conditions can be easily set.

[Conventional technology]

Conventionally, as a planarization process used for forming multilayer interconnections of LSI etc., for example, as shown in FIG.
After forming a first wiring layer 3 on the surface of the first wiring layer 3 via an insulating film 2, a buried insulating film 4 such as PSG (IJ phosphorus silicate glass) is formed to cover the first wiring layer 3. A photoresist coating M5Z is formed in a substantially flat shape by coating the surface of the buried insulating film 4 with photoresist l- and heat-treating it, and then the photoresist film 5 and the buried insulating film 4 are almost flat as shown in FIG. A so-called etch process is performed in which dry etching is performed at an equal etch rate to leave a substantially flat surface on the buried insulating film 4, and a second wiring layer is formed on the remaining buried insulating film 4 via the interlayer insulating film 2.・Tetsuku method is known.

Another method is to form a first wiring layer on the substrate and then apply liquid glass (generally called spin-on glass (SOG)) on the wiring formation surface. It is known that a glass film is formed into a substantially flat shape by heat treatment, and a second wiring layer is formed on the glass film via an insulating film between the eyebrows.

[Problem that the invention seeks to solve]

According to the above-mentioned etch pack method, it is necessary to set the etching conditions so that the photoresist film and the buried insulating film such as PSG have approximately the same etch rate during dry etching, but it is easy to set such conditions. It wasn't. For example, in plasma etching using CF4 as an etching gas, if the flow rate of H2 or O2 is changed, the etch rates of photoresist and PSG change as shown by curves A and B in FIG. 9, respectively. Here, the etch rate of photoresist (curve A) and the etch rate of PSG v
-) (curve B) coincides with point P, and this point! If it comes off, the etch rate of the two will be drastically different.

In practice, it is not easy to control etching conditions so as to satisfy point P, and etching progresses at an etch rate at or near point P. For this reason, reproducibility was not good.

Furthermore, as shown in FIG. 8, when a part of the PSG film 4 is exposed as etching progresses, the 02 released from 5i02 in the PSG increases the 02 concentration near the PEG exposed part, and the etch rate of the photoresist increases. In order to raise the surface area, portions a and b corresponding to the wiring steps were overetched, which hindered planarization.

In addition, in the flattening process of applying liquid glass as described above, the insulation and mechanical strength of the glass coating are not sufficient, and there are many cases where charges such as sodium ions are present in the glass coating. There is a problem in that the electrical characteristics (for example, the capacitance-voltage characteristics of an MO8 type transistor) of the circuit elements formed on the surface of the substrate become unstable.

[Means for solving problems]

This invention has been made to solve the above-mentioned problems, and is to use liquid glass instead of photoresist in the above-mentioned etch pack method.
It is a sign.

In other words, in the multilayer wiring forming method according to the present invention, after forming a first wiring layer on a substrate, an inorganic insulating film such as 5i02, PSG, etc. is applied to cover the first wiring layer and fill in the wiring steps. The surface of the inorganic insulating film is heat-treated in a liquid glass film to form a nearly flat glass film, and the glass film and inorganic insulating film are etched at approximately the same etch rate by dry etching to form an inorganic insulating film. The insulating film 't'ft is left in a flat shape, and a second wiring layer is formed on the remaining inorganic insulating film via an interlayer insulating film.

[Effect]

According to the method of this invention described above, the glass coating is 5s0
Since it is an inorganic insulator with 2t' as the main component, 5i02,
It has similar etching characteristics to inorganic insulating films such as PSG. Therefore, during dry etching, it is easy to set etching conditions so that the glass film and the inorganic insulating film have approximately the same etch rate, and the reproducibility of etching is also good.

Also, if part of the inorganic insulating film is exposed during etching, 1. The etch rate of the glass film hardly increases. Therefore, the inorganic insulating film is prevented from being excessively etched in the portion corresponding to the wiring level difference, and exhibits a good flat surface.

Furthermore, a second wiring layer was formed on the remaining inorganic insulating film via an interlayer insulating film, and no glass film remained below the second wiring layer, so that circuit elements formed on the substrate surface could be This can prevent the electrical characteristics of the device from becoming unstable.

〔Example〕

1 to 6 show the multilayer wiring forming process according to one embodiment of the present invention, and the process 1 corresponding to each figure number is shown in FIG.
11 to (6) will be explained in order.

11) Insulating film 12Y made of silicon octide or the like on the surface of the semiconductor substrate 100 made of silicon or the like: After forming this insulating film 1
The first wiring layer 14'4 is formed by depositing a desired wiring metal on the surface of the wiring layer 20 by any method such as vapor deposition or sputtering, and patterning it by photolithography.

(2) Next, by covering the first wiring layer 14 and filling the wiring steps, 5io2 or P2O7,'C is applied to the entire surface of the substrate.
(3) Next, liquid glass is deposited on the surface of the inorganic insulating film 16 using, for example, a rotating coating bag fl (spinner). (Suspension of fine silica powder)
t is applied evenly. Then, in order to remove the solvent from the coated glass, a hardened glass coating 18 is obtained by performing an eening process at, for example, 4000C to 450C.

(4) Next, by dry etching such as plasma etching, the glass plate M18 and the 16 inorganic insulating films thereunder are etched at approximately the same etch rate to form a flat inorganic insulating film 16 as shown in FIG. to remain.

In this case, it is easy to set the etching conditions to match the etch rate v between the glass substrate J[g18 and the inorganic insulating film 16 such as 5i02, PSA, etc., and the etching can be carried out smoothly without local excessive etching. progresses. .

(5) Next, a glabellar insulating film 20a is formed on the remaining inorganic insulating film 16 by CVD or the like. As the material for this glabellar insulating film part, any material such as 5i02, PSG, Si3N4, etc. can be used.

(6) After this, contact holes are provided at appropriate locations in the interlayer insulating film portion, and then a second wiring layer 22 is formed in the same manner as in the case of the first wiring layer described above.

〔Effect of the invention〕

As described above, according to the present invention, liquid glass is applied to the surface of the inorganic insulating film covering the first wiring layer t and heat-treated to form a substantially flat glass film, and the glass film and the inorganic insulating film are The film was dry-etched at approximately the same etch rate to leave a nearly flat layer on the inorganic insulating film, and the second wiring layer Z was formed on the remaining inorganic insulating film via the interlayer insulating film. You can get a immersive effect like this.

+1) Since the glass film and the inorganic insulating film have similar etching characteristics, it is easy to set the etching conditions during dry etching, and the writeability is good, improving the manufacturing yield.

(2) Since there is almost no increase in the etch rate of the glass film during dry etching, the inorganic insulating film is not partially over-etched and a good flat surface can be obtained.

(3) Since no glass film remains, an electrically stable flattened wiring structure can be realized.

[Brief explanation of the drawing]

1 to 6 are cross-sectional views of a substrate showing a multilayer wiring forming process according to an embodiment of the present invention, FIGS. 7 and 8 are cross-sectional views of a substrate showing a conventional planarization process, and FIG. , H2 and 02 in plasma etching
3 is a graph showing the relationship between flow rate and etch rate. 10... Semiconductor substrate, 12... Insulating film, 14...
1st wiring layer, 16... inorganic insulating film, 18... glass coating, additive... interlayer insulating film, η... second wiring layer. Applicant Nippon Musical Instrument Manufacturing Co., Ltd. Agent Patent Attorney Toshiaki Izawa Figure 1 (Japanese 4fj people) Figure 2 (No #!Hikijin decrease) Figure 3 (Attack on I) Figure 4 (Drei Ekko) Fig. 5 (Layer M-thick stock #Akinari)

Claims (1)

[Claims] (a) A step of forming a first wiring layer on a substrate; (b)
(c) forming an inorganic insulating film by covering the first wiring layer on the substrate and filling the wiring steps; (c) applying liquid glass to the surface of the inorganic insulating film and heat-treating the surface to make the surface almost flat; (d) dry etching the glass coating and the inorganic insulating film at substantially the same etch rate to leave the inorganic insulating film in a substantially flat shape; (e) A method for forming a multilayer wiring, including the steps of: forming an interlayer insulating film on the remaining inorganic insulating film; and (f) forming a second wiring layer on the interlayer insulating film.