JPH03295239A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to form almost uniformly the thickness of a first glass layer on the dense parts and coarse parts of a wiring layer by a method wherein the first glass layer of a slow polishing rate and a second glass layer of a fast polishing rate are respectively formed as an interlayer insulating film and the second glass layer is polished and flattened. CONSTITUTION:Wiring layers 20 to 23 consisting of Al or the like are formed on a semiconductor substrate 1 and an interlayer insulating film (a first glass layer) 3 consisting of PSG or the like is deposited. Then, an SOG buried layer (a second glass layer) 4 is formed in the surface by a spin coating method and heat treatment is performed to harden the layer 4. Subsequently, the surface of the layer 4 is polished using a hydrofluoric acid to flatten. At this time, the polishing rate of the buried layer (an SOG layer) 4 is set so as to be faster than that of the interlayer insulating film (a PSG layer) 3. Thereby, the film 3 results in working as a mask (a stopper) at the time of the polishing and the thickness of the film 3 can be formed almost evenly.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device having a multilayer wiring structure, the present invention relates to a method for manufacturing a semiconductor device having a multilayer wiring structure, with the purpose of forming an interlayer insulator with a uniform thickness to improve the coverage of the wiring layer. A first glass layer for interlayer insulation is formed on a patterned semiconductor substrate, and further thereon is an interlayer insulation film whose polishing rate is set higher than that of the first glass layer. and a step of polishing the second glass layer to planarize its surface.

(Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device having a multilayer wiring structure.

In recent years, there has been a demand for greater integration of LSIs, and as a result, multilayer wiring structures have been used as wiring layers. In this case, the coverage deteriorates due to the unevenness of the wedge base layer, which becomes the upper wiring layer, and to prevent this, the surface is usually flattened after patterning the wiring layer and depositing interlayer insulation. There is a need to.

[Conventional technology]

FIG. 3 shows a manufacturing process diagram of an example of a conventional method.

In the same figure (A), a wiring layer 2 made of aluminum or the like is formed on a semiconductor substrate 1 by patterning,
Then, an interlayer insulating film 3 such as HO 5 illicate glass is deposited. Next, as shown in the same figure (B), S
A buried layer 4 such as OG (spin on alas) is formed as a spin cord, and this is hardened by heat treatment. Subsequently, as shown in FIG. 5C, the surface is etched back using anisotropic etching (controlled etching) to flatten the surface, and a second wiring layer (not shown) is further patterned on the flattened surface. .

[Problems to be Solved by the Invention] By the way, the wiring layer pattern may be formed densely or sparsely as shown in FIG. 4 depending on the design of the device. In the same figure (A), the wiring layer 2+, 22.2 in the dense part
An interlayer insulating film (PS
G) 3 is formed, and then, in the same figure (B), a buried layer (SOG) 4 is spin-coded on the surface thereof. in this case,
As shown in Figure (B), the buried layer (
The SOG) 4 tends to be formed thinner than the rough portions, and there is a large step difference between the dense portions and the rough portions on the surface of the embedding 14.

For this reason, when etching back is performed by anisotropic etching, the thickness of the interlayer wiring 1lI3 becomes too thin, especially in areas where the wiring layer is dense and the buried layer 4 is thin, and in this state, the thickness of the interlayer wiring 1lI3 becomes too thin. When a wiring layer is formed, there is a problem in that defects tend to occur between the wiring layer and the underlying wiring layer.

In order to avoid this, if the etch back is reduced, the interlayer insulating film 3 on the wiring layer 20 in the rough portion becomes thicker, so a contact hole 6 is formed as shown in FIG. 7, there were problems such as poor coverage of the wiring layer 7 at the contact hole 6 portion.

In order to prevent defects due to the difference in the thickness of the interlayer insulating film, it is possible to form the interlayer insulating film (PSG) 3 thickly as shown in FIG. 2+, 22.

Interlayer insulation Il between 23! This creates a part where i13 is not formed, that is, a gap 5, and the processing liquid penetrates in the later process, or when the second wiring layer 7 is formed, the second wiring layer II gets into this gap and the lower layer Failures with the wiring layer are likely to occur.

Another method of depositing an insulating film that does not create voids is to deposit the shoulder part of the interlayer insulating film by sputtering. It is thicker than others, making it difficult to control the deposition.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the coverage of wiring layers by forming an interlayer insulating film with uniform spacing.

[Means to solve the problem]

The above problem is solved by forming a first glass layer as an interlayer insulating film on a semiconductor substrate on which a wiring layer has been patterned, and further forming an interlayer with a polishing rate set higher than that of the first glass layer. The problem is solved by a method for manufacturing a semiconductor device characterized by including a step of forming a second glass layer to serve as an insulating film, and a step of polishing the second glass layer to flatten the surface.

(Function) Since the polishing speed of the second glass layer is set to be faster than the polishing speed of the first glass layer, the first glass layer acts as a mask (stopper) during polishing. Become. In this case, even if the second glass layer is formed thinly in areas where wiring layers are densely formed, the first glass layer acts as a mask (stopper) and polishing does not proceed on its surface. The first in the dense and coarse parts
The thickness of the glass layer can be made approximately equal. Therefore, the thickness of the interlayer insulating film in dense areas does not become too thin as in the conventional example.

〔Example〕

FIG. 1 shows a manufacturing process diagram of a first embodiment of the present invention. In FIG. 1A, wiring layers 20 to 23 made of aluminum or the like are patterned to a thickness of, for example, 1 μm on a semiconductor substrate 1, and an interlayer insulating film (first glass II) 3 made of PSG or the like is formed by patterning to a thickness of, for example, 1 μm. Deposit to a thickness of 8 μm. Next, as shown in the same figure (B), SOG is embedded on the surface II (second glass l!).
4 is formed into a spin cord, for example at 400°C to 450°C.
The embedded lI4 is hardened by heat treatment for 30 minutes in nitrogen gas.

Subsequently, as shown in the same figure (C), for example, 0.5% to 1.0
% concentration of hydrofluoric acid to polish and flatten the surface.

At this time, the polishing rate of the buried layer (SOG) 4 is generally
When performing spin coding, it is possible to freely adjust the amount of water contained in the SOG. Therefore, SOG
The water content is adjusted so that the polishing rate of the buried layer (SOG) 4 is faster than the polishing rate of the interlayer insulation 11 (PSG) 3. As a result, the interlayer insulating film (PSG) 3 acts as a mask (stopper) during the polishing, and the thickness of the interlayer insulating film 3 can be formed to be approximately uniform as shown in FIG. . That is, as shown in FIG. 2B, the buried layer 4 in the dense portions such as the wiring layers 2+ and 22.23 is buried in the coarse portions such as the wiring layer 2°.
Even if it is formed thinner than the above, the interlayer insulation w
If the polishing speed is set to be different between A3 and the buried layer 4, polishing will not progress on the surface of the interlayer insulation ll13 in the dense area.
Therefore, the thickness of the interlayer insulating film 3 in the dense portion and the coarse portion can be made approximately equal.

Therefore, as in the conventional example where the interlayer insulating film 3 was flattened by etchback using anisotropic etching, the interlayer insulating film 3 in the dense parts becomes too thin, or the interlayer insulating film 3 in the rough parts becomes too thin. Problems such as force imbalance failure due to thickening of II3 no longer occur, and no particular failure occurs even when the 2Nth wiring layer is formed. Furthermore, since there is no need to particularly form the interlayer insulating film 3 thickly, the problem described using FIG. 5 does not occur.

In addition, if a silicon nitride film is formed on the surface of the interlayer insulating film 3 by the plasma CUD method in FIG. 1 <A), damage to the interlayer insulating film 3 during polishing at the stage of FIG. be able to.

FIG. 2 shows a manufacturing process diagram of a second embodiment of the present invention. In the same figure (A), wiring layers 20 to 23 made of aluminum or the like are formed to have a thickness of, for example, 1 μm on a semiconductor substrate 1, and PSG
For example, the interlayer insulating film 10 of
Deposited to a thickness of . Generally, when PSG is grown thinly, it can be grown with relatively good coverage, and the second embodiment utilizes this property.

Next, as shown in FIG. 4B, a buried layer 4 of SOG is spin-corded on the surface, and the buried layer 4 is hardened by heat treatment in nitrogen gas at 400 DEG C. to 450 DEG C. for 30 minutes, for example.

Next, as in the first embodiment, the polishing speed of the buried layer 4 is set to be faster than the polishing speed of the interlayer insulation sio, and polishing is performed as shown in FIG. The thickness of the insulating film 1o is made to be approximately uniform. As it is, the interlayer insulating film 10 is too thin to provide interlayer insulation, so an interlayer insulating film 11 of PSG is formed on the surface of the interlayer insulating film 10, as shown in FIG. In this second embodiment, in addition to the effects described in the first embodiment, the interlayer insulating film 10 can be removed without creating the above-mentioned voids, especially when the spacing between the wiring layers 21 to 23 in the dense portions is very narrow. This has the effect of making the thickness of 11 approximately uniform.

In each of the above embodiments, P is used as the interlayer insulation R3 and R10.
Although SOG is used as the SG and the buried layer 4, the present invention is not limited thereto. Silicon oxide is embedded as the film 310! t4
It is also possible to use a combination using PSG.

〔Effect of the invention〕

As explained above, according to the present invention, the first glass layer with a slow polishing rate and the second glass layer with a fast polishing rate are formed as interlayer insulating films, and the second glass layer is polished and planarized. Therefore, even if the second glass layer is formed thinly in areas where the wiring layer is densely formed, polishing will not proceed on the surface of the first glass layer, and the area where the wiring layer is densely formed and rough areas will be polished. The thickness of the first glass layer in the portion can be made approximately uniform. Therefore, unlike the conventional example, defects with the second wiring layer do not occur, and unlike the conventional example, there is no need to form a thick interlayer insulating film, so the coverage of the second and higher wiring layers is improved. Can be done.

[Brief explanation of drawings]

Fig. 1 is a manufacturing process diagram of the first embodiment of the present invention, Fig. 2 is a manufacturing process diagram of the second embodiment of the invention, Fig. 3 is a manufacturing process diagram of a conventional example, and Fig. 4 is an embedding process diagram. FIG. 5 is a diagram illustrating a level difference generated on a layer surface, and FIG. 5 is a diagram illustrating a problem that occurs when a thick interlayer insulating film is formed. Reference numeral 20 indicates the wiring layer in the coarse portion, and 21 to 23 indicate the wiring layer in the dense portion. 3.10.11 indicates an interlayer insulating film (first glass layer) such as PSG, and 4 indicates a buried li (second glass layer) such as SOG.

Claims (1)

[Claims] A first glass layer (3) to serve as an interlayer insulating film is formed on a semiconductor substrate (1) on which wiring layers (2_0 to 2_3) have been patterned, and further thereon, the first glass layer (3) is a step of forming a second glass layer (4) to serve as an interlayer insulating film, the polishing rate of which is set faster than that of the first glass layer (3); and polishing the second glass layer (4). A method of manufacturing a semiconductor device, comprising the step of flattening a surface by using a method of manufacturing a semiconductor device.