JPH0430524A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent cracking of a residual resin layer after total dry etching without depending on an aspect ratio and thereby to enable attainment of flattening by a method wherein a resin material for flattening is applied on a substrate, prebake for removing a solvent by vaporization is executed, an upper surplus part of a resin layer is removed by dry etching and the surface layer part of the residual resin layer is removed by wet etching gas then cured. CONSTITUTION:An Al wiring 2 is formed on a substrate 1 and they are coated with a PSG interlayer insulation film 3. An organic SOG film 4 is applied for flattening thereon and prebake is executed, so as to remove a solvent in the SOG film 4 by volatalization. Next, dry etching is executed to etch back the SOG film 4 until the upper surface of the insulation film 3 is exposed from the surface thereof, and an SOG film 4' is left only in a recessed part. Next, wet etching with a buffered fluorine acid is executed to remove the surface layer of the residual SOG film 4' by about 300 Angstrom (200 Angstrom or above). Then, a curing treatment is executed to cure the residual SOG film 4', and thereby a flattening processing is completed.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of the manufacturing method of semiconductor devices, especially the planarization method between multilayer wiring layers, the generation of cracks in the residual resin layer after full-surface dry etching is prevented regardless of the aspect ratio of the wiring. The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can perform planarization by applying a planarizing resin material onto a substrate, and a process in which a pre-evaporator is used to evaporate and remove the solvent in the applied resin. In the method for manufacturing a semiconductor device, the planarization process includes a step of performing a planarization process, a step of removing the upper surplus portion of the prebaked resin layer by dry etching, and a step of curing the residual resin layer after removing the dry etch. After etching, the surface layer portion of the residual resin layer is removed by wet etching, and then the curing is performed.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for planarizing between multilayer wiring layers.

[Conventional technology]

Many of the semiconductor devices currently in use have a multilayer wiring structure, and it is extremely important to ensure a high level of interlayer flatness in their manufacture.

In other words, when forming another wiring layer above a certain wiring layer, a layer of resin or the like is formed on the surface of the lower layer so that the level difference in the lower layer does not adversely affect the deposition of the upper layer. The upper layer is formed after the steps are eliminated, that is, flattened.

The flattening resin material is applied to the substrate in a fluid state dissolved in a solvent, and after pre-baking (heating to about 100°C, for example) to evaporate the solvent, it is cured (
cure) processed. The planarization resin layer formed in this manner requires a certain degree of thickness in order to achieve effective planarization.

However, on the other hand, leaving a thick resin layer between wiring layers
There are problems in ensuring the reliability of the semiconductor device due to cracks occurring during curing of the resin layer, through-hole contacts, and the like.

Conventionally, in order to solve the above problem, after coating and pre-baking, the upper excess portion of the resin layer is removed by dry etching the entire surface, leaving the resin only in the recesses between the wirings, and then hardening is performed. The planarization was made possible with a small amount of residual resin.

FIGS. 3(a) to 3(d) show a conventional method of dry etching the entire surface. In FIG. 1A, a substrate 1 to be subjected to a planarization process has an Aβ wiring 2 formed thereon and covered with an interlayer insulating film 3.

A flattening resin material 4 is applied thereon and prebaked as shown in FIG. 4(b). Next, as shown in FIG. 2C, the entire surface is dry-etched until the surface becomes flat. By performing dry etching on the entire surface in this way, the resin layer 4', which is thinner than that shown in FIG. 4B, is hardened, thereby suppressing the occurrence of cracks in the resin layer.

However, as the aspect ratio of interconnects increases with the increase in the density of semiconductor devices, the amount of resin remaining in the recesses between interconnects increases. As shown in Figure 2, it has become impossible to prevent the occurrence of cracks 5 during the hardening process.

[Problem to be solved by the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can flatten the remaining resin layer after dry etching the entire surface by preventing cracks from occurring, regardless of the aspect ratio of the wiring.

[Means to solve the problem]

According to the present invention, the above objects include a step of applying a flattening resin material on a substrate, a step of performing a prebater to evaporate and remove the solvent in the applied resin, and an upper surplus of a prebaked resin layer. In a method for manufacturing a semiconductor device that includes a step of removing a portion by dry etching and a step of curing the residual resin layer after the dry etching, the surface layer portion of the residual resin layer is removed after the dry etching. This is achieved by a method of manufacturing a semiconductor device characterized in that the above-mentioned curing is performed after removal by wet etching.

The inventors of the present invention investigated in detail the properties of the resin layer remaining in the recesses after dry etching the entire surface, and found that the surface layer of the residual resin layer was significantly altered compared to the surface of the resin layer before dry etching.

FIG. 2 shows an example of the results of measuring the wettability to water at various depths from the surface of the resin layer. The flattening resin used was organic SOG (spin-on glasses).
It is a co-hydrolyzate of methyltrialkoxysilane and tetraalkoxysilane. The above SOG was spin-coded onto a Si substrate to a thickness of about 5,000 mm, and then heated at 120° C. as a precursor for measurement. Full-surface dry etching is C.
The above prebaked S00 was etched by reactive ion etching using F4+CHF3 as an etchant.
The top 2000A of the layer was removed. The contact angle of water was measured for the samples subjected to the above-mentioned whole surface dry etching and the prebaked samples that were not subjected to the whole surface dry etching, after etching was removed from the surface to each depth shown in the figure with diluted hydrochloric acid. From Figure 2, in this example it is approximately 30 meters from the surface.
It can be seen that up to the depth of 0, the quality has changed due to the influence of dry etching on the entire surface.

Although the details of this altered layer are not yet fully clear, it is highly likely that this is a region where the organic SOG is oxidized during reactive ion etching, increasing the number of hydroxyl groups and increasing the contact angle with water. It is thought that the altered layer, which has properties significantly different from the surrounding resin, is the source of cracks during curing.

Therefore, the present inventor focused on this deteriorated layer and discovered that cracks in the resin can be prevented by removing the deteriorated layer by wet etching, which does not have a substantial effect on the resin that is the object of etching, and has developed the present invention. It has been completed.

[For production]

According to the method of the present invention, the aspect ratio of the wiring can be adjusted by removing the deteriorated layer, which is the source of cracks, on the surface layer of the residual resin layer after prebeta by wet etching, which does not substantially affect the properties of the resin. Prevents cracks in the resin without twisting.

Hereinafter, the present invention will be explained in more detail with reference to Examples.

〔Example〕

According to the present invention, planarization was performed by the procedure shown in FIGS. 1(a) to 1(d). FIG. 1(a) shows the state of a substrate to be subjected to planarization treatment. Aj7 wiring 2 with a thickness of 1 μm is formed on the substrate 1 by sputtering, and then CVD is performed on it.
It is then covered with a PSG interlayer insulating film 3 having a thickness of 0.8 μm.

In the process shown in FIG. 1(b), an organic SOG film 4 made of a cohydrolyzate of methyltrialkoxysilane and tetraalkoxysilane dissolved in a solvent is coated on the insulating film 3 of the substrate using a spin cord to reduce the thickness of the flat part. and 0.5μm (=50
00 people). After coating, a prebater was performed to heat the film at 120° C. for 2 minutes to volatilize and remove the solvent in the SOG film 4.

In the process shown in Figure 1 (C), CF4+C is used as an etchant.
Perform dry etching using reactive ion etching using HF3 mixed gas, and etch back about 0.8 μm from the surface of the SOG film 4 until the top surface of the insulating film 3 is exposed, leaving 4° of the SOG film only in the recessed part. I let it happen.

In the step of Figure 1(d), buffered butonic acid (0.5%
Wet etching was performed using HF) for 150 seconds to remove approximately 300 portions of the surface layer of the remaining SOG film. Although the wet etch depth is emphasized in the figure, this amount of wet etch does not substantially affect the flatness.

Next, a curing process was performed by holding the film at 450° C. for 30 minutes in a nitrogen gas atmosphere to harden the remaining SOG film 4' and complete the planarization process.

The surface of the residual SOG film 4° subjected to the planarization process was observed using a scanning electron microscope, and it was confirmed that no cracks were generated.

[Conventional example]

For comparison, after the dry etching shown in FIG. 1(C) was performed according to the conventional method, a curing process was performed without performing the wet etching shown in FIG. 1(d). Other processing steps were performed under the same conditions as in the example to complete the planarization process.

When the surface of the planarized residual SOG film 4' was observed using a scanning electron microscope, it was found that many cracks had occurred.

In the above embodiment, the surface layer of the residual SOG film 4' is approximately 30 mm thick.
Although 0 people were removed, it was confirmed that cracks could be substantially prevented by removing about 200 people.

〔Effect of the invention〕

As explained above, according to the present invention, even if the aspect ratio of the wiring is increased, cracks can be prevented from occurring in the residual resin layer after the entire surface is dry-etched, and flattening can be performed.
A high-density, high-aspect-ratio semiconductor device having multilayer wiring can be manufactured stably with high reliability.

[Brief explanation of drawings]

Figures 1 (a) to (d) are cross-sectional views showing an example of the planarization procedure according to the present invention, and Figure 2 shows the wettability of the surface layer of the flattened resin layer before and after dry etching. The graph showing the results of measuring the properties and FIGS. 3(a) to 3(d) are cross-sectional views showing the conventional planarization procedure. 1: Substrate, 2: Wiring, 3: Interlayer insulation film, 4, 4'
: Flattened resin film, 5: Crack. (a) F (b) Figure Figure (C1> (b) (C) (d) Figure

Claims (1)

[Claims] 1. A step of applying a flattening resin material onto a substrate, a step of pre-baking to evaporate the solvent in the applied resin, and a step of drying the upper excess portion of the pre-baked resin layer. In a method for manufacturing a semiconductor device that includes a step of removing by etching and a step of curing the residual resin layer after the dry etching, after the dry etching, the surface layer of the residual resin layer is wet etched. A method for manufacturing a semiconductor device, comprising performing the above-mentioned curing after removal. 2. The method of manufacturing a semiconductor device according to claim 1, wherein organic SOG is used as the planarizing resin material, and a hydrofluoric acid etchant is used in the wet etching. 3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the wet etching removes a surface layer of the residual resin layer to a thickness of 200 Å or more.