JPH0273652A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the overetching of a coating film opened with a recess, and to easily form an interlayer insulating film having excellent flatness by forming a silicon oxide film including impurity on the silicon oxide film, then forming a coating layer, and etching back it. CONSTITUTION:An aluminum interconnection 3 having a predetermined thickness is formed in a predetermined pattern on the insulating film 2 of a semiconductor substrate 1. A silicon oxide film 4 is formed by a plasma CVD method on the whole surface, and a silicon oxide film (PSG) 5 including impurity is formed thereon by a normal pressure plasma CVD method. Then, after the whole surface is coated with organic siloxane polymer solution, it is baked to form an organic siloxane polymer layer 6. Thereafter, the whole surface is etched by reactive ion etching using CF4, etc., a silicon oxide film 7 is eventually formed on a whole surface by a plasma CVD method, the film 5 having equal etching rate to that of the film 6 is formed, and the overetching of the layer 6 between aluminum interconnections 3a and 3b is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device in which an interlayer insulating film is planarized.

[Conventional technology]

In recent years, with the miniaturization and multilayering of wiring in semiconductor devices, flattening between wiring layers has become important. The coating method, which is one of the planarization methods, involves growing an oxide film (CVD oxide film) on metal wiring using a vapor phase growth method, and then using silicate glass (silica film) or organic siloxane, which is formed by coating and baking. A polymer is formed, and a CVD oxide film is further grown on the polymer to form a wiring interlayer film.

That is, as shown in FIG. 3, a silicon oxide film 4 is grown as an insulating film between the eyebrows on an aluminum wiring 3 formed on an insulating film 2 of a semiconductor substrate 1, and an organic siloxane polymer 6 is applied thereon and baked. Formed by Then, a silicon oxide film 7 is formed thereon.

In this method, as the thickness of the coating film increases, the exposed area of the coating film at the through-hole opening increases, and when sputtering aluminum for upper layer wiring, the coating film is removed.

Outgas from the aluminum causes poor adhesion of aluminum. To avoid this, there is a method of etching back the entire surface to remove the coating film at the opening of the through hole.

That is, as shown in FIG. 4, after the organic siloxane polymer 6 is applied, the entire surface is etched and banked to leave the organic siloxane polymer 6 only in the recesses, and then the silicon oxide film 7 is grown thereon.

[Problem to be solved by the invention]

In the above-described conventional method for manufacturing an interlayer film for a semiconductor device, since the unevenness of the lower pattern causes a difference in the thickness of the coating film on the wiring, it is necessary to perform etching back until the thickest part is removed. A certain amount of over-etching is necessary, taking into consideration the film thickness and uniformity of etching to ensure a margin.

On the other hand, the etching rate of silica films and organic siloxane polymers is about twice as fast as that of oxide films, so in areas where the coating film is thin, that is, in fine wiring areas, the coating film is likely to be over-etched as shown in Figure 4. For this reason, there is a problem in that flatness deteriorates.

In this case, the insulating film between the eyebrows is a silicon nitride film, PSG (phosphorous glass), or BSG (boron glass).

If a silicon oxide film containing impurities such as BPSG (borophosphorus glass) is used, the etching rate ratio can be reduced to approximately 1.
:1, but when a silicon nitride film is grown on aluminum, it becomes susceptible to stress migration, and the glabellar capacitance increases due to the high dielectric constant. In addition, with a silicon oxide film containing impurities, it is difficult to grow the oxide film at a low temperature, so there is a problem that hillocks occur in the aluminum wiring.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the above-mentioned problems and form a glabellar insulating film with excellent flatness.

[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes a step of forming a silicon oxide film on a metal wiring layer formed on a substrate, and a step of forming a silicon oxide film containing impurities on the silicon oxide film. a step of forming a film on the silicon oxide film, a step of flattening the surface by forming a coating film having approximately the same etching rate as the silicon oxide film, and a step of flattening the surface of the silicon oxide film so that at least the silicon oxide film containing impurities on the metal wiring layer is exposed. The method includes a step of etching back the coating film until it is completely etched, and a step of forming a silicon oxide film on the entire surface to complete the glabellar insulating film.

[Effect]

In the above manufacturing method, when etching back the coating film, the silicon oxide film containing impurities having the same etching rate as the coating film is etched at the same time, so over-etching of the coating film in the recessed portions is suppressed and planarization is achieved.

(Example) Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(d) are longitudinal sectional views showing an embodiment of the present invention in the order of steps.

First, as shown in FIG. 1(a), the insulating film 2 of the semiconductor substrate 1 is
An aluminum wiring 3 having a thickness of 1.0 am is formed thereon in a desired pattern. Then, 2,000 silicon oxide films 4 are grown on the entire surface using the plasma CVD method, and on top of this, 4,000 silicon oxide films containing impurities, here PSG films 5, are grown using the atmospheric pressure plasma CVD method.

Next, as shown in FIG. 1(b), an organic siloxane polymer solution is applied to the entire surface and fired to form an organic siloxane polymer layer 6. At this time, due to the pattern dependence of the coating film thickness, the film thickness of the organic siloxane polymer layer 6 is
There are about 1,000 people on the top, and about 3,000 people on the wide wiring 3b.

Next, as shown in FIG. 1C, the entire surface is etched back using, for example, CF4 or active ion etching. At this time, organic siloxane polymer and PSG
The etching rate ratio is set to 1:l.

If the amount of etching back is 4000, over-etching will occur on the wiring 3a by about 1000, and the organic siloxane polymer layer 6 in this area will be completely removed. Further, although over-etching occurs by about 3000 layers on the wiring 3b, the flatness does not deteriorate because it does not reach the silicon oxide film 4.

Finally, as shown in Figure 1(d), plasma CVD is applied to the entire surface.
An interlayer insulating film is formed by growing 5,000 silicon oxide films 7 using the method.

According to this method, by forming the PSG film 5 having the same etching rate as the organic siloxane polymer layer 6, it is possible to form the organic siloxane polymer layer on the wirings 3a and 3b in the same manner as if the organic siloxane polymer layer was applied to this area by the PSG film 5. It becomes a state. As a result, over-etching of the organic siloxane polymer layer 6 between the wirings 3a and 3b is suppressed, and planarization can be realized as a whole.

It goes without saying that a highly reliable multilayer wiring can be formed by etching hacking without exposing the coating layer on the side surface of the opening.

FIG. 2 is a longitudinal cross-sectional view for explaining another embodiment of the present invention.

In this embodiment, a silicon oxide film 4A is grown on the aluminum wiring 3 by bias sputtering, and then a PSG film 5A is grown as in the first embodiment. An organic siloxane polymer layer 6 is formed, the entire surface is etched, and finally plasma C
Silicon oxide film 7 is grown using the VD method.

In this method, by forming the silicon oxide film 4A on the aluminum wiring 3 by bias sputtering, the stepped portions of the aluminum wiring 3 are tapered, and the overall flatness can be improved.

Furthermore, even if the amount of etching back of the siloxane polymer layer 6 is set to be large enough to completely remove the PSG film 5 on the fine wiring 3a, the flatness will deteriorate due to the taper of the underlying silicon oxide film 4A. Never.

Although an example using a bias sputtering method is shown here, it goes without saying that a similar effect can be obtained by using a growth method such as a bias plasma CVD method that provides a tapered portion at the step portion. Moreover, the same effect can be obtained by using an inorganic silica film instead of the above-mentioned organic siloxane polymer or by applying it multiple times.

〔Effect of the invention〕

As explained above, in the present invention, a silicon oxide film containing impurities is formed on a silicon oxide film, and then a coating film is formed, and this is hacked by etching, so over-etching of the coating film in the recessed portions is suppressed. However, it is possible to obtain an interlayer film with good flatness that maintains the shape after the coating film is formed. Further, since the silicon oxide film containing impurities is not grown directly on the aluminum wiring, defects such as hillocks and stress migration are not caused, and a highly reliable semiconductor device can be obtained.

[Brief explanation of the drawing]

FIGS. 1(a) to (a) are longitudinal sectional views showing one embodiment of the present invention in the order of manufacturing steps, FIG. 2 is a longitudinal sectional view of a part of the process of another embodiment of the present invention, and FIGS. FIG. 4 is a longitudinal sectional view showing different conventional methods. 1... Semiconductor substrate, 2... Insulating film, 3.3a, 3b
...Aluminum wiring, 4...Silicon oxide film, 4
A... Silicon oxide film by bias sputtering, 5.
...PSG film, 6...organosiloxane polymer layer, 7
...Silicon oxide film. Figure 1 Figure ■ Figure 2 Figure 4- Figure 4

Claims (1)

[Claims] 1. A process of forming a silicon oxide film on the metal wiring layer formed on the substrate, a process of forming a silicon oxide film containing impurities on this silicon oxide film, and a process of substantially etching this silicon oxide film. forming a coating film with an equal rate to flatten the surface; etching back the coating film until at least the silicon oxide film containing impurities on the metal wiring layer is exposed; and etching back the silicon oxide film on the entire surface. 1. A method of manufacturing a semiconductor device, comprising the step of forming an interlayer insulating film.