JP2606315B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which an interlayer insulating film is planarized.

[Conventional technology]

2. Description of the Related Art In recent years, with miniaturization and multilayering of wiring of a semiconductor device, planarization between wiring layers has become important. The coating method, which is one of the planarization methods, is to grow an oxide film (CVD oxide film) on a metal wiring by a vapor phase growth method, and form a silicate glass (silica film) or an organic siloxane formed by coating and firing. A polymer is formed, and a CVD oxide film is grown thereon to form a wiring interlayer film.

That is, as shown in FIG. 3, a silicon oxide film 4 is grown as an interlayer insulating film on an aluminum wiring 3 formed on an insulating film 2 of a semiconductor substrate 1, and an organic siloxane polymer 6 is applied thereon. It is formed by firing. Then, a silicon oxide film 7 is formed thereon.

In this method, when the thickness of the coating film is large, the exposed area of the coating film in the through-hole opening becomes large, and when sputtering aluminum for the upper layer wiring, outgassing from the coating film causes poor adhesion of aluminum. In order to avoid this, there is a method of etching back the entire surface to remove the coating film at the through hole opening.

That is, as shown in FIG. 4, after applying the organic siloxane polymer 6, the entire surface is etched back to leave the organic siloxane polymer 6 only in the concave portion, and then the silicon oxide film 7 is grown thereon.

[Problems to be solved by the invention]

In the above-described conventional method for manufacturing an interlayer film of a semiconductor device, since a difference occurs in the coating film thickness on the wiring due to the unevenness of the lower pattern, etching back must be performed until the thickest portion disappears. Further, a certain degree of over-etching is necessary in consideration of a margin from the film thickness and the uniformity of etching.

On the other hand, since the etching rate of the silica film or the organic siloxane polymer is about twice as fast as that of the oxide film, the coating film is liable to be over-etched as shown in FIG. Therefore, there is a problem that flatness is deteriorated.

In this case, if a silicon nitride film or a silicon oxide film containing impurities such as PSG (phosphorus glass), BSG (boron glass), and BPSG (boron phosphorous glass) is used for the interlayer insulating film,
Although the etching rate ratio can be made approximately 1: 1, the growth of a silicon nitride film on aluminum is susceptible to stress migration, and the interlayer capacitance is increased due to the high dielectric constant. Further, in the case of a silicon oxide film containing impurities, it is difficult to grow the oxide film at a low temperature, so that there is a problem that hillocks occur in the aluminum wiring.

An object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming an interlayer insulating film having excellent flatness by solving the above-mentioned problems.

[Means for solving the problem]

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a first silicon oxide film on a metal wiring layer formed on a substrate in close contact therewith, and including an impurity on the first silicon oxide film A step of forming a second silicon oxide film, a step of forming a coating film having substantially the same etching rate on the second silicon oxide film to flatten the surface thereof, The method includes a step of etching back the coating film at least until it is exposed, and a step of forming a third silicon oxide film on the entire surface to complete an interlayer insulating film.

[Action]

In the above-described manufacturing method, when the coating film is etched back, the silicon oxide film containing impurities having the same etching rate as that of the coating film is simultaneously etched, so that overetching of the coating film in the concave portion is suppressed and flattening is realized.

Embodiment Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (d) are longitudinal sectional views showing one embodiment of the present invention in the order of steps.

First, as shown in FIG. 1A, an aluminum wiring 3 having a thickness of 1.0 μm is formed in a required pattern on an insulating film 2 of a semiconductor substrate 1. Then, a silicon oxide film 4 is grown on the entire surface by a plasma CDV method at 2000 °, and a silicon oxide film containing impurities, here a PSG film 5 is grown thereon by a normal pressure plasma CVD method at a temperature of 4000 °.

Next, as shown in FIG. 1B, an organic siloxane polymer solution is applied to the entire surface and baked to form an organic siloxane polymer layer 6. At this time, the thickness of the organic siloxane polymer layer 6 is reduced due to the pattern dependence of the coating thickness.
The above is about 1000 mm, and about 3000 mm on the wide wiring 3b.

Next, as shown in FIG. 1C, the entire surface is etched back by reactive ion etching using, for example, CF ₄ . At this time, the etching rate ratio between the organosiloxane polymer and PSG is set to be 1: 1. Assuming that the etching back amount is 4000 mm, about 1000 on wiring 3a
オ ー バ is over-etched, and the organic siloxane polymer layer 6 in this region is completely removed. Further, overetching of about 3000 ° is performed on the wiring 3b, but does not reach the silicon oxide film 4, so that the flatness does not deteriorate.

Finally, as shown in FIG.
An interlayer insulating film is formed by growing silicon oxide film 7 at 5000.degree.

According to this method, the PSG film 5 having the same etching rate as that of the organic siloxane polymer layer 6 is formed, so that the organic siloxane polymer layer is coated on the wirings 3a and 3b by the PSG film 5 in this region. State. Thereby, over-etching of the organic siloxane polymer layer 6 between the wirings 3a and 3b is suppressed, and planarization as a whole can be realized.

It goes without saying that a highly reliable multilayer wiring can be formed without exposing the coating film layer on the side surface of the opening by etching back.

FIG. 2 is a longitudinal sectional view for explaining another embodiment of the present invention.

In this embodiment, after a silicon oxide film 4A is grown on the aluminum wiring 3 by a bias sputtering method, a PSG film 5 and an organic siloxane polymer layer 6 are formed as in the first embodiment, and the entire surface is etched back. Finally, a silicon oxide film 7 is grown by using a plasma CVD method.

In this method, the silicon oxide film 4A formed on the aluminum wiring 3 is formed by the bias sputtering method, so that the step portion of the aluminum wiring 3 is tapered, and the overall flatness can be improved.

Further, even when the etching back amount of the organic siloxane polymer layer 6 is set to be relatively large and the PSG film 5 on the fine wiring 3a is completely removed, the flatness is deteriorated due to the taper of the underlying silicon oxide film 4A. There is no.

Although an example using the bias sputtering method has been described here, it goes without saying that a similar effect can be obtained by a growth method having a taper at a step portion such as a bias plasma CVD method. Similar effects can be obtained by using an inorganic silica film instead of the above-mentioned organic siloxane polymer, or by coating it multiple times.

〔The invention's effect〕

As described above, according to the present invention, since the coating film is formed after forming the silicon oxide film containing impurities on the silicon oxide film and etching back the coating film, over-etching of the coating film in the concave portion is suppressed. In addition, it is possible to obtain an interlayer film having good flatness while maintaining the shape after the formation of the coating film. In addition, since a silicon oxide film containing impurities is not directly grown on the aluminum wiring, defects such as hillocks and stress migration do not occur.
A highly reliable semiconductor device can be obtained.

[Brief description of the drawings]

1 (a) to 1 (d) are longitudinal sectional views showing one embodiment of the present invention in the order of manufacturing steps, FIG. 2 is a longitudinal sectional view showing a part of the steps of another embodiment of the present invention, FIGS. FIG. 4 is a longitudinal sectional view showing different conventional methods. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Insulating film, 3, 3a, 3b ... Aluminum wiring, 4 ... Silicon oxide film, 4A ... Silicon oxide film by bias sputtering, 5 ... PSG film, 6 ... Organic siloxane Polymer layer 7, silicon oxide film.

Claims (1)

(57) [Claims] A step of forming a first silicon oxide film on and in close contact with a metal wiring layer formed on a substrate; and a step of forming a second silicon oxide film containing impurities on the first silicon oxide film. A step of forming a film, a step of forming a coating film having substantially the same etching rate as the second silicon oxide film on the second silicon oxide film to flatten the surface, and at least exposing the second silicon oxide film. A method of manufacturing a semiconductor device, comprising: a step of etching back the coating film; and a step of forming a third silicon oxide film on the entire surface to complete an interlayer insulating film.