JPS5897848A - Smoothing method for surface - Google Patents
Smoothing method for surfaceInfo
- Publication number
- JPS5897848A JPS5897848A JP19742381A JP19742381A JPS5897848A JP S5897848 A JPS5897848 A JP S5897848A JP 19742381 A JP19742381 A JP 19742381A JP 19742381 A JP19742381 A JP 19742381A JP S5897848 A JPS5897848 A JP S5897848A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- coating
- film
- dry etching
- smoothing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009499 grossing Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title claims description 8
- 238000001312 dry etching Methods 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 claims abstract description 6
- 239000011248 coating agent Substances 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 239000004447 silicone coating Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 239000011229 interlayer Substances 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 102200008771 rs121918549 Human genes 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本！１Ｉｊｉ社、多層配線の一部に多結晶層を用いたり
、半導体結晶に凹部を設けたことによる半導体装置表面
の凹凸を平滑化する方法に関するものである。[Detailed description of the invention] Book! 1Iji Co., Ltd., relates to a method for smoothing unevenness on the surface of a semiconductor device caused by using a polycrystalline layer as part of a multilayer interconnection or by providing a recessed portion in a semiconductor crystal.
多結晶層を用いた従来の多層配線について示せば、第１
図ＣＧ）に示す様に、半導体結晶１０上の酸化Ｊ［１１
の上に多結晶層１２ｔ、さらにその上に層間絶縁膜１３
ｔ−形成すると、多結晶層１２の側面は急使になり（微
細加工上急使にならざるｔ得ない］、かつＯｖＤ法等に
よる層間絶縁膜もステップカバーが充分でないので、こ
３６の上ＫＡｔ等金属膜１４を堆積し選択エッチすると
、側面がうすくなったシ、図中矢印で示す如（段切れを
生じてしまう。Regarding conventional multilayer wiring using polycrystalline layers, the first
As shown in Figure CG), oxidized J[11
A polycrystalline layer 12t is formed on top of the polycrystalline layer 12t, and an interlayer insulating film 13 is further formed on top of the polycrystalline layer 12t.
When T- is formed, the side surface of the polycrystalline layer 12 becomes a courier (it cannot help but become a courier due to microfabrication), and the interlayer insulating film formed by the OvD method etc. does not provide sufficient step cover. When a metal film 14 such as KAt is deposited and selectively etched, the side surfaces become thinner and breakage occurs as shown by the arrow in the figure.
従来、こｒＬｔ改善するため、酸化Ｍｌｌや層間絶縁１
［１３上に塗布隊化膜１５ｔ−スピン＝−トして表面を
平滑化していた。塗布酸化膜ＩＳは、ｏｃｎや丁キエス
ピン、スピン、ライト等の商品名ｔもり塗布剤で、２０
Ｇ−１０００′ｃ程度の熱処理で酸化膜となる。この中
には、不純物を含まな−もの中、リン等の不純物を含む
ものがＴｏ９、目的により使いわけらｎている。冨１５
１ＩＣ＆）に示テ如（、塗布酸化Ｑ １５ Ｋより表面
は平滑化さｎ１金属膜１４の段切扛も改善さｎる。しか
しながら、一般に塗布酸化膜１５ｒｊ熱酸化嘆やＯＶＤ
酸化膜に比しエッチ速度えば、多結晶層１２上の層間絶
縁膜１３や塗布酸化膜１５に開孔を設け、金属Ｊ［１４
と多結晶層１２ｔ−ｊｉｉ！！続する場酋、通常のフォ
トプロセスでレジスト上マスタに多結晶層【２上に開孔
を設は様とすると塗布酸く、多結晶層１２の側面もエッ
チさｎてしまい結果的に表面平滑化の効果なくなってし
まうこ、とがしばしばある。Conventionally, in order to improve this rLt, oxidation Mll and interlayer insulation 1
[13 was coated with a plated film 15t-spun to smooth the surface. The coating oxide film IS is a coating agent with a trade name such as ocn, chokiespin, spin, light, etc.
It becomes an oxide film by heat treatment of about G-1000'c. Among these, among those that do not contain impurities, those that contain impurities such as phosphorus are classified as To9 depending on the purpose. Tomi 15
As shown in 1IC&), the surface is smoother and the step-cutting of the metal film 14 is improved by coating oxidation Q15K. However, in general, thermal oxidation or OVD coating oxide film 15rj
If the etch rate is higher than that of the oxide film, openings are formed in the interlayer insulating film 13 on the polycrystalline layer 12 and the coated oxide film 15, and the metal J[14
and polycrystalline layer 12t-jii! ! Next, if you try to make holes on the polycrystalline layer [2] on the resist using a normal photo process, the coating will be acidic and the sides of the polycrystalline layer 12 will also be etched, resulting in a smooth surface. It often happens that the effect of the change is lost.
本実開拡上述の問題を改善するためになさｎたもので塗
布酸化膜形成後少なく加工の必要な部分の塗布酸化膜を
除去して、下地の加工しやすい酸化膜中層間絶縁膜を露
出すると共に、平滑化に効果ある段差底部や側面の塗布
酸化膜を残すものである。塗布酸化膜の除去は、Ｈ？等
のウエットエツナによっても可能であるがエッチ速度が
著しく高いので制御が困ｍなため、プラズマエッチ、反
応性イオンエッチ、イオンエッチ等のドライエッチで行
なうことが望ましい。以下に図面を用いて本実明管詳述
する。１１２図に）には、半導体結晶１０上のａ＋ｔＩ
ｇｘｔ上に多結晶層１２、層間絶縁ｆｉ１３’ｉ形成し
た後、塗布酸化ＷＸ１５を堆積した断面を示す。This practical development was done in order to improve the above-mentioned problem, and after forming the coated oxide film, remove the coated oxide film in the parts that require less processing to expose the underlying oxide film and interlayer insulating film, which is easy to process. At the same time, it leaves an applied oxide film on the bottom and side surfaces of the step, which is effective for smoothing. Is it possible to remove the applied oxide film using H? Although this is possible with a wet etcher such as, the etch rate is extremely high and difficult to control, it is preferable to use dry etching such as plasma etching, reactive ion etching, or ion etching. This actual tube will be explained in detail below using the drawings. 112), a+tI on the semiconductor crystal 10
A cross section is shown in which a coating oxide WX15 is deposited after forming a polycrystalline layer 12 and interlayer insulation fi13'i on gxt.
その後、第２図（６）に示す様に全面をドライエッチ雰
囲気でエッチして塗布酸化膜１５のうすい部分ｔ、除去
し、かつ平滑効果のある部分を残し、加工の必要な層間
絶縁膜１３もしくは酸化１［１１・を露出する、ドライ
エッチは、例見ば０１番と０−の混曾ガス（０，２０〜
８０％）で行なうと、塗布酸化膜と熱酸化層のエッチ速
度比は約４＝１以上にとｎｌま九〇ＶＤ酸化膜に対して
は約３：１以上にとれるので、この全面エッチの際層間
絶嶽ｇＸ１３や酸化膜１５の除去のさｎ方は少ない、こ
の後＠２図（ｅ）の如く多結晶層１２上の開孔や、必要
に応じ酸化ｊｌ［１１の加工は、塗布酸化膜がないため
非常に行ないやすくな）、第１図（６）の様な問題はな
くなった。Thereafter, as shown in FIG. 2(6), the entire surface is etched in a dry etching atmosphere to remove the thin part t of the applied oxide film 15, leaving a smoothing part, and leaving the interlayer insulating film 13 that needs processing. Alternatively, dry etching to expose oxidized 1[11.
80%), the etch rate ratio between the coated oxide film and the thermal oxide layer is about 4=1 or more, and for the nl to 90VD oxide film, it is about 3:1 or more. There is little time to remove the interlayer gap gX13 and the oxide film 15.After this, as shown in Figure 2(e), holes are formed on the polycrystalline layer 12, and processing of oxidation layer [11] is performed as necessary. Since there is no oxide film, it is very easy to carry out), and the problem as shown in Fig. 1 (6) is eliminated.
他の本発明例について述べる。塗布酸化膜とｒＢＧ（リ
ンを数ｔｓ〜１０５Ｇ程度含む酸化膜）のエッチ速度比
は約２＝１以下になるので、層間絶縁膜１３や酸化ｇＸ
１１の少なく共表面部ＱＦ８Ｇで形成した後、塗布酸化
Ｍｌ［］５ｔ−堆積し全面ドライエッチを行なえば、第
３図の如くほぼ塗布酸化膜１５０表面形状のｔま７８Ｇ
が露出さｎるので、表面平滑化効果はほとんど失わｎな
い利点がある。Other examples of the present invention will be described. Since the etch rate ratio between the coated oxide film and rBG (an oxide film containing about several ts to 105G of phosphorus) is approximately 2=1 or less, the interlayer insulating film 13 and oxidized gX
After forming the co-surface portion QF8G with a small amount of oxide film 11, if coating oxide Ml [ ] 5t is deposited and dry etching is performed on the entire surface, the surface shape of the coating oxide film 150 is approximately 78G as shown in FIG.
Since the surface is exposed, there is an advantage that almost no surface smoothing effect is lost.
第３図の例は、１’８Ｇに限らず塗布酸化膜の成分や熱
処理条件、層間絶縁膜や酸化膜の形成条件、ドライエッ
チ条件によってもエッチ選択比を適宜制御できるので、
他の材料への応用も可能である。In the example shown in FIG. 3, the etch selectivity can be controlled not only by 1'8G but also by the composition of the applied oxide film, heat treatment conditions, interlayer insulation film and oxide film formation conditions, and dry etching conditions.
Application to other materials is also possible.
ｔた、多層配線のときの平滑化の例を主に述べてきたが
、凹部分離等結晶内に凹Ｗ（もしくは凸部〕のある場酋
、酸化膜等による段差のある場合にも同様ＫＶ効である
。パIn addition, although we have mainly described examples of smoothing in multilayer wiring, KV can also be applied in cases where there are depressions (or protrusions) in the crystal, such as in the case of a depression separation, or in the case where there is a step due to an oxide film, etc. It is effective.
第１図に）〜（Ｃ） ｔ；ｊ：多結晶を用いた多層配線
の従来の方法を示した断面図、第２図（Ｇ）〜（６）は
本発明による平滑方法を多層配９線に適用したときの断
面図、ｔＩＸ３図は本発明の他の実施例を説゛明するた
め断面図である。
１０゜。半導体結晶、１１ 、 、酸化、嘆、１２．、
多結晶層、１３００層間絶縁膜、１４０．金属層、１５
．。
塗布酸化膜
以上
出願人 株式会社第二精工金
代理人 弁理士最上 務
第１図（ａ）
第１図（ｂ）
第１図（Ｃ）
第２図（α）
／−〜ＩＯ
第２図（１７）
第２図（Ｃ）
第３図1) to (C) t;j: Cross-sectional views showing the conventional method of multilayer interconnection using polycrystal, and FIGS. 2(G) to (6) show the smoothing method according to the present invention for A cross-sectional view when applied to a wire, tIX3 is a cross-sectional view for explaining another embodiment of the present invention. 10°. Semiconductor crystal, 11, Oxidation, lamentation, 12. ,
Polycrystalline layer, 1300 interlayer insulating film, 140. metal layer, 15
．． . Coated oxide film Applicant Daini Seikokin Co., Ltd. Agent Patent Attorney Mogami Affairs Figure 1 (a) Figure 1 (b) Figure 1 (C) Figure 2 (α) /-~IO Figure 2 ( 17) Figure 2 (C) Figure 3
Claims (1)
凹’ｇｔ−設けたことによる半導体装置表面の凹凸を塗
布Ｗ１１と硅素屓を塗布して平滑化する方法において、
前記凹凸の表面を酸化膜で被覆した後、前記塗布ａｔ−
塗布、熱処理後、全表面をドライエッチ雰囲気にさらす
ととＫよ）少なく共前記塗布嘆の不要部上前記酸化膜が
露出するまで除去すること１％黴とする表面平滑化方法
。 （乃 少な（共前記酸化膜の表面Ｋｔｌ！ＩＪンを含む
肩が形成されて＊ Ｄ 、前記ドライエッチによって前
記塗布膜と共Ｋ１１ｌ記リンを含む腹の一部も除去さｎ
ることｔＷ徴とする特許請求の範囲第１頂上戦の表面平
滑化方法。(1) In a method of smoothing unevenness on the surface of a semiconductor device due to multilayer wiring using a polycrystalline layer or by providing recesses in a semiconductor crystal by applying coating W11 and silicone coating,
After coating the uneven surface with an oxide film, the coating at-
After coating and heat treatment, the entire surface is exposed to a dry etching atmosphere, and at least 1% of the mold is removed from the unnecessary portions of the coating until the oxide film is exposed. A shoulder containing a small amount of phosphorus (Ktl!
Claim 1: A method for smoothing the surface of a top surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19742381A JPS5897848A (en) | 1981-12-08 | 1981-12-08 | Smoothing method for surface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19742381A JPS5897848A (en) | 1981-12-08 | 1981-12-08 | Smoothing method for surface |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5897848A true JPS5897848A (en) | 1983-06-10 |
Family
ID=16374268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19742381A Pending JPS5897848A (en) | 1981-12-08 | 1981-12-08 | Smoothing method for surface |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5897848A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60231340A (en) * | 1984-04-27 | 1985-11-16 | Sony Corp | Manufacture of semiconductor device |
| JPS61196555A (en) * | 1985-02-26 | 1986-08-30 | Nec Corp | Formation for multilayer interconnection |
| JPS61272951A (en) * | 1985-05-28 | 1986-12-03 | Nippon Gakki Seizo Kk | Forming method of multilayer wiring |
| JPS62295437A (en) * | 1986-06-14 | 1987-12-22 | Yamaha Corp | Forming method for multilayer interconnection |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5214366A (en) * | 1975-07-25 | 1977-02-03 | Hitachi Ltd | Process for production of semiconductor device |
| JPS53104186A (en) * | 1977-02-23 | 1978-09-11 | Hitachi Ltd | Multilayer wiring body |
-
1981
- 1981-12-08 JP JP19742381A patent/JPS5897848A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5214366A (en) * | 1975-07-25 | 1977-02-03 | Hitachi Ltd | Process for production of semiconductor device |
| JPS53104186A (en) * | 1977-02-23 | 1978-09-11 | Hitachi Ltd | Multilayer wiring body |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60231340A (en) * | 1984-04-27 | 1985-11-16 | Sony Corp | Manufacture of semiconductor device |
| JPH0642481B2 (en) * | 1984-04-27 | 1994-06-01 | ソニー株式会社 | Manufacturing method of semiconductor device |
| JPS61196555A (en) * | 1985-02-26 | 1986-08-30 | Nec Corp | Formation for multilayer interconnection |
| JPS61272951A (en) * | 1985-05-28 | 1986-12-03 | Nippon Gakki Seizo Kk | Forming method of multilayer wiring |
| JPS62295437A (en) * | 1986-06-14 | 1987-12-22 | Yamaha Corp | Forming method for multilayer interconnection |
| JPH0587146B2 (en) * | 1986-06-14 | 1993-12-15 | Yamaha Corp |
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