JPS6028237A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6028237A
JPS6028237A JP58137354A JP13735483A JPS6028237A JP S6028237 A JPS6028237 A JP S6028237A JP 58137354 A JP58137354 A JP 58137354A JP 13735483 A JP13735483 A JP 13735483A JP S6028237 A JPS6028237 A JP S6028237A
Authority
JP
Japan
Prior art keywords
film
photoresist
electrode
opening
element region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58137354A
Other languages
Japanese (ja)
Inventor
Hitoshi Kawanabe
川邦辺 均
Kazunobu Shozen
少前 和伸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP58137354A priority Critical patent/JPS6028237A/en
Publication of JPS6028237A publication Critical patent/JPS6028237A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To make the end surface of an opening for fitting an electrode steep by using a laminate of a negative type resist film as a foundation and a positive type resist film as an upper layer as masks when the surface of a semiconductor substrte, to which an element region is formed, is adhered with an SiO2 film and the opening is formed through etching while being made to correspond to the element region. CONSTITUTION:The upper section of a semiconductor substrate 1, to which an element region is shaped through diffusion, is coated with an SiO2 film 2, the whole surface is coated with a negative type resist film 3, and an opening corresponding to the element region is bored through photoetching to expose the film 2 as a film 2'. Since the circumferential wall of the opening takes a tapered shape in a negative type resist at that time, a positive type resist film 4 is formed additionally on the film 3, the film 4 is also attached to the side wall of the opening section through the same treatment, and the opening section is brought to a steep shape. The exposed film 2' is removed through etching, the whole surface is coated with a metallic material 5 for an electrode, and the films 4 and 3 are removed together with the material 5 applied on the films 4 and 3, thus obtaining the electrode 5 having a precise pattern on the element region.

Description

【発明の詳細な説明】 く技術分野〉 本発明は半導体装置の電極形成に関するものであり、特
にリフトオフ法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to the formation of electrodes for semiconductor devices, and particularly relates to a lift-off method.

〈従来技術〉 リフトオフ法とは、半導体基板上にフォトレジストを塗
布して例えば電極パターンを形成しておき、後にフォト
レジスト上及び半導体基板上に電極用金属膜を被着させ
、フォトレジスト上に伺着した不要部分の金属膜をフォ
トレジストの剥離と同時に取り除いて例えば電極を形成
する方法であり、工程が簡単な上、エツチング液を使用
しない為、電極側面のエツチングが無い、という利点等
があって広く利用されている。
<Prior art> The lift-off method is a method in which a photoresist is applied onto a semiconductor substrate to form, for example, an electrode pattern, and then a metal film for electrodes is deposited on the photoresist and the semiconductor substrate, and then a metal film for electrodes is deposited on the photoresist and the semiconductor substrate. This is a method of forming, for example, an electrode by removing the deposited unnecessary metal film at the same time as removing the photoresist.The process is simple, and since no etching solution is used, there is no need to etch the sides of the electrode. It is widely used.

この方法をより効果的にするには、フォトレジスト上に
被着した金属膜と基板上に直接被着した金属膜とがフォ
トレジスト膜厚による段差によって分離している状態が
望ましい。その為フォトレジストは被着しようとルてい
る金属膜厚より厚くする必要がある。特に厚膜電極(1
0μm程度)を必要とする半導体素子の場合、フォトレ
ジスト厚は20μm程度必要となる。
In order to make this method more effective, it is desirable that the metal film deposited on the photoresist and the metal film deposited directly on the substrate be separated by a step difference due to the thickness of the photoresist film. Therefore, the photoresist needs to be thicker than the metal film to be deposited. Especially thick film electrode (1
In the case of a semiconductor device that requires a photoresist thickness of about 0 μm), the photoresist thickness needs to be about 20 μm.

処でネガタイプフォトレジストでレジスト膜厚を、厚く
してパターンを形成した場合、パターン形成後のレジス
ト側面は第1図で示す様にテーパー状になりやすく、そ
の為、金属膜の分離がむずかしくなる。
However, when a pattern is formed by increasing the resist film thickness using a negative type photoresist, the sides of the resist after pattern formation tend to become tapered as shown in Figure 1, making it difficult to separate the metal film. .

第1図において、lは回路素子が形成された半導体基板
で、該基板lの導体被着が必要な電極開口部等を除いて
表面が5i02膜2で被われ、該5i02膜2上にネガ
タイプフォトレジスト3が塗布される。該塗布されたネ
ガタイプフォトレジスト3には電極パターン像が露光続
いて現像され電極開口部2aが形成された後、電極金属
膜5が蒸着等によって形成され、不要部分の金属膜5が
レジスト3の剥離と共に除去される。このようなネガタ
イプフォトレジストでは、予め行なう電極開口部2aの
形成時にレジストの開口端面3aがテーパー状にエツチ
ングされて急峻な段差が得られず、そのために電極部で
の金属膜5の分離が難しいという不都合かある。
In FIG. 1, l is a semiconductor substrate on which circuit elements are formed, and the surface of the substrate l is covered with a 5i02 film 2, except for electrode openings where conductors must be adhered. Photoresist 3 is applied. An electrode pattern image is exposed and developed on the applied negative type photoresist 3 to form an electrode opening 2a, and then an electrode metal film 5 is formed by vapor deposition or the like, and unnecessary portions of the metal film 5 are removed from the resist 3. It is removed with peeling. In such a negative type photoresist, when the electrode opening 2a is formed in advance, the opening end surface 3a of the resist is etched into a tapered shape, making it impossible to obtain a steep step, and therefore it is difficult to separate the metal film 5 at the electrode part. There is an inconvenience.

又、ポジタイプレジストの場合、電極パターン形成後の
レジストの側面はステップ状態ではあるが、、半導体基
板とレジストとの密着が比較的劣る為、エツチングを要
するコンタクト部絶縁膜エッチに適さない欠点があった
。その為、ポジタイプフォトレジストを用いてリフトオ
フを行う場合、第2図(al〜(C)に示す様に、予め
ネガタイプフォトレジスト3を用いてコンタクト部の絶
縁膜2のエツチングを行ない(第2図(a))、次にネ
ガタイプフォトレジスト3を剥離後ポジタイプフォトレ
ジスト4でリフトオフ用のパターンを形成(第2図(b
))L、その後電極となる金属5を被着(第2図(C)
)して、ポジタイプフォトレジスト剥離により第2図(
dlの様な電極5を形成していた。しかしこのような改
良型の工程におG−)でも工程数が多い上に、レジスト
膜厚が一層しか形成されない為必要な膜厚を得るにはな
お充分ではない、という問題があった。
In addition, in the case of positive type resist, although the side surface of the resist after electrode pattern formation is in a step state, the adhesion between the semiconductor substrate and the resist is relatively poor, so it has the disadvantage that it is not suitable for etching the contact insulation film, which requires etching. there were. Therefore, when lift-off is performed using a positive type photoresist, as shown in FIGS. Figure (a)), then after peeling off the negative type photoresist 3, a pattern for lift-off is formed with positive type photoresist 4 (Figure 2 (b)).
)) L, then deposit the metal 5 that will become the electrode (Fig. 2 (C)
) and then peeling off the positive photoresist to create the image shown in Figure 2 (
An electrode 5 like dl was formed. However, even in this improved process G-), there are problems in that the number of steps is large and the resist film is formed only in one layer, which is still insufficient to obtain the required film thickness.

〈発明の目的〉 本発明は従来の欠点を改良したものであり、リフトオフ
法による電極パターン形成時のフォトレジストの剥離作
業を簡単にし、且つ信頼性の高いパターンを得ることが
できる半導体装置の製造方法を提供する。
<Purpose of the Invention> The present invention improves the conventional drawbacks, and provides a method for manufacturing a semiconductor device that simplifies the work of removing photoresist during electrode pattern formation using the lift-off method and can obtain a highly reliable pattern. provide a method.

〈実施例〉 第3図(a+〜(dlは本発明の方法を半導体装置に実
施した工程図を説明するための断面図である。半導体基
板1に半導体素子を形成する為、所定の部分に不純物を
拡散等の工程を施こした後に、基板表面に絶縁膜として
二酸化ケイ素膜2を被着し、続いてネガタイプフォトレ
ジスト3を塗布し、従来のフォトエツチング技術で、例
えば電極に対応するパターンを形成する(第3図(a)
)。
<Example> FIG. 3 (a+ to (dl) are cross-sectional views for explaining process diagrams in which the method of the present invention is applied to a semiconductor device. In order to form a semiconductor element on a semiconductor substrate 1, a predetermined portion is After performing processes such as diffusion of impurities, a silicon dioxide film 2 is deposited as an insulating film on the substrate surface, and then a negative type photoresist 3 is applied, and patterns corresponding to, for example, electrodes are formed using conventional photoetching techniques. (Fig. 3(a))
).

次に先に形成したネガタイプフォトレジスト3のパター
ン上に、第3図(b)に示す如くポジタイプフォトレジ
スト4を塗布し、該ポジタイプフォトレジスト膜4のパ
ターンとしては、ネガタイプフォトレジスト3を覆う形
状になる様なガラスマスクを用いて従来のフォトエツチ
ング技術でパターンを形成する。即ちネガタイプフォト
レジストの欠点であるエツチング端面のテーパ状を補っ
て急峻な端面を形成する。次にコンタクト部の絶縁膜2
′を公知の技術でエツチングし、その後にフォトレジス
ト上及び基板上に電極となるための金属材料5を被着す
る(第3図(C))。次に該半導体基板をフォトレジス
ト剥離剤に浸漬し、ポジタイプレジスト4.ネガタイプ
レジスト3の剥離と同時にフォトレジスト上に被着した
不要部分の金属膜をも除去して、第3図Fdlに示す如
く基板1に被着された電極5を形成する。このとき電極
開口の端面はポジレジストで被われているため急峻にな
っており、レジスト上の金属膜は剥離され易い。
Next, on the pattern of the negative type photoresist 3 formed earlier, a positive type photoresist 4 is applied as shown in FIG. 3(b). A pattern is formed using a conventional photoetching technique using a glass mask that forms a covering shape. That is, the tapered shape of the etched end face, which is a drawback of negative type photoresists, is compensated for and a steep end face is formed. Next, the insulating film 2 of the contact part
' is etched using a known technique, and then a metal material 5 to serve as an electrode is deposited on the photoresist and the substrate (FIG. 3(C)). Next, the semiconductor substrate is immersed in a photoresist stripping agent, and a positive type resist 4. At the same time as the negative type resist 3 is peeled off, unnecessary portions of the metal film deposited on the photoresist are also removed to form electrodes 5 deposited on the substrate 1 as shown in FIG. 3Fdl. At this time, the end face of the electrode opening is steep because it is covered with a positive resist, and the metal film on the resist is easily peeled off.

く効 果〉 以上説明した様に、本発明の方法はネガタイプフォトレ
ジストを下地にしている事から、コンタクト部の絶縁膜
エツチングにも問題は無く、またポジタイプフォトレジ
ストが、ネガタイプフォトレジストを覆うパターン形状
となっている為、全体としてレジスト膜厚は厚く、パタ
ーン形成後のレジスト側面はステップ状態なって、厚膜
電極の場合でも、フォトレジスト上の不要部分の金属膜
と、半導体基板上の残すべき部分の金属膜が分離されや
すく、作業が非常に簡単になってパターン形状の信頼性
も向上する。ざら【こ、ネガタイプフォトレジスト、ポ
ジタイプフォトレジストと2層形状にする為、レジスト
に発生するピンホールも極端に少なくなる利点もある。
As explained above, since the method of the present invention is based on a negative type photoresist, there is no problem in etching the insulating film at the contact area, and the positive type photoresist covers the negative type photoresist. Because of the patterned shape, the overall resist film thickness is thick, and the sides of the resist after pattern formation are in a step state, and even in the case of thick film electrodes, unnecessary parts of the metal film on the photoresist and the metal film on the semiconductor substrate are removed. The portion of the metal film that should be left is easily separated, making the work much easier and improving the reliability of the pattern shape. Because it has a two-layered structure consisting of a negative type photoresist and a positive type photoresist, it also has the advantage of extremely reducing the number of pinholes that occur in the resist.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はネガタイプフォトレジスタを用いた従来の製造
方法を説明するための断面図、第2図(al〜Fdlは
ポジタイプフォトレジスタを用いた場合の従来のリフト
オフ工程図、第3図は本発明の一実施例を説明するため
の工程図である。 に半導体基板、 2.2’:二酸化ケイ素膜。 3:ネガタイプフォトレジスト膜、4:ポジタイプフォ
トレジスト膜、5:電極用金属膜。 代理人 弁理士 福 士 愛 彦(他2名)(bノ 第 (C) 3!2I!
Figure 1 is a cross-sectional view for explaining the conventional manufacturing method using a negative type photoresistor, Figure 2 (al to Fdl is a diagram of the conventional lift-off process when a positive type photoresistor is used, and Figure 3 is a diagram of the present invention). 2 is a process diagram for explaining one embodiment of the invention. 2.2': silicon dioxide film; 3: negative type photoresist film; 4: positive type photoresist film; 5: metal film for electrode. Agent Patent attorney Aihiko Fuku (2 others) (B No. (C) 3!2I!

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁膜で被われた半導体基板上にネガタイプフォト
レジストでパターンを形成する工程と、該パターン上に
ポジタイプフォトレジストを塗布して該ポジタイプフォ
トレジストを対応するパターンにエツチングする工程と
、上記エツチングによって露出した基板表面の絶縁膜を
エツチングする工程と、上記フォトレジストパターン上
及び露出した半導体基板上に金属膜を被着する工程と、
次に残留するフォトレジストを剥離すると同時にフォト
レジスト上の金属膜を除去する工程とからなることを特
徴とする半導体装置の製造方法。
1. A step of forming a pattern using a negative type photoresist on a semiconductor substrate covered with an insulating film, a step of applying a positive type photoresist on the pattern and etching the positive type photoresist into a corresponding pattern, and a step of etching the positive type photoresist into a corresponding pattern. a step of etching an insulating film on the surface of the substrate exposed by etching; a step of depositing a metal film on the photoresist pattern and the exposed semiconductor substrate;
A method for manufacturing a semiconductor device, comprising the steps of: peeling off the remaining photoresist; and simultaneously removing a metal film on the photoresist.
JP58137354A 1983-07-26 1983-07-26 Manufacture of semiconductor device Pending JPS6028237A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58137354A JPS6028237A (en) 1983-07-26 1983-07-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58137354A JPS6028237A (en) 1983-07-26 1983-07-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6028237A true JPS6028237A (en) 1985-02-13

Family

ID=15196692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58137354A Pending JPS6028237A (en) 1983-07-26 1983-07-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6028237A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465337A (en) * 2014-12-03 2015-03-25 复旦大学 Method for manufacturing metal nanometer slit through PMMA/NEB double-layer glue

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465337A (en) * 2014-12-03 2015-03-25 复旦大学 Method for manufacturing metal nanometer slit through PMMA/NEB double-layer glue

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