JPH05283429A - Manufacture of thin film transistor device - Google Patents

Manufacture of thin film transistor device

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Publication number
JPH05283429A
JPH05283429A JP10355592A JP10355592A JPH05283429A JP H05283429 A JPH05283429 A JP H05283429A JP 10355592 A JP10355592 A JP 10355592A JP 10355592 A JP10355592 A JP 10355592A JP H05283429 A JPH05283429 A JP H05283429A
Authority
JP
Japan
Prior art keywords
film
photoresist
channel
conductive film
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10355592A
Other languages
Japanese (ja)
Inventor
Hitoshi Shiraishi
均 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP10355592A priority Critical patent/JPH05283429A/en
Publication of JPH05283429A publication Critical patent/JPH05283429A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To obtain a manufacturing method of a thin film transistor which can form the channel part of a thin film transistor with high reproducibility. CONSTITUTION:A gate Cr electrode 12 is patterned on a glass substrate 10, and continuously an SiN film 11 and an a-Si film 13 are formed (process A). Photo resist 15 is patterned on a channel forming part, and an N<+>-a-Si film 14 is formed by a lift-off method (process B). Photo resist is patterned on a conducting film forming part containing a channel forming part, and the a-Si film 13 and the N<+>-a-Si film 14 except on the conducting film forming part are etched and eliminated at the same time (process C). Photo resist 15 is peeled (process D). After photo resist 18 is again patterned on a channel part 16B, a drain Cr film 16 is formed (process E). The photo resist 18 is peeled and eliminated and the channel part of a thin film transistor is formed (process F).

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、薄膜トランジスタ装置
の製造方法に関し、特に、導電膜中のチャンネル部分の
形成に係り、薄膜トランジスタのチャンネル部を再現性
良く形成する薄膜トランジスタ装置の製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor device, and more particularly, to a method of manufacturing a channel portion in a conductive film, and more particularly to a method of manufacturing a thin film transistor device in which a channel portion of a thin film transistor is formed with good reproducibility.

【0002】[0002]

【従来の技術】従来の薄膜トランジスタ装置において
は、チャンネル部分を形成する方法として、導電膜上に
ドレインCr電極を形成した後、このドレインCr膜を
マスクとしてチャンネル生成部分の導電膜をドライエッ
チングにより所定膜厚分除去する手段が採用されてい
る。
2. Description of the Related Art In a conventional thin film transistor device, as a method of forming a channel portion, a drain Cr electrode is formed on a conductive film, and then the conductive film in a channel generating portion is dry-etched to a predetermined area using the drain Cr film as a mask. Means for removing the film thickness is adopted.

【0003】以下、図3に基づいて薄膜トランジスタの
従来のチャンネル部形成方法を説明する。図3は、従来
の薄膜トランジスタ装置の製造法によるチャネル部分の
形成状況を工程順に示した断面図であつて、まず、図3
工程Aに示すように、ガラス基板10上にCr膜からなる
ゲ−トCr電極12をパタ−ニングした後、プラズマCV
Dにより絶縁膜としてのSiN膜11、導電膜としてのa
−Si膜13及びn+−a−Si膜14を順次堆積する。そ
して、このn+−a−Si膜14及びa−Si膜13をエッ
チングするためのホトレジスト19のマスクをパタ−ニン
グする。
A conventional method for forming a channel portion of a thin film transistor will be described below with reference to FIG. 3A to 3C are cross-sectional views showing, in the order of steps, formation of a channel portion by a conventional method of manufacturing a thin film transistor device.
As shown in step A, after the gate Cr electrode 12 made of a Cr film is patterned on the glass substrate 10, plasma CV is performed.
By D, SiN film 11 as an insulating film and a as a conductive film
The -Si film 13 and the n + -a-Si film 14 are sequentially deposited. Then, the mask of the photoresist 19 for etching the n + -a-Si film 14 and the a-Si film 13 is patterned.

【0004】次に、導電部分のパタ−ン形成を行う。即
ち、図3工程Aの状態でホトレジスト19をマスクにし、
フッ素系の反応性ガスを用いてn+−a−Si膜14及び
a−Si膜13のドライエッチングを行う。図3工程B
は、n+−a−Si膜14及びa−Si膜13をドライエッ
チングによりホトレジスト19の下以外の部分を除去した
後、このホトレジスト19を剥離除去した状態を示す図で
ある。
Next, a pattern of the conductive portion is formed. That is, using the photoresist 19 as a mask in the state of FIG.
The n + -a-Si film 14 and the a-Si film 13 are dry-etched using a fluorine-based reactive gas. Figure 3 Process B
FIG. 6 is a diagram showing a state in which the photoresist 19 is peeled off after the portions of the n + -a-Si film 14 and the a-Si film 13 other than under the photoresist 19 are removed by dry etching.

【0005】続いて、ドレイン電極部分のパタ−ン形成
を行う。即ち、図3工程Bの状態でドレインCr膜16を
スパッタ法により全面に形成した後、図3工程Cに示す
ように、ホトレジスト20をマスクにし、反応性ガスCl
2を用いてチャンネル部分16BのドレインCr膜16のドラ
イエッチングを行う。
Then, a pattern is formed on the drain electrode portion. That is, after the drain Cr film 16 is formed on the entire surface by the sputtering method in the step B of FIG. 3, the photoresist 20 is used as a mask as shown in the step C of FIG.
2 is used to dry-etch the drain Cr film 16 of the channel portion 16B.

【0006】このようにチャンネル部分16Bのドレイン
Cr膜16を除去した後、図3工程Cの状態で同じホトレ
ジスト20をマスクにして、反応性ガスをフッ素系のガス
に切り換え、ドライエッチングによりチャンネル部分16
Bのn+−a−Si膜14を除去し、また、同部分16Bのa
−Si膜13を所定膜厚分だけ除去する。以上の工程を経
た後、ホトレジスト20を剥離除去し、図3工程Dに示す
薄膜トランジスタを形成する。
After removing the drain Cr film 16 of the channel portion 16B in this way, the same photoresist 20 is used as a mask in the state of step C of FIG. 3 to switch the reactive gas to a fluorine-based gas, and dry etching is performed to the channel portion. 16
The n + -a-Si film 14 of B is removed, and a
-Si film 13 is removed by a predetermined thickness. After the above steps, the photoresist 20 is peeled and removed to form the thin film transistor shown in step D of FIG.

【0007】[0007]

【発明が解決しようとする課題】従来の上記した薄膜ト
ランジスタの形成方法では、チャンネル部分16Bの形成
において、a−Si膜13を所定膜厚分除去するという方
法を用いているため、このa−Si膜13のドライエッチ
ングを途中で止めることが必要であり、ドライエッチン
グ速度の基板内均一性を再現性良く保たなければならな
いという問題点がある。また、従来の上記薄膜トランジ
スタの形成方法では、チャンネル部分16Bのa−Si膜1
3がそのままエッチング面であるため、ドライエッチン
グによるプラズマダメ−ジを受けやすいという問題点を
有している。
In the conventional method of forming a thin film transistor described above, a method of removing the a-Si film 13 by a predetermined film thickness is used in the formation of the channel portion 16B. Since it is necessary to stop the dry etching of the film 13 on the way, there is a problem that the uniformity of the dry etching rate within the substrate must be maintained with good reproducibility. In the conventional method of forming a thin film transistor, the a-Si film 1 of the channel portion 16B is used.
Since 3 is the etching surface as it is, it has a problem that it is susceptible to plasma damage due to dry etching.

【0008】そこで、本発明は、上記問題点を解消する
薄膜トランジスタ装置の製造方法を提供することを目的
とする。特に本発明は、チャンネル部分を比較的簡易に
精度良く形成することができ、また、チャンネル部分が
プラズマダメ−ジを受けることがない薄膜トランジスタ
装置の製造方法を提供することを目的とする。更に本発
明は、薄膜トランジスタ装置の製造プロセスを安定化さ
せ、薄膜トランジスタ装置の製品信頼性の向上を図る薄
膜トランジスタ装置の製造方法を提供することを目的と
する。
Therefore, an object of the present invention is to provide a method of manufacturing a thin film transistor device that solves the above problems. In particular, it is an object of the present invention to provide a method of manufacturing a thin film transistor device in which the channel portion can be formed relatively easily and accurately and the channel portion is not subject to plasma damage. A further object of the present invention is to provide a method of manufacturing a thin film transistor device, which stabilizes the manufacturing process of the thin film transistor device and improves the product reliability of the thin film transistor device.

【0009】[0009]

【課題を解決するための手段】そして、本発明は、チャ
ンネル生成部分にレジストをパタ−ニングした後、第2
導電膜(n+−a−Si膜)やドレイン膜(ドレインC
r膜)を成膜するという手段を採用し、チャンネル部の
形成にドライエッチング技術を用いないことを特徴と
し、これによって前記目的を達成したものである。
According to the present invention, after patterning a resist on a channel generating portion, a second step is performed.
Conductive film (n + -a-Si film) and drain film (drain C)
It is characterized in that the dry etching technique is not used for forming the channel portion by adopting a means of forming an r film).

【0010】即ち、本発明は、(1) 基板上にゲ−ト電極
をパタ−ニングし、続いて、絶縁膜及び第1導電膜を成
膜する工程、(2) ゲ−ト電極上のチャンネル生成部分に
ホトレジストをパタ−ニングした後、第2導電膜を成膜
する工程、(3) 導電膜生成部分にホトレジストをパタ−
ニングし、導電膜生成部分以外の第1導電膜、第2導電
膜の二層の膜を同時にエッチング除去する工程、(4) 上
記導電膜生成部分上のホトレジスト及びチャンネル生成
部分上のホトレジストを全て剥離する工程、(5) チャン
ネル部分に再びホトレジストをパタ−ニングし、ドレイ
ン膜を成膜する工程、(6) チャンネル部上のホトレジス
トを剥離する工程、を含むことを特徴とする薄膜トラン
ジスタ装置の製造方法を要旨とするものである。
That is, according to the present invention, (1) a step of patterning a gate electrode on a substrate, and subsequently forming an insulating film and a first conductive film, (2) a step of forming a gate electrode on the gate electrode. After the photoresist is patterned on the channel generation portion, the second conductive film is formed. (3) The photoresist is patterned on the conductive film generation portion.
And simultaneously etching and removing the two layers of the first conductive film and the second conductive film other than the conductive film generating portion, (4) All the photoresist on the conductive film generating portion and the photoresist on the channel generating portion are removed. Manufacture of a thin film transistor device characterized by including a step of peeling, (5) a step of patterning a photoresist again on the channel portion to form a drain film, and (6) a step of peeling the photoresist on the channel portion. The method is the gist.

【0011】以下、本発明を詳細に説明すると、本発明
によるチャンネル部分の形成手段としては、具体的に
は、ガラス基板上にCr膜から成るゲ−ト電極をパタ−
ニングし、続いて、絶縁膜としてSiN膜を、また、第
1導電膜としてa−Si膜を成膜する。その後、ゲ−ト
電極上のチャンネル生成部分にホトレジストをパタ−ニ
ングした後、リフトオフ法によりn+−a−Si膜(第
2導電膜)を成膜する。
The present invention will be described in detail below. Specifically, as a means for forming a channel portion according to the present invention, specifically, a gate electrode made of a Cr film is patterned on a glass substrate.
Then, a SiN film is formed as an insulating film and an a-Si film is formed as a first conductive film. After that, a photoresist is patterned on the channel generation portion on the gate electrode, and then an n + -a-Si film (second conductive film) is formed by a lift-off method.

【0012】次に、チャンネル生成部分も含めた導電膜
生成部分にホトレジストをパタ−ニングし、導電膜生成
部分以外のa−Si膜及びn+−a−Si膜を同時にエ
ッチング除去した後、該ホトレジストを剥離する。続い
て、チャンネル部分に再びホトレジストをパタ−ニング
した後、ドレインCr膜を成膜し、次に、このホトレジ
ストを剥離除去して薄膜トランジスタのチャンネル部を
形成する。
Next, a photoresist is patterned on the conductive film forming portion including the channel forming portion, and the a-Si film and the n + -a-Si film other than the conductive film forming portion are simultaneously removed by etching. Strip the photoresist. Then, after patterning a photoresist again on the channel portion, a drain Cr film is formed, and then the photoresist is peeled off to form a channel portion of the thin film transistor.

【0013】本発明は、以上のとおりチャンネル部の形
成にドライエッチングを行わないので、製造上安定した
プロセスでチャンネル部分が形成され、また、チャンネ
ル部のプラズマダメ−ジ等の心配がなく、製品信頼性の
向上に大きな効果が生ずるものである。
According to the present invention, since dry etching is not performed for forming the channel portion as described above, the channel portion is formed by a stable process in manufacturing, and there is no fear of plasma damage of the channel portion. This has a great effect on improving reliability.

【0014】[0014]

【実施例】次に、本発明の実施例を図1及び図2に基づ
いて説明する。図1及び図2は、本発明の一実施例を説
明するための図であり、このうち図1は、薄膜トランジ
スタ装置の製造法によるチャンネル部分の形成状況を工
程順(工程A〜工程C)に示した工程順断面図であり、
図2は、図1に続く工程D〜工程Fからなる工程順断面
図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to FIGS. 1 and 2 are views for explaining one embodiment of the present invention, in which FIG. 1 shows the formation state of a channel portion according to a method of manufacturing a thin film transistor device in a process order (process A to process C). It is a process order sectional view shown,
2A to 2C are cross-sectional views in order of the processes, which include processes D to F following FIG. 1.

【0015】まず、図1工程Aに示すように、ガラス基
板10上にCr膜から成るゲ−トCr電極12をパタ−ニン
グした後、プラズマCVDにより絶縁膜としてのSiN
膜11及び第1導電膜としてのa−Si膜13を順次堆積す
る。次に、第2導電膜としてn+−a−Si膜14をリフ
トオフ法を用いてパタ−ン形成を行う。即ち、図1工程
Bに示すように、ホトレジスト15のマスクをチャンネル
形成部分にパタ−ニングした後、第2導電膜としてn+
−a−Si膜14をプラズマCVDにて堆積させる。
First, as shown in FIG. 1A, a gate Cr electrode 12 made of a Cr film is patterned on a glass substrate 10 and then SiN as an insulating film is formed by plasma CVD.
The film 11 and the a-Si film 13 as the first conductive film are sequentially deposited. Next, the n + -a-Si film 14 is patterned as a second conductive film by using the lift-off method. That is, as shown in step B of FIG. 1, after patterning the mask of the photoresist 15 on the channel formation portion, n + is formed as the second conductive film.
The -a-Si film 14 is deposited by plasma CVD.

【0016】続いて、この状態で、図1工程Cに示すよ
うに、リフトオフ法で形成したホトレジスト15のマスク
及びn+−a−Si膜14を覆う形でホトレジスト17を塗
布し、導電膜生成部をホトリソグラフィにより形成した
後、フッ素系の反応性ガスを用いて導電膜生成部以外の
+−a−Si膜14及びa−Si膜13のドライエッチン
グを行う。以上の工程を経た後、ホトレジスト15及び17
を剥離除去する。
Subsequently, in this state, as shown in step C of FIG. 1, a photoresist 17 is applied so as to cover the mask of the photoresist 15 formed by the lift-off method and the n + -a-Si film 14 to form a conductive film. After the portions are formed by photolithography, dry etching is performed on the n + -a-Si film 14 and the a-Si film 13 other than the conductive film forming portion using a fluorine-based reactive gas. After the above steps, photoresists 15 and 17
Peel off.

【0017】ここで、前記したとおり、n+−a−Si
膜14をリフトオフにより形成しているため、ホトレジス
ト15上のn+−a−Si膜14aは、剥離液によってホト
レジスト15と共に除去される。そして、図2工程Dに示
すように、ホトレジスト15、17の剥離工程を通すことに
よりチャンネル部分16Bが精度良く形成される。
Here, as described above, n + -a-Si
Since the film 14 is formed by lift-off, the n + -a-Si film 14a on the photoresist 15 is removed together with the photoresist 15 by the stripping solution. Then, as shown in FIG. 2D, the channel portion 16B is formed with high precision by passing through the photoresist 15 and 17 peeling step.

【0018】次に、図2工程Eに示すように、再びリフ
トオフ法によりドレイン電極の形成を行う。即ち、図2
工程Dの状態でチャンネル部16B上にホトレジスト18を
ホトリソグラフィによりパタ−ニングした後、ドレイン
Cr膜16をプラズマCVDにより堆積する。そして、ホ
トレジスト18を剥離除去することにより、図2工程Fに
示す薄膜トランジスタを形成する。
Next, as shown in step E of FIG. 2, the drain electrode is formed again by the lift-off method. That is, FIG.
In the state of step D, a photoresist 18 is patterned on the channel portion 16B by photolithography, and then a drain Cr film 16 is deposited by plasma CVD. Then, the photoresist 18 is peeled and removed to form the thin film transistor shown in step F of FIG.

【0019】本発明の実施例においては、リフトオフ法
によるチャンネル部分16Bの形成を行っているため、従
来の技術のようにチャンネル形成部のa−Si膜13をド
ライエッチングにより所定膜厚分除去するという方法を
使わずに済み、該方法の採用を必要としないものであ
る。従って、製造上安定したプロセスでチャンネル部分
16Bを形成することができる。また、本発明の実施例に
おいては、チャンネル部分16Bの形成においてドライエ
ッチング工程を通していないので、チャンネル部のa−
Si膜13がプラズマダメ−ジを受けず、製品の信頼性が
向上する利点を有する。
In the embodiment of the present invention, since the channel portion 16B is formed by the lift-off method, the a-Si film 13 in the channel forming portion is removed by a predetermined thickness by dry etching as in the prior art. This method does not have to be used and does not require the adoption of this method. Therefore, the manufacturing process is stable and the channel part
16B can be formed. Further, in the embodiment of the present invention, since the dry etching process is not performed in the formation of the channel portion 16B, a-
The Si film 13 does not suffer plasma damage and has the advantage of improving the reliability of the product.

【0020】[0020]

【発明の効果】本発明は、以上詳記したとおり、チャン
ネル生成部分にレジストをパタ−ニングした後、第2導
電膜(n+−a−Si膜)やドレイン膜(ドレインCr
膜)を成膜する方法を用いているため、チャンネル部分
を比較的簡易に精度良く形成することができ、その結
果、薄膜トランジスタの製造プロセスが安定化するとい
う効果が生ずる。また、チャンネル部の形成にドライエ
ッチング技術を用いていないため、チャンネル部がプラ
ズマダメ−ジを受ける心配がなく、薄膜トランジスタ装
置の製品信頼性の向上に大きな効果が生ずる。
As described in detail above, according to the present invention, after the resist is patterned in the channel forming portion, the second conductive film (n + -a-Si film) and the drain film (drain Cr) are formed.
Since the method of forming the film is used, the channel portion can be formed relatively easily and accurately, and as a result, the manufacturing process of the thin film transistor is stabilized. Further, since the dry etching technique is not used for forming the channel portion, there is no fear that the channel portion will be damaged by plasma, and a great effect is brought about in improving the product reliability of the thin film transistor device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を説明するための図であっ
て、チャンネル部分の形成状況を工程順(工程A〜工程
C)に示した工程順断面図。
FIG. 1 is a diagram for explaining one embodiment of the present invention, which is a process order cross-sectional view showing a formation state of a channel portion in process order (process A to process C).

【図2】図1に続く工程D〜工程Fからなる工程順断面
図。
2A to 2C are cross-sectional views in order of the processes, including process D to process F following FIG.

【図3】従来法を説明するための図であって、チャンネ
ル部分の形成状況を工程順(工程A〜工程D)に示した
工程順断面図。
FIG. 3 is a diagram for explaining a conventional method, which is a process order cross-sectional view showing the formation state of a channel portion in process order (process A to process D).

【符号の説明】[Explanation of symbols]

10 ガラス基板 11 SiN膜 12 ゲ−トCr電極 13 a−Si膜 14 n+−a−Si膜 14a ホトレジスト上のn+−a−Si膜 15 ホトレジスト 16 ドレインCr膜 16B チャンネル部 17〜20 ホトレジスト10 glass substrate 11 SiN film 12 gate Cr electrode 13 a-Si film 14 n + -a-Si film 14a n + -a-Si film on photoresist 15 photoresist 16 drain Cr film 16B channel part 17-20 photoresist

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 (1) 基板上にゲ−ト電極をパタ−ニング
し、続いて、絶縁膜及び第1導電膜を成膜する工程、 (2) ゲ−ト電極上のチャンネル生成部分にホトレジスト
をパタ−ニングした後、第2導電膜を成膜する工程、 (3) 導電膜生成部分にホトレジストをパタ−ニングし、
導電膜生成部分以外の第1導電膜、第2導電膜の二層の
膜を同時にエッチング除去する工程、 (4) 上記導電膜生成部分上のホトレジスト及びチャンネ
ル生成部分上のホトレジストを全て剥離する工程、 (5) チャンネル部分に再びホトレジストをパタ−ニング
し、ドレイン膜を成膜する工程、 (6) チャンネル部上のホトレジストを剥離する工程、 を含むことを特徴とする薄膜トランジスタ装置の製造方
法。
1. A step of (1) patterning a gate electrode on a substrate, and subsequently forming an insulating film and a first conductive film, (2) a channel generation portion on the gate electrode. After patterning the photoresist, a step of forming a second conductive film, (3) patterning the photoresist on the conductive film generation portion,
A step of simultaneously etching and removing the two-layer film of the first conductive film and the second conductive film other than the conductive film generating portion, (4) a step of removing all the photoresist on the conductive film generating portion and the photoresist on the channel generating portion And (5) a step of patterning a photoresist again on the channel portion to form a drain film, and (6) a step of peeling off the photoresist on the channel portion.
【請求項2】 絶縁膜としてSiN膜を、第1導電膜及
び第2導電膜としてa−Si膜及びn+−a−Si膜を
用いることを特徴とする請求項1に記載の薄膜トランジ
スタ装置の製造方法。
2. The thin film transistor device according to claim 1, wherein a SiN film is used as the insulating film, and an a-Si film and an n + -a-Si film are used as the first conductive film and the second conductive film. Production method.
JP10355592A 1992-03-30 1992-03-30 Manufacture of thin film transistor device Pending JPH05283429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10355592A JPH05283429A (en) 1992-03-30 1992-03-30 Manufacture of thin film transistor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10355592A JPH05283429A (en) 1992-03-30 1992-03-30 Manufacture of thin film transistor device

Publications (1)

Publication Number Publication Date
JPH05283429A true JPH05283429A (en) 1993-10-29

Family

ID=14357072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10355592A Pending JPH05283429A (en) 1992-03-30 1992-03-30 Manufacture of thin film transistor device

Country Status (1)

Country Link
JP (1) JPH05283429A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100590925B1 (en) * 1999-07-30 2006-06-19 비오이 하이디스 테크놀로지 주식회사 method for manufacturing the TFT- LCD
US9196746B2 (en) 2011-12-05 2015-11-24 Samsung Display Co., Ltd. Thin film transistor comprising main active layer and sub active layer, and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100590925B1 (en) * 1999-07-30 2006-06-19 비오이 하이디스 테크놀로지 주식회사 method for manufacturing the TFT- LCD
US9196746B2 (en) 2011-12-05 2015-11-24 Samsung Display Co., Ltd. Thin film transistor comprising main active layer and sub active layer, and method of manufacturing the same

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