JPH038338A - Manufacture of multilayer wiring structure - Google Patents

Abstract

PURPOSE:To avoid the drop of throughput so as to elevate yield by exposing the whole face with such light quantity that only the section, where the thickness of a resist to become a mask is thin, dissolves, and developing it so as to expose the projection of an interlayer insulating film, and then executing selective etching, With the same resist as a mask, so that the interlayer insulating film may be flat. CONSTITUTION:An SiO2 film 2 is overlaid on the surface of a semiconductor substrate 1 where formation of a transistor, etc., has finished, and thereon the first wiring layer 3 in the specified shape is formed. Next, while burying this, APSG interlayer insulating film 4 is overlaid on the whole face, and a positive resist film 6 is provided including a projection 5 generated by the existence of the wiring layer 3. That is, the thickness of the film 6 is thinned at a region corresponding to the projection 5 and is thickened at the region not corresponding to the projection 5 so as to flatten the surface in advance, and the whole face is exposed with such exposure quantity that the thin region dissolves in developer. Next, the thin region is removed, and the resist film 6, which has become needless, is removed so as to flatten the insulating film 4, and here a second wiring layer is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a multilayer wiring structure that can be planarized using a simple method.

(B) Conventional Technology When electrodes or wirings in contact with a semiconductor substrate are covered with a passivation insulating film made of Si or 5i1Na, a step is created on the surface of the passivation film. When a second layer wiring is formed on this passivation film, the surface is required to be flattened to prevent disconnection, which is likely to occur at the stepped portion. One method for flattening is to flatten the surface by coating a resist as a dummy film on the passivation film, and then maintain flatness by selecting etching conditions such that the etching rates of the dummy film and the passivation film are approximately equal. An etch-back method for removing the dummy film is known (for example, disclosed in Japanese Patent Application Laid-Open No. 62-98646).
issue).

(c) Problems to be Solved by the Invention However, in the etch-back method, the etching speed of the dummy film is very slow, and it takes time.
This method requires expensive equipment such as reactive ion etching (reactive ion etching) equipment, and has the disadvantage that throughput is reduced and capital investment increases costs.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional problems.
) The entire surface is exposed to a light intensity that dissolves only the thin part of the film, and after development to expose the convex part (5) of the interlayer insulating film (4), the glabellar insulating film is removed using the resist (6) as a mask. (4
), the present invention provides a method for manufacturing a multilayer wiring structure that can be planarized by a simple method by performing selective etching to planarize the structure.

(E) Effect According to the present invention, there is no need for a special device such as RIE, and -
The photo-etching technology used for boat fishing can be used as is.
In addition to improving throughput, there is no need for new capital investment.

Example) An example of the method according to the present invention will be described in detail below with reference to FIG.

First, as shown in FIG. 1A, a silicon oxide film (Si
Al or A with a thickness of several micrometers is inserted through an insulating film (2) such as
The first layer is formed by depositing an ffi-barrier layer by vapor deposition or sputtering and patterning it using a photomask.
A wiring layer (3) is formed. The first wiring layer (3) can be brought into contact with the diffusion layer formed on the surface of the substrate (1) through a contact hole in the insulating film (2).

Thereafter, a glabellar insulating film (4) made of PSG (phosphorus silicate glass) or the like is formed on the entire surface using the CVD method so as to cover the first wiring layer (3). At this stage, the surface of the interlayer insulating film (4) inevitably has a step due to the thickness of the first wiring layer (3), and a convex portion (5) is formed.

Next, as shown in FIG. 1B, for example, AZ-1350 (S
A positive resist such as HIPLEY (trade name) is applied over the entire surface by spin-on coating and baked to form a resist film (6). By controlling the rotation speed and rotation time of the spin-on coating method, the resist film (6) is formed to be thin on the convex parts (5) of the interlayer insulating film (4) and thick on the low parts, so that its surface is flat. Form it so that

Next, as shown in FIG. 1C, the entire surface is irradiated with exposure light without using a photomask. Since the positive resist film (6) is sequentially exposed to light from the surface, only the thin resist film (6) on the convex portion (5) of the interlayer insulating film (4) is exposed at this time (X in the figure).
The amount of exposure is adjusted so that the film is exposed to light and dissolved in the developer.

Next, as shown in the first diagram, the resist film (6) is developed to remove only the exposed portion of the resist film (6) and expose the top of the convex portion (5) of the interlayer insulating film (4). Then, as shown in Figure 1E, the glabellar insulating film (4) is etched by using the resist film (6) that was not removed by development as a mask and using a dry method or a wet method to control factors such as etching time. The interlayer insulating film (4) is removed by etching so as to remove only the protrusions (5).

Then, as shown in FIG. 1F, the remaining resist film (6)
is removed to obtain a planarized interlayer insulating film (4). Thereafter, the process moves to the formation of a further upper wiring layer (second wiring layer).

(G) Effects of the Invention According to the method of the present application explained above, all conventional methods are used and no RIE equipment is required, so the glabellar insulating film (4) can be flattened by a simple method. This method has the advantage that there is no reduction in throughput, and therefore semiconductor devices can be manufactured with high yield.

[Brief explanation of the drawing]

FIGS. 1A to 1F are cross-sectional views for explaining the present invention.

Claims (2)

[Claims] (1) A step of forming a first wiring layer on the main surface of a semiconductor substrate and depositing an interlayer insulating film thereon, and depositing a resist on the interlayer insulating film so as to flatten the step of the interlayer insulating film. a step of applying exposure light to the entire surface of the resist with an energy that exposes the entire thickness of the thin portion of the resist corresponding to the unevenness of the interlayer insulating film; and developing the resist. a step of exposing a convex portion of the interlayer insulating film; a step of planarizing the surface of the interlayer insulating film by selectively etching the exposed interlayer insulating film to the middle of the film thickness; A method for manufacturing a multilayer wiring structure, comprising the step of forming a second wiring layer. (2) The method for manufacturing a multilayer wiring structure according to claim 1, wherein the resist is a positive resist.