JP2000012538A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable accurate formation of a connection hole and wiring groove in an interlayer insulating film in the case of forming buried wiring with use of a dual damascene process. SOLUTION: An interlayer insulating film 3 of plasma SiO2 or the like is formed as deposited to a thickness of 2.0 μm on a semiconductor substrate 1, on which a semiconductor element having a gate electrode 2 is formed as a lower layer. The film 3 is polished by a CMP(chemical-mechanical polishing) method until a thickness of the film from the gate electrode 2 becomes 0.8 μm to be thereby flatten. Next, a mask for processing of a connection hole and a wiring groove is formed by a silylation method. With use of the mask and an RIE(reactive ion etching) method, removal of resist using an oxygen gas, etching of the film 3 and removal of a silylation layer 8 formed on a resist are repeated. As a result, a connection hole 10 and a wiring groove 9 for the dual damascene are made in the insulating film 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a multilayer wiring by a dual damascene method.

[0002]

2. Description of the Related Art In recent years, when a multilayer wiring is formed on a semiconductor element, a dual-damascene method is used because the wiring is stacked, and the step becomes larger in the upper layer and the wiring becomes difficult to process. Things are getting more and more.
In order to form a metal wiring, first, a groove is dug in an insulating film, a metal is buried in the entire surface, and then a CMP method is performed.
Polishing the entire surface by a method. At this time, a method including forming a hole for making contact with the semiconductor region in addition to the metal in the lower layer below the metal wiring is called a dual damascene method.

In the dual damascene method, after forming a connection hole with a lower wiring and a wiring groove, a wiring material is deposited, and CMP is performed.
It is formed by a process such as removing a wiring material other than a wiring portion by a method.

For example, a method disclosed in Japanese Patent Application Laid-Open No. Hei 9-115866 is used.

That is, first, plasma CVD is performed on a lower wiring 22 such as a gate electrode formed on a semiconductor substrate 21.
An interlayer insulating film 23 of SiO ₂ or the like is deposited to a desired film thickness by a method or the like, and as shown in FIG. 4A, the interlayer insulating film 23 is planarized by a CMP method, and Is polished until a desired film thickness is obtained.

Next, as shown in FIG. 4B, a desired pattern is formed by a photolithography technique, and using the resist pattern 24a as a mask, a desired film of an upper wiring is formed by RIE using a fluorine-based gas. The interlayer insulating film 23 is etched to a depth corresponding to the thickness.

Next, after removing the resist 24a, a new resist 24b is applied, and as shown in FIG. 4 (c), a lower wiring 22 and a connection hole 26 for the upper wiring are formed by photolithography and RIE. The interlayer insulating film 23 is formed by etching until the lower wiring 22 is exposed. After that, the resist is stripped. As a result, FIG.
As shown in (d), the connection hole 26 and the wiring groove 25 necessary for the embedded wiring are formed.

Next, as shown in FIG. 4E, after depositing a barrier metal film 27 such as Ti or TiN by CVD or sputtering, a wiring material 28 such as Al or Cu is deposited by CVD or sputtering. It is laminated by a method.

Next, the wiring material film 28 and the barrier metal film 27 in portions other than the portions where the connection holes 26 and the wiring grooves 27 are formed are removed by CMP until the interlayer insulating film 23 is exposed, and
Wiring material 2 embedded in interlayer insulating film 23 and wiring groove 25
Polish so that there is no step with 8. As a result, FIG.
As shown in (f), the upper wiring 28 connected to the lower wiring 22 is formed in the connection hole 26 and the wiring groove 25.

In the above-described step of FIG. 4, two photolithography steps and an etching step are performed.

[0011]

As described above, in order to form a buried wiring using the dual dansin method, it is necessary to form connection holes and wiring grooves in an interlayer insulating film with high precision.

In order to form such connection holes and wiring grooves, (1) forming the connection holes after forming the wiring grooves;
(2) After forming the connection hole, a wiring groove is formed. (3)
After depositing the interlayer insulating film in an amount obtained by subtracting the depth of the wiring groove, for example, in processing an interlayer insulating film such as a SiN film,
After laminating a film having selectivity, and further processing the film having selectivity into a pattern of a connection hole, an interlayer insulating film equivalent to a wiring groove depth is deposited, and a wiring groove and a wiring groove are formed using a wiring groove pattern mask. There is a method of simultaneously processing the connection holes.

However, in the method (1), although the formation of the wiring groove seems to be good, when a resist pattern for the next connection hole is formed at the bottom of the wiring groove, a resist pattern having a large aspect ratio is required. Advanced lithography technology is required. Specifically, when there is no step, the diameter is 0.4
A 1.0 μm focus margin can be obtained in forming a μm resist pattern, but in this case, the focus margin is significantly reduced to 0.2 μm.

In the method (2), although the formation of the resist pattern is easy, the lower connection wiring groove is already exposed at the bottom of the connection hole when the wiring groove is formed after the connection hole processing. When the erosion amount of the wiring is limited to a certain level or less, a processing technique with high selectivity to this film is required. Specifically, when TiSix is used for the base electrode, for example, the selectivity of the etching between the insulating film such as a SiO ₂ film and TiSix may be about 20 when only one etching is performed. In the case of repeated exposure, a selection ratio about twice this is required.

Further, the method (3) has problems that the steps are complicated and the number of steps is large, so that the cost is high.

[0016]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein at least two wirings are formed via a contact hole formed in an interlayer insulating film and formed above. In the method of manufacturing a semiconductor device in which the formed wiring is embedded in the interlayer insulating film, after forming the first wiring, an interlayer insulating film is formed, and a photosensitive silicon-containing resist is applied on the interlayer insulating film. And exposing the contact hole forming region to light, exposing the first exposure region other than the contact hole forming region and the second exposure region other than the second wiring forming region in the second wiring forming region. A step of exposing the first exposure region so that the exposure amount becomes larger, a step of silylating the exposed resist, and removing a non-silylated resist in the contact hole formation region; And using the silylated resist as a mask, forming the interlayer insulating film deeper than the difference between the thickness of the interlayer insulating film and the thickness of the second wiring and on the second wiring forming region. Etching until all of the silylated resist is removed; and removing the resist in the non-silylated second wiring formation region.
By etching the interlayer insulating film by the thickness of the second wiring using the silylated resist as a mask,
Forming the contact hole and the second wiring groove, and depositing a wiring material on the entire surface and removing the wiring material by polishing until an interlayer insulating film is exposed, whereby the contact hole and the second wiring groove are removed. A step of embedding the wiring material in the wiring groove.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the present invention, the first contact hole forming region is not exposed and the first contact hole forming region is formed in the second wiring forming region and other than the first contact hole forming region. The step of exposing the second exposure region other than the exposure region and the second wiring formation region so that the first exposure region has a larger exposure amount uses a mask that covers only the contact hole formation region. 2. The semiconductor device according to claim 1, further comprising: performing a first exposure; and performing a second exposure using a mask that covers only the second wiring formation region. It is a manufacturing method of.

Further, in the method of manufacturing a semiconductor device according to the present invention, the contact hole forming region is not exposed, and the first contact hole forming region is formed in the second wiring forming region and other than the contact hole forming region. The step of exposing the second exposure region other than the exposure region and the second wiring formation region so that the first exposure region has a larger exposure amount includes the step of exposing the transmittance of the first exposure region to the second exposure region. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of exposing using a single mask, the transmittance being higher than the transmittance of the second exposure region and the contact hole formation region being shielded from light. is there.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, based on one embodiment,
The present invention will be described in detail.

FIG. 1 is a view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a view for explaining the first half of FIG. 1, and FIG. 3 is a view for explaining the latter half of FIG. FIG.

First, an interlayer insulating film 3 made of a plasma SiO ₂ film or the like is formed on a semiconductor substrate 1 on which a semiconductor element made up of a gate electrode 2 serving as a lower electrode and the like is formed.
m. Further, as shown in FIG. 1A, the thickness of the interlayer insulating film 3 from the gate electrode 2 is 0.8
Polishing is performed to a thickness of μm, and the interlayer insulating film 3 is flattened.

Next, a mask for processing the connection holes and the wiring grooves is formed by a silylation method. In the present embodiment, a silylation method using a negative resist will be described. First, a negative resist 4 composed of nephtoquinonediazide and a novolak resin is applied on the insulating film to a thickness of 1.0 μm.
Subsequently, the resist 4 is exposed to light having different intensities in a region other than the connection hole forming region and a region other than the wiring groove forming region.

As a result, as shown in FIG. 1B, on the resist 4, a connection hole forming region 5 which is not exposed and a wiring groove forming region 6 other than the connection hole having a relatively low exposure intensity are formed. Three regions other than the connection hole forming region 5 and the wiring groove forming region 6 having a high exposure intensity are formed. In addition,
A method for changing the exposure intensity will be described later.

Next, at 180 ° C., H
MDS (hexamethyldisilazane) is supplied. Thereby, the silyl group is substituted for the phenolic hydroxyl group of the novolak resin, that is, the silyl group is silylated. On the other hand, since the silylation does not proceed in the unexposed area, the resist is shown in FIG.
As shown in (c), a silylated layer 8 is formed according to the exposure intensity.

Next, the removal of the resist using oxygen gas by RIE, the etching of the interlayer insulating film 3 and the removal of the silylated layer 8 on the resist surface are repeated by a mixed gas of CHF ₃ , CF ₄ and Ar. Thereby, as shown in FIG. 1D, the connection hole 10 and the wiring groove 9 for dual damascene are used.
Is formed on the interlayer insulating film 3. A method of repeating this etching will be described later.

Next, after performing a natural oxide film removing step on the surface of the layer insulating film 3 including the connection holes 10 and the wiring grooves 9, a barrier metal 11 made of TiN or Ti is formed by a CVD method. As shown in FIG. 1E, for example, a wiring material 12 such as Cu is continuously deposited. Thereafter, at 200 to 400 ° C. and 30 to
In some cases, heat treatment for about 60 minutes is added.

Next, the connection hole 10 and the wiring groove 9 are formed by CMP.
The barrier metal 11 and the wiring material 12 on the interlayer insulating film 3 are removed, leaving only the barrier metal 11 and the wiring material 12. As a result, the embedded wiring 12a is formed by the dual damascene method as shown in FIG. Even in the description of multi-layer wiring of two or more layers, the above-described steps can be repeated to form the wiring with high accuracy.

Next, with reference to FIG. 2, a description will be given of a double exposure method as an embodiment of the present invention as an exposure method for changing the intensity on the resist surface. Here, the light source of the resist material, the exposure device, and the like are all described as i-rays, but the present invention is not limited to the light source.

First, as shown in FIG. 2A, a 1.0 μm thick negative resist 4 applied on the interlayer insulating film 3 is used.
Next, exposure is performed using a mask 13 that shields the connection hole formation region from light. This exposure amount is 1/4 to 1/2 of the initial condition.
Set relatively low. Specifically, for example, the exposure time may be set to 8 msec so that the photosensitive area on the resist surface has a thickness of about 0.15 μm when the subsequent silylation step is completed.

Subsequently, as shown in FIG. 2B, exposure is performed by using a mask 14 that passes through portions other than the wiring grooves. This exposure amount is higher than that of the exposure other than the connection holes, and is set so that the silylated layer does not disappear when the connection holes 10 are processed by RIE in the insulating film described later. Specifically, when the silylation step is completed, the silylated layer 8 has a thickness of 0.
For example, the exposure time is set to 420 m so as to be about 6 μm.
Seconds may be set. At this time, the connection hole forming region is not exposed because it is in the wiring groove forming region.

As a result, the connection hole forming region 5 which has not been exposed, the wiring groove forming region 6 other than the connection hole having a relatively low exposure intensity, and the connection hole forming region 5 having a relatively high exposure intensity.
In addition, a region 7 other than the wiring groove forming region 6 is formed. Note that this method is one of the embodiments of the present invention. In addition, by using a halftone mask technology capable of adjusting the amount of transmitted light in an exposure mask, a desired exposure can be performed on the resist surface in one exposure. A method of forming an intensity distribution of the above is also effective.

Next, a method of processing the connection holes 10 and the wiring grooves 9 in the interlayer insulating film 3 by RIE will be described with reference to FIG. Although an embodiment using a magnetron type RIE as the RIE apparatus will be described, the present invention is not limited to this.

Firstly, shown in FIG. 3 (a), the resist 4 of the connection hole forming region that is not silylated silylated resist pattern as a mask, the O ₂ 10 sccm, CO ₂ and 10
sccm, pressure 20 mTorr, magnetic field strength 40 Gau
ss, RF power is set to 300 W, and removed.

Next, as shown in FIG. 3 (c), the interlayer insulating film 3 in the connection hole forming region is made of 50 sccm CHF ₃ and CF ₄
20 sccm, Ar 100 sccm, pressure 200
At mTorr, a magnetic field strength of 80 Gauss, and an RF power of 700 W, the interlayer insulating film 3 is etched by an amount equal to or more than a value obtained by subtracting a predetermined wiring groove depth (0.4 μm) from a film thickness of 0.8 μm.

At this time, the upper limit of the etching amount is determined until the silylated layer 9 in a portion other than the wiring groove forming region disappears.
When the selectivity between the silylated layer 8 and the interlayer insulating film 3 in the etching is 1, the etching depth is 0.6 μm. At this time, 0.15% of the resist surface of the wiring groove portion other than the connection hole was formed.
The μm-thick silylated layer 8 is removed, exposing the surface of the underlying resist 4.

Next, as shown in FIG. 3D, the resist 4 whose surface has been exposed is removed under the above-described resist removal conditions, and further, as shown in FIG.
Under the above etching conditions, the wiring groove 9 is etched to a depth of 0.4 μm. At this time, etching for forming the connection hole 10 proceeds at the same time, and excessive etching is not performed.
The connection hole 10 and the wiring groove 9 can be processed at the same time. afterwards,
As shown in FIG. 1, formation of a barrier metal, embedding of a wiring material, and the like are performed to form an embedded wiring 12a.

[0037]

As described above in detail, according to the present invention, the formation of contact holes and wiring trenches for forming wirings of Al, Cu and the like by the dual damascene method can be performed by the conventional lithography technology or RIE technology. Accordingly, it can be formed more easily and accurately, and the number of steps, that is, the production cost can be reduced.

Further, by changing the transmittance by the mask pattern, the number of exposures can be reduced to one, and the accuracy can be further improved and the number of steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram provided for explanation of a first half step of FIG. 1;

FIG. 3 is a diagram provided for explanation of a latter half process of FIG. 1;

FIG. 4 is a diagram provided for explanation of a conventional dual damascene process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate electrode 3 Insulating film 4 Resist 5 Connection hole formation area which is not exposed 6 Wiring groove formation area other than connection hole with relatively low exposure intensity 7 Connection hole formation area and wiring with relatively high exposure intensity Region other than groove forming region 8 Silylation layer 9 Wiring groove 10 Connection hole 11 Barrier metal 12 Wiring material 12 Embedded wiring 12a

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device, wherein at least two wirings are formed via contact holes formed in an interlayer insulating film, and wirings formed above are embedded in the interlayer insulating film. Forming an interlayer insulating film after forming the first wiring, applying a photosensitive silicon-containing resist on the interlayer insulating film, exposing the contact hole forming region to light, And exposing a first exposure region other than the contact hole formation region and a second exposure region other than the second wiring formation region such that the first exposure region has a larger exposure amount. A step of silylating the exposed resist and removing the resist in the non-silylated contact hole formation region, and using the silylated resist as a mask to form the interlayer insulating film, Etching deeper than the difference between the thickness of the interlayer insulating film and the thickness of the second wiring, and removing all silylated resist on the second wiring formation region; Removing the resist in the second wiring formation region that has not been silylated; and etching the interlayer insulating film by the thickness of the second wiring using the silylated resist as a mask.
Forming the contact hole and the second wiring groove; and depositing a wiring material on the entire surface and removing the wiring material by polishing until an interlayer insulating film is exposed, thereby forming the contact hole and the second wiring groove. A method for manufacturing a semiconductor device, comprising a step of embedding the wiring material in a wiring groove. 2. A first exposure region other than the contact hole formation region and a second exposure region other than the contact hole formation region in the second wiring formation region without exposing the contact hole formation region. Exposing the first exposure region so that the exposure amount is larger in the first exposure region, using a mask that covers only the contact hole formation region; 2. The method of manufacturing a semiconductor device according to claim 1, comprising: performing a second exposure using a mask that covers only the second exposure. 3. 3. A first exposure region other than the contact hole formation region and a second exposure region other than the contact hole formation region in the second wiring formation region without exposing the contact hole formation region. Exposing the first exposure region to have a larger exposure amount, the transmittance of the first exposure region is higher than the transmittance of the second exposure region, and the contact hole formation region is 2. The method for manufacturing a semiconductor device according to claim 1, comprising a step of exposing using a single mask that is shielded from light.