JP2550601B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A method of filling a trench formed in a silicon substrate with an insulator to planarize the trench and forming a semiconductor device on the trench. The process of flattening the substrate surface by filling a plurality of trenches of different sizes formed on the silicon substrate with an insulator that has been chemically vapor-deposited for the purpose of flattening forms a groove on the semiconductor substrate. And a step of coating an insulating material on the substrate by a chemical vapor deposition method to a film thickness equal to or more than the depth of the groove, and the concave part formed on the concave part in the insulating layer on the groove position is flat. Forming a low-contrast pattern having a film thickness substantially equal to the groove depth and having a cross-sectional area substantially equal to the cross-sectional area of the recess regardless of the width of the groove in a portion having a wider bottom. ,
A step of forming the low-contrast pattern to cover the entire surface of the body substrate with a flat material layer and flattening;
A semiconductor device is formed by using the substrate formed by the low contrast pattern and the step of completely etching the insulator at substantially the same etching rate and leaving the insulator only in the groove.

[Industrial applications]

The present invention relates to a manufacturing method for filling a trench formed on a substrate with an insulating material to obtain a flat substrate.

For semiconductor devices such as IC and LSI, thin film formation technology, photolithography technology (photolithography or electron beam lithography),
Although miniaturization is progressing due to advances in diffusion layer formation technology, etc., VLSI has been put to practical use, but as a technology for separating such semiconductor elements, conventional field oxide films have been formed by selective oxidation of silicon (abbreviated as Si). Instead, trenches (deep trenches) are formed in the Si substrate, and the trenches are filled with an insulator for element isolation, or trenches with a large aspect ratio are provided for area isolation.

The reason for this is that as the device becomes smaller, the dimensional accuracy of the insulating layer is required to be higher and higher.

[Conventional technology]

4 (A) to 4 (E) are cross-sectional views for explaining a conventional element isolation technique. The element isolation layer forming position and the region isolation position formed on the Si substrate 1 by the conventional selective oxidation method are shown in FIG. A wide recess 2 and a narrow recess 3 are created by a trench process using reactive ion etching (abbreviated as RIE). Next, an insulating layer such as a silicon dioxide (SiO ₂ ) layer 4 is formed on the Si substrate 1 by chemical vapor deposition (substantially CVD) to a thickness not less than the depth of the trench.

In this case, in the narrow recess 3, the SiO ₂ layers 4 are in contact with each other to form a recess 9 as shown in the figure, whereas in the wide recess 2, a flat recess 5 having a similar shape remains. (As shown in FIG. 9B) A resist pattern 6 is formed in the flat recess 5 by using a photolithography technique (photolithography) to fill the flat recess 5.

However, in this case, a recess 7 is left at the boundary between the resist pattern 6 and the SiO ₂ layer 4 as shown in the figure, but this is to allow a positioning margin when the mask pattern is displaced. (The above C in the same figure) Next, after an insulating layer such as a resist layer 8 is formed thereon by a spin coating method or the like to flatten the surface, (D in the same figure above), a resist layer 8 and a SiO ₂ layer 4 are formed. By etching back to the position of the Si substrate 1 using an etchant that etches at a similar rate, the wide recess 2 and the narrow recess 3 are each flatly filled with SiO ₂ . (E in the same figure) Here, as an etchant capable of dry etching the resist and SiO ₂ at a substantially constant rate, for example, a mixed gas of methane trifluoride (CHF ₃ ) and O ₂ can be cited.

 However, this is not ideally the case in general.

FIG. 3 shows such an example, and shows a case where narrow recesses 3 are gathered on a flat Si substrate 1, and SiO is formed by the CVD method.
_{When the} resist layer 8 is formed by a spin coating method or the like after forming the film of the _second layer 4 to a thickness not less than the depth of the trench
Macroscopically, the resist layer 8 is flat, but microscopically, due to the presence of the recess of the narrow recessed portion 3, the resist layer 8 is
As shown in the figure, the thickness of the resist layer is different between the gathering region of the narrow recesses 3 and the region of the smooth substrate. Therefore, if the etching back is performed up to the smooth substrate surface where the narrow recess 3 is not formed, overetching occurs in the region of the narrow recess 3 and the flatness is impaired. (B in the same figure) On the contrary, Si in which the recess 3 with a narrow etch back is formed
When it is aligned with the substrate surface, the SiO ₂ layer remains on the smooth substrate surface.

As described above, according to the conventional method, it is difficult to completely fill the hole with SiO ₂ when there are large and small recesses on the Si substrate.

[Problems to be solved by the invention]

As described above, according to the conventional element isolation technique, it is difficult to completely fill the recesses having different areas such as the element isolation region and the region isolation region with the insulator to completely flatten the surface.

[Means for solving problems]

The above-mentioned problem is that the step of filling the plurality of trenches of different sizes formed on the Si substrate to be treated with the chemical vapor grown insulator to flatten the substrate surface is performed by the chemical vapor deposition method. A step of forming a flat recess having a cross-sectional shape similar to that of the trench by coating an insulator with a film thickness equal to or more than the above, and the recess and the flat recess formed in the insulating layer on the trench position. A step of coating a low-contrast pattern that substantially coincides with the depression and the depression on the depression between the formed resist pattern and the insulating layer, and coating a resist layer on the Si substrate to be processed coated with the low-contrast pattern. This can be solved by carrying out a step of flattening the surface of the Si substrate and a step of etching the Si substrate to be processed up to the surface of the Si substrate to leave the insulating film only in the trench.

[Action]

The reason why the conventional method of flattening trenches such as wide recesses and narrow recesses formed by the trench process on the Si substrate by filling them with SiO ₂ is not ideal is as shown in FIG. The recess 9 formed on the narrow recess 3 when the SiO ₂ layer was formed on the substrate and the recess 7 formed on forming the resist pattern 6 on the flat recess 5 were left as they are. It depends.

However, when the recesses 9 and the recesses 7 are filled with a resist by photolithography using a resist, the volume of these is very small, and the projections are always formed in order to achieve dimensional accuracy, so that the resist layer 8 is formed. Does not flatten, and therefore, ideal backfilling is not performed even if it is etched back.

Therefore, the present invention solves the problem by forming a low-contrast resist pattern in the recesses 9 and the recesses 5 and filling the resist pattern.

FIG. 2 is a sectional view showing the principle of the present invention. FIG. 2 (A) shows a state where a resist low contrast pattern 10 is formed on a Si substrate 1, and FIG. 2 (B) shows Si. It shows a state in which it is applied to a flat concave portion 5 and a concave portion 9 formed when the SiO ₂ layer 4 is formed on the wide concave portion 2 and the narrow concave portion 3 of the substrate 1.

In this way, the low-contrast pattern 10 made of resist has a low height and has a wide hem, which is almost the same as the surface of the SiO ₂ layer 4, and the misalignment of the mask pattern due to the wide hem. Also, the margin increases.

Next, as a method of forming such a low-contrast pattern, after applying a positive resist, a material (for example, a blackening material) which becomes harder to pass through when light is applied is applied thereon.

 Exposure is performed by shifting the focus with weak light.

After overexposed development, the temperature is raised to cause reflow.

 It uses a low-resolution exposure optical system.

The pattern edge of the reticle or mask is finely uneven and blurred.

 A combination of the above methods.

It can be done by taking such a method.

〔Example〕

1 (A) to 1 (E) are cross-sectional views for explaining a method for carrying out the present invention, in which a wide concave portion 2 and a narrow concave portion 3 for performing element isolation by a trench process similar to the conventional one are formed on a Si substrate. Was formed (the above-mentioned FIG. A), and then a SiO ₂ layer 4 similar to the conventional one was formed by CVD using SiH ₄ and O ₂ as reaction gases.

Here, there is a recess 9 above the narrow recess 3 and a flat recess 5 above the wide recess 2. Next, the recess 9 and the flat recess 5 are filled with resist on the SiO layer 4 by using a photo-etching technique. At this time, the focus is defocused by weak light and the exposure is performed. A low contrast pattern 10 was formed.

By this process, the recess 9 and the flat recess 5 are almost flatly filled with the resist. (Above same figure C) Next, after the resist layer 8 is coated and flattened by spin coating in the same manner as in the conventional case (above same figure D),
Set it in the plasma etching equipment, perform plasma etching using a mixed gas of CHF ₃ and O ₂ as an etchant,
By etching up to the surface of the Si substrate, it was possible to obtain the Si substrate 1 in which the wide recesses 2 and the narrow recesses 3 were flatly filled with the SiO ₂ layer 4. (Effect of the same figure) [Effect of the invention] As described above, according to the present invention, the Si substrate, which requires the dense formation of the interlayer insulating layer and the isolation region, is flatly filled with an insulator such as SiO _2. It is possible to
It is possible to form a high-density semiconductor device such as VLSI with high accuracy.

[Brief description of drawings]

1 (A) to 1 (E) are sectional views for explaining the element isolation method according to the present invention, FIGS. 2 (A) and 2 (B) are sectional views showing the principle of the present invention, and FIG. 3 (A). , (B) are sectional views for explaining the conventional element isolation method, and FIGS. 4 (A) to (E) are sectional views for explaining the conventional element isolation technique. In the figure, 1 is a Si substrate, 2 is a wide recess, 3 is a narrow recess, 4 is a SiO ₂ layer, 5 is a flat recess, 6 is a resist pattern, 7 is a recess, 8 is a resist layer, 9 is a recess, and 10 is a recess. Low contrast pattern.

Claims (1)

(57) [Claims] 1. A step of flattening a substrate surface by filling a plurality of trenches formed on a semiconductor substrate with different sizes with an insulating material obtained by chemical vapor deposition, and a step of forming a groove on the semiconductor substrate. A step of coating an insulating material on the substrate by a chemical vapor deposition method so as to have a film thickness equal to or larger than a depth of the groove, and a recess having a flat bottom on the recess formed in the insulating layer on the groove position. Forming a low-contrast pattern in which the film pressure is approximately equal to the groove depth and has a cross-sectional area substantially equal to the cross-sectional area of the recess regardless of the width of the groove in the wide portion. A step of covering the entire surface of the substrate on which the contrast pattern is formed with a planarizing material layer to planarize, and the planarizing material layer, the low contrast pattern, and the insulator are entirely etched at substantially the same etching rate to form only a groove Leave the insulator on The method of manufacturing a semiconductor device that that the process, characterized in that it comprises a.