JPS6466939A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6466939A JPS6466939A JP22360987A JP22360987A JPS6466939A JP S6466939 A JPS6466939 A JP S6466939A JP 22360987 A JP22360987 A JP 22360987A JP 22360987 A JP22360987 A JP 22360987A JP S6466939 A JPS6466939 A JP S6466939A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- trenches
- layer
- sio2 layer
- flatly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
Abstract
PURPOSE:To bury trenches flatly with an insulator, and to form an Si substrate with high accuracy by forming a plurality of the trenches being shaped onto the Si substrate to be treated and having a different size, coating the Si substrate coated with a low contrast pattern with a resist layer and flattening the Si substrate. CONSTITUTION:A wide recessed section 2 and narrow recessed sections 3 isolating elements by a trench process are shaped onto an Si substrate 1, and an SiO2 layer 4 is formed through CVD using SiH4 and O2 as a reaction gas. The recesses 9 and the flat recessed section 5 are buried with a resist by employing a photoetching technique on the SiO2 layer 4, but low contrast patterns 10 are shaped by displacing a focus and exposing the layer 4 by weak light at that time. The substrate is set to a plasma etching device, and plasma etching is performed, using the mixed gas of CHF3 and O2 as an etchant. The Si substrate 1, the trenches of which are buried flatly with the SiO2 layer 4, is acquired.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62223609A JP2550601B2 (en) | 1987-09-07 | 1987-09-07 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62223609A JP2550601B2 (en) | 1987-09-07 | 1987-09-07 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6466939A true JPS6466939A (en) | 1989-03-13 |
JP2550601B2 JP2550601B2 (en) | 1996-11-06 |
Family
ID=16800876
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62223609A Expired - Lifetime JP2550601B2 (en) | 1987-09-07 | 1987-09-07 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2550601B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5212114A (en) * | 1989-09-08 | 1993-05-18 | Siemens Aktiengesellschaft | Process for global planarizing of surfaces for integrated semiconductor circuits |
KR100242387B1 (en) * | 1997-07-28 | 2000-03-02 | 김영환 | Method of forming an element isolation film in a semiconductor device |
KR100476372B1 (en) * | 1997-12-30 | 2005-07-07 | 주식회사 하이닉스반도체 | Trench type isolation layer formation method for semiconductor devices with different trench widths |
-
1987
- 1987-09-07 JP JP62223609A patent/JP2550601B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5212114A (en) * | 1989-09-08 | 1993-05-18 | Siemens Aktiengesellschaft | Process for global planarizing of surfaces for integrated semiconductor circuits |
KR100242387B1 (en) * | 1997-07-28 | 2000-03-02 | 김영환 | Method of forming an element isolation film in a semiconductor device |
KR100476372B1 (en) * | 1997-12-30 | 2005-07-07 | 주식회사 하이닉스반도체 | Trench type isolation layer formation method for semiconductor devices with different trench widths |
Also Published As
Publication number | Publication date |
---|---|
JP2550601B2 (en) | 1996-11-06 |
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