JPS57124443A - Forming method for electrode layer - Google Patents

Forming method for electrode layer

Info

Publication number
JPS57124443A
JPS57124443A JP1039881A JP1039881A JPS57124443A JP S57124443 A JPS57124443 A JP S57124443A JP 1039881 A JP1039881 A JP 1039881A JP 1039881 A JP1039881 A JP 1039881A JP S57124443 A JPS57124443 A JP S57124443A
Authority
JP
Japan
Prior art keywords
film
wafer surface
electrode layer
etching
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1039881A
Other languages
Japanese (ja)
Inventor
Tsutomu Tsuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1039881A priority Critical patent/JPS57124443A/en
Publication of JPS57124443A publication Critical patent/JPS57124443A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To realize an opening cross section with the size larger toward the wafer surface by a method wherein an insulating film the Si concentration therein is larger away from the wafer surface and then the insulating film is partially etched away for the formation of an electrode. CONSTITUTION:Piled upon a high resistance buffer laye 32 and a dynamic layer 33 provided on a semi-insulating GaAs substrate 31 is an SiNX film 34, formed by the plasma CVD technique, wherein a point further from the wafer surface contains more Si. Formed on the SiNX film 34 is a photoresist film 35 with an opening for a gate electrode. The film 35 serves as a mask for etching the film 34. A Pd 36 is formed following a complete removal of the film 35. Then, the film 34 is removed by etching. This procedure results in an opening cross section with the size larger toward the wafer surface, simplifying the electrode layer forming process.
JP1039881A 1981-01-27 1981-01-27 Forming method for electrode layer Pending JPS57124443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1039881A JPS57124443A (en) 1981-01-27 1981-01-27 Forming method for electrode layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1039881A JPS57124443A (en) 1981-01-27 1981-01-27 Forming method for electrode layer

Publications (1)

Publication Number Publication Date
JPS57124443A true JPS57124443A (en) 1982-08-03

Family

ID=11749021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1039881A Pending JPS57124443A (en) 1981-01-27 1981-01-27 Forming method for electrode layer

Country Status (1)

Country Link
JP (1) JPS57124443A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63193577A (en) * 1987-02-05 1988-08-10 Mitsubishi Electric Corp Manufacture of semiconductor light detecting device
JP2014229665A (en) * 2013-05-20 2014-12-08 富士通セミコンダクター株式会社 Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63193577A (en) * 1987-02-05 1988-08-10 Mitsubishi Electric Corp Manufacture of semiconductor light detecting device
JP2014229665A (en) * 2013-05-20 2014-12-08 富士通セミコンダクター株式会社 Method for manufacturing semiconductor device

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