JPS56100420A - Plasma etching method for oxidized silicon film - Google Patents

Plasma etching method for oxidized silicon film

Info

Publication number
JPS56100420A
JPS56100420A JP304680A JP304680A JPS56100420A JP S56100420 A JPS56100420 A JP S56100420A JP 304680 A JP304680 A JP 304680A JP 304680 A JP304680 A JP 304680A JP S56100420 A JPS56100420 A JP S56100420A
Authority
JP
Japan
Prior art keywords
etching
plasma etching
film
silicon film
etching method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP304680A
Other languages
Japanese (ja)
Inventor
Takuji Sugawara
Haruo Okano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP304680A priority Critical patent/JPS56100420A/en
Publication of JPS56100420A publication Critical patent/JPS56100420A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent the production of an ion shock layer on the occasion of plasma etching and thereby make a semiconductor device operate normally by etching an SiO2 film in a part of the course of process by gas plasma containing F and C and then etching the same by a solution containing F. CONSTITUTION:A resist mask 3 is goven to the SiO2 film 2 on an Si substrate 1. The film 2 is subjected to plasma etching in a part of the course of process thereof by adding CF4 of 12cc/min and H2 of 8cc/min and by applying high-frequency electric power of 21W/cm<2> at the stage when the substances are in 0.04 Torr. Next, the remaining film of SiO2 including the ion shock layer is removed through etching with NH4F, whereby a pattern or SiO22 with little etching on the lateral surface thereof can be formed.
JP304680A 1980-01-17 1980-01-17 Plasma etching method for oxidized silicon film Pending JPS56100420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP304680A JPS56100420A (en) 1980-01-17 1980-01-17 Plasma etching method for oxidized silicon film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP304680A JPS56100420A (en) 1980-01-17 1980-01-17 Plasma etching method for oxidized silicon film

Publications (1)

Publication Number Publication Date
JPS56100420A true JPS56100420A (en) 1981-08-12

Family

ID=11546363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP304680A Pending JPS56100420A (en) 1980-01-17 1980-01-17 Plasma etching method for oxidized silicon film

Country Status (1)

Country Link
JP (1) JPS56100420A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0259098A2 (en) * 1986-09-04 1988-03-09 AT&T Corp. Integrated circuits having stepped dielectric regions
JPH01154565A (en) * 1987-12-10 1989-06-16 Fujitsu Ltd Manufacture of junction fet
JPH01173932U (en) * 1988-05-25 1989-12-11
JP2004356575A (en) * 2003-05-30 2004-12-16 Semiconductor Leading Edge Technologies Inc Manufacturing method of semiconductor device
JP2005236062A (en) * 2004-02-20 2005-09-02 Nec Electronics Corp Manufacturing method for nonvolatile semiconductor memory apparatus
US7655506B2 (en) 2003-09-01 2010-02-02 Nec Electronics Corporation Leadless type semiconductor package, and production process for manufacturing such leadless type semiconductor package

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0259098A2 (en) * 1986-09-04 1988-03-09 AT&T Corp. Integrated circuits having stepped dielectric regions
JPH01154565A (en) * 1987-12-10 1989-06-16 Fujitsu Ltd Manufacture of junction fet
JPH01173932U (en) * 1988-05-25 1989-12-11
JP2004356575A (en) * 2003-05-30 2004-12-16 Semiconductor Leading Edge Technologies Inc Manufacturing method of semiconductor device
US7655506B2 (en) 2003-09-01 2010-02-02 Nec Electronics Corporation Leadless type semiconductor package, and production process for manufacturing such leadless type semiconductor package
JP2005236062A (en) * 2004-02-20 2005-09-02 Nec Electronics Corp Manufacturing method for nonvolatile semiconductor memory apparatus

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