JPS57148371A - Manufacture of mesa type semiconductor device - Google Patents

Manufacture of mesa type semiconductor device

Info

Publication number
JPS57148371A
JPS57148371A JP56034445A JP3444581A JPS57148371A JP S57148371 A JPS57148371 A JP S57148371A JP 56034445 A JP56034445 A JP 56034445A JP 3444581 A JP3444581 A JP 3444581A JP S57148371 A JPS57148371 A JP S57148371A
Authority
JP
Japan
Prior art keywords
substrate
ground
mesa groove
type
windows
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56034445A
Other languages
Japanese (ja)
Inventor
Masatake Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56034445A priority Critical patent/JPS57148371A/en
Publication of JPS57148371A publication Critical patent/JPS57148371A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To enable to easily form the mesa groove of double-negative bevel type for the subject semiconductor device by a method wherein, after a semiconductor substrate has been selectively ground using sand blasting method, a chemical etching is performed on a semiconductor substrate. CONSTITUTION:P type regions 2 and 3 are formed on an N type Si substrate 1, and an N type region 7 is formed on the region 3. Then, a photoresist 9 is coated on both surfaces of the substrate 1, an windows 10a and 10b for the mesa groove are provided on both sides of the substrate 1. Then, using a sand blasting method (a), the windows 10a and 10b are ground and the steppings 11a and 11b are formed at the ground section. Subsequently, windows 12a and 12b for the mesa groove are provided on the substrate 1 by performing a photoresist method, and an etching is simultaneously performed on the steppings 11a, 11b and a non-ground section. Thus, the mesa groove 13 of double negative bevel structure can be formed by the help of the stepping located between the ground layer region and the non-ground layer region and the difference of the chemical etching speed.
JP56034445A 1981-03-10 1981-03-10 Manufacture of mesa type semiconductor device Pending JPS57148371A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56034445A JPS57148371A (en) 1981-03-10 1981-03-10 Manufacture of mesa type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56034445A JPS57148371A (en) 1981-03-10 1981-03-10 Manufacture of mesa type semiconductor device

Publications (1)

Publication Number Publication Date
JPS57148371A true JPS57148371A (en) 1982-09-13

Family

ID=12414436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56034445A Pending JPS57148371A (en) 1981-03-10 1981-03-10 Manufacture of mesa type semiconductor device

Country Status (1)

Country Link
JP (1) JPS57148371A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6279667A (en) * 1985-10-03 1987-04-13 Mitsubishi Electric Corp Semiconductor device
US4680615A (en) * 1984-06-14 1987-07-14 Brown, Boveri & Cie Ag Silicon semiconductor component with an edge contour made by an etching technique, and method for manufacturing this component
EP0461879A2 (en) * 1990-06-12 1991-12-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having an isolating groove and method of making the same
CN106328696A (en) * 2015-06-30 2017-01-11 赛米控电子股份有限公司 Semiconductor device and manufacturing method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4680615A (en) * 1984-06-14 1987-07-14 Brown, Boveri & Cie Ag Silicon semiconductor component with an edge contour made by an etching technique, and method for manufacturing this component
JPS6279667A (en) * 1985-10-03 1987-04-13 Mitsubishi Electric Corp Semiconductor device
EP0461879A2 (en) * 1990-06-12 1991-12-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having an isolating groove and method of making the same
CN106328696A (en) * 2015-06-30 2017-01-11 赛米控电子股份有限公司 Semiconductor device and manufacturing method thereof
CN106328696B (en) * 2015-06-30 2021-06-18 赛米控电子股份有限公司 Semiconductor element and method for manufacturing semiconductor element

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