JPS56126922A - Forming method for automatic positioning pattern - Google Patents

Forming method for automatic positioning pattern

Info

Publication number
JPS56126922A
JPS56126922A JP3026180A JP3026180A JPS56126922A JP S56126922 A JPS56126922 A JP S56126922A JP 3026180 A JP3026180 A JP 3026180A JP 3026180 A JP3026180 A JP 3026180A JP S56126922 A JPS56126922 A JP S56126922A
Authority
JP
Japan
Prior art keywords
substrate
stages
positioning
etched
automatic positioning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3026180A
Other languages
Japanese (ja)
Other versions
JPS5944772B2 (en
Inventor
Minoru Matsumoto
Tsutomu Kamei
Nobuo Kawase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55030261A priority Critical patent/JPS5944772B2/en
Publication of JPS56126922A publication Critical patent/JPS56126922A/en
Publication of JPS5944772B2 publication Critical patent/JPS5944772B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To decrease processes, diminish errors and obtain large difference in stages by a method wherein an element pattern as well as an automatic positioning pattern are made up on an insulating film on a substrate, and the substrate is etched. CONSTITUTION:An SiO2 film 2 is made up on an Si substrate 3, and resist-masks 1 for forming an automatic positioning pattern and an element pattern are each built up to regions I, II. The film 2 is etched, the masks 1 are removed and B is introduced to the Si substrate by BBr3 in a nonoxidizable atmosphere. At the same time, Si is etched by Br, and difference in stages (a) is made up. When thermally treating the substrate, an impurity layer is expanded while Si is also oxidized to form SiO2, and the difference in stages of Si for positioning further expands to (b). According to this constitution, positioning accuracy is little because the number of man- hour of positioning is few, and large difference in stages is obtained.
JP55030261A 1980-03-12 1980-03-12 How to form automatic alignment pattern Expired JPS5944772B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55030261A JPS5944772B2 (en) 1980-03-12 1980-03-12 How to form automatic alignment pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55030261A JPS5944772B2 (en) 1980-03-12 1980-03-12 How to form automatic alignment pattern

Publications (2)

Publication Number Publication Date
JPS56126922A true JPS56126922A (en) 1981-10-05
JPS5944772B2 JPS5944772B2 (en) 1984-11-01

Family

ID=12298753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55030261A Expired JPS5944772B2 (en) 1980-03-12 1980-03-12 How to form automatic alignment pattern

Country Status (1)

Country Link
JP (1) JPS5944772B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119723A (en) * 1982-12-27 1984-07-11 Toshiba Corp Manufacture of semiconductor device
JPS60133735A (en) * 1983-12-21 1985-07-16 Fujitsu Ltd Manufacture of semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50161169A (en) * 1974-06-17 1975-12-26

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50161169A (en) * 1974-06-17 1975-12-26

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119723A (en) * 1982-12-27 1984-07-11 Toshiba Corp Manufacture of semiconductor device
JPH0352206B2 (en) * 1982-12-27 1991-08-09 Tokyo Shibaura Electric Co
JPS60133735A (en) * 1983-12-21 1985-07-16 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS5944772B2 (en) 1984-11-01

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