JPS56138941A - Forming method of wiring layer - Google Patents

Forming method of wiring layer

Info

Publication number
JPS56138941A
JPS56138941A JP4175380A JP4175380A JPS56138941A JP S56138941 A JPS56138941 A JP S56138941A JP 4175380 A JP4175380 A JP 4175380A JP 4175380 A JP4175380 A JP 4175380A JP S56138941 A JPS56138941 A JP S56138941A
Authority
JP
Japan
Prior art keywords
film
wiring layer
covered
patterning
thereafter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4175380A
Other languages
Japanese (ja)
Inventor
Kazuo Tokitomo
Chuichi Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4175380A priority Critical patent/JPS56138941A/en
Publication of JPS56138941A publication Critical patent/JPS56138941A/en
Pending legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the pattern accuracy of a wiring layer and protect the wiring layer against corrosion by utilizing an insulating layer for patterning the wiring layer. CONSTITUTION:An aluminum alloy film 10 is covered by evaporation through an insulating film 2 formed on the surface of a semiconductor substrate 1, a silicon nitride film (or a silicon oxide film) 11 is covered thereon, and a mask of a resist film 12 is formed thereon. Then, the film 11 is etched and removed for patterning. Thereafter, with the films 12 and 11 as masks the film 10 is reactively ion etched to pattern the wiring layer. Thereafter, when the film 12 is molten and removed, a wiring layer made of the film 10 covered with the silicon nitride film is formed. Thus, the resist film becomes sufficient only with half a thickness of the conventional one to improve the pattern accuracy of the wiring layer.
JP4175380A 1980-03-31 1980-03-31 Forming method of wiring layer Pending JPS56138941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4175380A JPS56138941A (en) 1980-03-31 1980-03-31 Forming method of wiring layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4175380A JPS56138941A (en) 1980-03-31 1980-03-31 Forming method of wiring layer

Publications (1)

Publication Number Publication Date
JPS56138941A true JPS56138941A (en) 1981-10-29

Family

ID=12617173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4175380A Pending JPS56138941A (en) 1980-03-31 1980-03-31 Forming method of wiring layer

Country Status (1)

Country Link
JP (1) JPS56138941A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5913329A (en) * 1982-07-03 1984-01-24 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Method of producing semiconductor device
JPS63110654A (en) * 1986-10-28 1988-05-16 Sony Corp Etching method
JPH02144916A (en) * 1988-11-26 1990-06-04 Sony Corp Formation of metal wiring pattern

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5913329A (en) * 1982-07-03 1984-01-24 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Method of producing semiconductor device
JPS63110654A (en) * 1986-10-28 1988-05-16 Sony Corp Etching method
JPH02144916A (en) * 1988-11-26 1990-06-04 Sony Corp Formation of metal wiring pattern

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