JPS5724547A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS5724547A JPS5724547A JP9936980A JP9936980A JPS5724547A JP S5724547 A JPS5724547 A JP S5724547A JP 9936980 A JP9936980 A JP 9936980A JP 9936980 A JP9936980 A JP 9936980A JP S5724547 A JPS5724547 A JP S5724547A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon nitride
- substrate
- nitride layers
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
PURPOSE:To prevent the substrate surface from warping and to improve the accuracy of etching by covering both the device forming surface and the opposite side with a silicon nitride layer simultaneously and removing said layer after forming a field oxide film. CONSTITUTION:After forming silicon nitride layers 12a on both sides of an N type silicon substrate 1, with only the layer 12a on the main surface left, the layer on the opposite said is removed. Then silicon nitride layers 13a, 13b are formed on both sides, and the main surface is covered with a photoresist layer 14 which is to be come a mask of prescribed pattern. A silicon nitride layer 13a' with prescribed pattern is formed by plasma-etching, and then ion inplantation is carried out to form an impurity diffused layer for channel-cut. The photoresist layer 14 is removed, and a field oxide layer 15 is formed. Then, the silicon nitride layers are removed. By this procedure, no warping of the substrate and accurate processing will result.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9936980A JPS5724547A (en) | 1980-07-22 | 1980-07-22 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9936980A JPS5724547A (en) | 1980-07-22 | 1980-07-22 | Manufacture of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5724547A true JPS5724547A (en) | 1982-02-09 |
Family
ID=14245624
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9936980A Pending JPS5724547A (en) | 1980-07-22 | 1980-07-22 | Manufacture of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5724547A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59107525A (en) * | 1982-12-13 | 1984-06-21 | Nec Corp | Semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52131462A (en) * | 1976-04-28 | 1977-11-04 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1980
- 1980-07-22 JP JP9936980A patent/JPS5724547A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52131462A (en) * | 1976-04-28 | 1977-11-04 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59107525A (en) * | 1982-12-13 | 1984-06-21 | Nec Corp | Semiconductor device |
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