JPS5693331A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5693331A
JPS5693331A JP17002979A JP17002979A JPS5693331A JP S5693331 A JPS5693331 A JP S5693331A JP 17002979 A JP17002979 A JP 17002979A JP 17002979 A JP17002979 A JP 17002979A JP S5693331 A JPS5693331 A JP S5693331A
Authority
JP
Japan
Prior art keywords
patterning
mask
type resist
plasma
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17002979A
Other languages
Japanese (ja)
Inventor
Keiji Nishimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17002979A priority Critical patent/JPS5693331A/en
Publication of JPS5693331A publication Critical patent/JPS5693331A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To attempt the elevation of precision of the patterning of the semiconductor device to be formed self-alignmently by a method wherein a positive type resist mask is formed in a region remaining a negative type resist mask in another region. CONSTITUTION:An MIS type semiconductor element region 14 and a circumferential circuit region 15 are formed on an Si substrate, and a CVD polycrystalline Si layer 1 is formed on the surface. Negative type resist masks 11, 11' are applied respectively on the regions 14, 15, and the patterning of gate electrodes 16, 17 is performed by plasma etching using CF4. Then a positive type resist mask 18 is accumulated selectively, the SiO2 film 3 is etched by plasma of CHF3 and the patterning of an under part electrode 2 is performed by plasma of CF4 again. By this constitution, the deformation or the discrepancy of position of the negative type mask is not generated when the positive type mask is to be formed, the patterns to be formed self-alignmently in accumulation can be formed together by dry etching, and the highly precise and highly integrated pattern can be obtained.
JP17002979A 1979-12-26 1979-12-26 Manufacture of semiconductor device Pending JPS5693331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17002979A JPS5693331A (en) 1979-12-26 1979-12-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17002979A JPS5693331A (en) 1979-12-26 1979-12-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5693331A true JPS5693331A (en) 1981-07-28

Family

ID=15897275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17002979A Pending JPS5693331A (en) 1979-12-26 1979-12-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5693331A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4916082A (en) * 1989-03-14 1990-04-10 Motorola Inc. Method of preventing dielectric degradation or rupture
US5173437A (en) * 1991-08-01 1992-12-22 Chartered Semiconductor Manufacturing Pte Ltd Double polysilicon capacitor formation compatable with submicron processing
US5188976A (en) * 1990-07-13 1993-02-23 Hitachi, Ltd. Manufacturing method of non-volatile semiconductor memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4916082A (en) * 1989-03-14 1990-04-10 Motorola Inc. Method of preventing dielectric degradation or rupture
US5188976A (en) * 1990-07-13 1993-02-23 Hitachi, Ltd. Manufacturing method of non-volatile semiconductor memory device
US5173437A (en) * 1991-08-01 1992-12-22 Chartered Semiconductor Manufacturing Pte Ltd Double polysilicon capacitor formation compatable with submicron processing

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