JPS55165636A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55165636A
JPS55165636A JP7372579A JP7372579A JPS55165636A JP S55165636 A JPS55165636 A JP S55165636A JP 7372579 A JP7372579 A JP 7372579A JP 7372579 A JP7372579 A JP 7372579A JP S55165636 A JPS55165636 A JP S55165636A
Authority
JP
Japan
Prior art keywords
mask
film
layers
produced
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7372579A
Other languages
Japanese (ja)
Inventor
Toshihiko Fukuyama
Masao Sugita
Shintaro Yanagisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP7372579A priority Critical patent/JPS55165636A/en
Publication of JPS55165636A publication Critical patent/JPS55165636A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To easily make a fine pattern, by using Al or Cr produced by a life-off method, for an etching mask for a film of a high-melting-point metal or its silicide. CONSTITUTION:Mo 14 is overlapped on a field oxide film 12 and a gate oxide film 13 on a p-type Si substrate 11. A resist mask 15 is provided to coat Al 16 by evaporation. Ultrasonic waves are then applied under acetone to remove the resist 15 and the Al thereon. The Mo 14 is etched by CF4 plasma through the Al mask. At that time, the etching ratio is 1:10<2> and the Mo is selectively removed. After that, the Al mask is removed by a diluted solution of hydrochloric acid so that a gate electrode of Mo is manufactured. N-layers 17, 18 are then provided. These layers are covered with Si3N4 19. An opening is made. An Al film 20 is produced. As a result, an FET is completed. According to time method, the change in pattern dimensions is minimized and a fine pattern can be obtained.
JP7372579A 1979-06-12 1979-06-12 Manufacture of semiconductor device Pending JPS55165636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7372579A JPS55165636A (en) 1979-06-12 1979-06-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7372579A JPS55165636A (en) 1979-06-12 1979-06-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55165636A true JPS55165636A (en) 1980-12-24

Family

ID=13526483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7372579A Pending JPS55165636A (en) 1979-06-12 1979-06-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55165636A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58164226A (en) * 1982-03-24 1983-09-29 Nippon Telegr & Teleph Corp <Ntt> Etching of semiconductor substrate
EP0126424A2 (en) * 1983-05-23 1984-11-28 International Business Machines Corporation Process for making polycide structures
JPS6175544A (en) * 1984-06-25 1986-04-17 テキサス　インスツルメンツ　インコ−ポレイテツド Making of semiconductor device
JPS6196735A (en) * 1984-10-17 1986-05-15 Toshiba Corp Conductor pattern forming process
JPS6453579A (en) * 1987-08-25 1989-03-01 Matsushita Electric Ind Co Ltd Method of forming microelectrode pattern
US5536364A (en) * 1993-06-04 1996-07-16 Nippon Soken, Inc. Process of plasma etching silicon

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58164226A (en) * 1982-03-24 1983-09-29 Nippon Telegr & Teleph Corp <Ntt> Etching of semiconductor substrate
EP0126424A2 (en) * 1983-05-23 1984-11-28 International Business Machines Corporation Process for making polycide structures
JPS6175544A (en) * 1984-06-25 1986-04-17 テキサス　インスツルメンツ　インコ−ポレイテツド Making of semiconductor device
JPS6196735A (en) * 1984-10-17 1986-05-15 Toshiba Corp Conductor pattern forming process
JPS6453579A (en) * 1987-08-25 1989-03-01 Matsushita Electric Ind Co Ltd Method of forming microelectrode pattern
US5536364A (en) * 1993-06-04 1996-07-16 Nippon Soken, Inc. Process of plasma etching silicon

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