JPS5629326A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5629326A
JPS5629326A JP10529679A JP10529679A JPS5629326A JP S5629326 A JPS5629326 A JP S5629326A JP 10529679 A JP10529679 A JP 10529679A JP 10529679 A JP10529679 A JP 10529679A JP S5629326 A JPS5629326 A JP S5629326A
Authority
JP
Japan
Prior art keywords
pattern
resist
aluminum
substrate
positive resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10529679A
Other languages
Japanese (ja)
Other versions
JPS5914889B2 (en
Inventor
Atsushi Ueno
Onori Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP54105296A priority Critical patent/JPS5914889B2/en
Publication of JPS5629326A publication Critical patent/JPS5629326A/en
Publication of JPS5914889B2 publication Critical patent/JPS5914889B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To eliminate breakdown of the edge of a positive resist pattern even if temperature rises during etching step by forming a photoresist pattern formed with negative type photoresist on side surface as an etching mask. CONSTITUTION:An Si oxide film 2 is formed on an Si substrate 1, and an aluminum film 3 is subseqnently formed thereon. Thereafter a positive resist pattern 4 is formed thereon. Then, a negative resist 5 is coatedon the surface of the substrate 1. Thereafter, the resist 5 is etched from the vertical direction of the surface of the substrate using an etching unit having strong vertical directivity to expose partly the aluminum electrode. At this time the resist 5 on the film 3 and on the pattern 4 is removed, but the part 5' of the resist 5 is retained on the side surface of the pattern 4. Subsequently, with the pattern 4 as a mask the exposed aluminum is etched, thereby forming an aluminum pattern 6 in the approximately same width as the pattern 4. Even if the temperature during the etching step rises higher than the softening temperature of the positive resist, the edge of the positive resist pattern may not break down.
JP54105296A 1979-08-17 1979-08-17 Manufacturing method of semiconductor device Expired JPS5914889B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54105296A JPS5914889B2 (en) 1979-08-17 1979-08-17 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54105296A JPS5914889B2 (en) 1979-08-17 1979-08-17 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5629326A true JPS5629326A (en) 1981-03-24
JPS5914889B2 JPS5914889B2 (en) 1984-04-06

Family

ID=14403719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54105296A Expired JPS5914889B2 (en) 1979-08-17 1979-08-17 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5914889B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59163829A (en) * 1983-03-08 1984-09-14 Matsushita Electronics Corp Pattern formation
JPS6010732A (en) * 1983-06-30 1985-01-19 Toshiba Corp Manufacture of semiconductor device
JPS60137023A (en) * 1983-12-26 1985-07-20 Fujitsu Ltd Forming method of pattern and device used for executing said method
EP0158357A2 (en) * 1984-04-13 1985-10-16 Nippon Telegraph And Telephone Corporation Method of forming resist micropattern
JPS61279689A (en) * 1985-06-05 1986-12-10 Nec Corp Structure of etching mask having protective film for side wall and its production
JPS62120030A (en) * 1985-11-20 1987-06-01 Toshiba Corp Forming method for fine pattern
JPH08236526A (en) * 1994-12-22 1996-09-13 Siemens Ag Method of making all surfaces of wafer for integrated circuit device global plane or flattening it

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0953273A (en) * 1995-08-14 1997-02-25 Masaya Nagashima U-shaped gutter

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59163829A (en) * 1983-03-08 1984-09-14 Matsushita Electronics Corp Pattern formation
JPS6010732A (en) * 1983-06-30 1985-01-19 Toshiba Corp Manufacture of semiconductor device
JPS60137023A (en) * 1983-12-26 1985-07-20 Fujitsu Ltd Forming method of pattern and device used for executing said method
EP0158357A2 (en) * 1984-04-13 1985-10-16 Nippon Telegraph And Telephone Corporation Method of forming resist micropattern
JPS61279689A (en) * 1985-06-05 1986-12-10 Nec Corp Structure of etching mask having protective film for side wall and its production
JPS62120030A (en) * 1985-11-20 1987-06-01 Toshiba Corp Forming method for fine pattern
JPH08236526A (en) * 1994-12-22 1996-09-13 Siemens Ag Method of making all surfaces of wafer for integrated circuit device global plane or flattening it

Also Published As

Publication number Publication date
JPS5914889B2 (en) 1984-04-06

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