JPS6010732A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enlarge widths of wirings, and to enable to remove an increase of resistance and disconnection at the step parts of the wirings by a method wherein a protective film is anisotropically etched to leave the protective film on the side walls of a mask material, and after then, the wiring film is selectively etched to be removed using the remaining protective film and the mask material. CONSTITUTION:After an SiO2 film pattern 14 is formed according to the PEP method on a polycrystalline silicon layer 13, a CVD-SiO2 film 15 is formed on the whole surface, and the CVD-SiO2 film 15' is left only on the side walls of the SiO2 film pattern 14 according to the RIE method. Because the polycrystalline silicon layer 13 is etched to be removed using the remaining CVD-SiO2 film 15' and the SiO2 film pattern 14 thereof as masks to form wirings 16, 16, the interval between the wirings 16, 16 can be reduced by the amount corresponding to the remaining CVD-SiO2 films 15', namely by 2L, and widths of the wirings can be enlarged by the amount thereof.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to an improvement in a method for manufacturing a semiconductor device.

,gu;□ [:3 Technical background of the invention and its problems] Conventionally,
When forming wiring on a semiconductor substrate or performing element isolation using an element isolation method such as the LOCO8 method, a four-turn regimen is used.

First, the case of forming wiring on a semiconductor substrate will be described with reference to FIGS. That is, as shown in FIG. 1(a), an insulating film 2 and a wiring material film 3 are formed on a semiconductor substrate 1, and then a cyst tJ?turn 4 is formed by photolithography (PEP method).

Next, using this resist pattern 4 as a mask, the wiring material film 3 is selectively etched away to form wirings 5, 5, and the resist pattern 4 is peeled off to manufacture a semiconductor device (FIG. 1(b)). (Illustrated).

However, according to this manufacturing method, since the wirings 5, 5 are formed by photolithography, due to the limitations of phosphorography, the length t) and the spacing (
dl) is subject to restrictions. Therefore, if dl becomes long and t becomes short, or if the wiring 5.5 has a high resistance, disconnection is likely to occur. In particular, the breakage becomes more noticeable in areas where the base of the wirings 5, 5 is uneven.

Next, a case where element isolation is performed using the LOCO8 method will be described with reference to FIGS. 2(a) to 2(c).

First, an insulating film 2 is formed on a semiconductor substrate 1, and then, for example, a Si, N4 film (not shown) is formed on this insulating film 2. Subsequently, on this 813N4 film, a resist groove 6 having an opening corresponding to a portion where an element isolation region is to be formed is formed by the PEP method.

Next, using this resist pattern 6 as a mask, the 513N4 film is selectively etched away, and the Si 3
A N4 film layer 7 is formed (as shown in FIG. 2(a)).

Note that d2 in FIG. 2(a) indicates the interval between the S i and N4 film patterns 7.7. Furthermore, the resist no-turns 6 are peeled off (as shown in FIG. 2(b)), and heat treatment is performed using the Si3N4 film pattern 7 as a mask to form an element isolation region 8.
A semiconductor device is manufactured (as shown in FIG. 2(C)).

However, this manufacturing method has the disadvantage that during heat treatment, the element isolation region 8 expands laterally below the Si3N4 film pattern 7, creating a so-called bird's beak, and that the flat turn conversion difference increases.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and includes wiring 1]
It is an object of the present invention to provide a method of manufacturing a semiconductor device with a small difference in cross-turn conversion, as well as to prevent high resistance and disconnection of wiring by widening the wiring.

[Summary of the invention]

In the present invention, a film is formed on a semiconductor substrate via an insulating film, a mask material is formed on the film, a protective film is then formed on the entire surface, and this protective film is further anisotropically etched. leaving a protective film on at least the side wall of the mask material;
After that, by selectively etching and removing the film using the remaining protective film and mask material, the main idea is to prevent the wiring from becoming high in resistance and breakage, and to reduce the lid/conversion difference. . 1 [Embodiments of the Invention] The present invention will be described below with reference to FIGS. 3(a) to (d) and FIGS. 4(a) to 4.
This will be explained with reference to (d).

Example 1 [i] First, a thermal oxide film 12 with a thickness of about 900× as an insulating film and a polycrystalline silicon layer 13 with a thickness of about 6000× as a coating were sequentially formed on an 81 substrate 11 as a semiconductor substrate. Subsequently, by using the PEP method, a 51 mm film having a thickness of about 6,000 mm is applied as a mask material on this polycrystalline silicon layer 13.
After forming the 02 film pattern 14, a CVD-8102 film 15 having a thickness of about 60001 (7) as a protective film was formed on the entire surface (as shown in FIG. 3(a)).

Next, this CVD-S t O2 film 15 is anisotropically etched by reactive ion etching (RIE), and CVD-8 is etched only on the sidewalls of the 5102 film pattern 14.
The +02 film 15' was left (as shown in FIG. 3(b)).

Next, the remaining CVD-8102 film 15' and St
Using the O2 film pattern 14 as a mask, the exposed polycrystalline silicon layer 13 is selectively etched away, and the wiring 16.
16 (as shown in FIG. 3(C)). Next, the remaining CVD-SsO2 film 15' and the 8tO2 film pattern 14 were removed, and a semiconductor device was manufactured (as shown in FIG. 5-3(d)).

According to the present invention, after forming the 5IO2 film pattern 14 on the polycrystalline silicon layer 13 by the PEP method,
A CVD-8i02 film 15 is formed on the entire surface, and CVD-8i02 is deposited only on the 5iO2 film and the side walls of the turns 14 by RIE method.
o2 film 15' remains, and this remaining CvD-8Io2 film 15' and 8102 film IJ? Using the turn 14 as a mask, the polycrystalline silicon layer 13 is etched away and the wiring 16.
16, the spacing between the wires 16 and 16 is set to the conventional (d
l), the amount corresponding to the remaining CVD-S io 2 film 15', that is, 2L (2X approximately 5000X) = 100OO
It can be shortened by X and its distribution line width can be widened. therefore,
Compared to the conventional method, lower resistance of wiring 16.16 can be achieved,
Can prevent disconnection.

The above is for 5IO2 membrane/# Tough 14 and CV
It can be controlled by the thickness of the D-8IO2 film 15 and etching conditions.

Example 2 (i) First, on an 81 substrate 11, a thermal oxide film 12 with a thickness of about 900X, a polycrystalline silicon layer 17 with a thickness of about 500X, an S15N4 film 18 with a thickness of about 2500X, and a After forming a SiO□ film pattern 14 of about 6000×, a CVD-S IO2 skin 15 of about 6000× thick was formed on the entire surface (as shown in FIG. 4(a)). Subsequently, in the same manner as in Example 1, a residual CVD-SiO2 film 15' was formed on the side wall of the four turns 14 of the SiO□ film (see Fig. 4).
b) As shown).

[11] Next, the remaining CVD-8102 film 15' and S
Using the iOJ pattern 14 as a mask, the S i , N
4 film 18 was etched away by RIE method, and 513N
4j made turn 18'. At this time, the remaining CV
The D-SiO2 film 15' and the 5102 film pattern 14 were also etched away to some extent. Note that the etching in the portion where the element isolation region is to be formed was stopped at the underlying polycrystalline silicon layer 17 (as shown in FIG. 4(c)). Next, the remaining CVD-S iO2 film 15' and 5IO2 film i!
p714 (illustrated in Figure 4(d)).

Therefore, according to the present invention, PE is applied on the 513N4 film 18.
After forming a 5in2 film pattern 14 by the P method, a CVD-SiO2 film 15 is formed on the entire surface, and a CVD-8 film is deposited only on the side wall of the 5IO2 film turn 14 by the RIE method.
The t02 film 15' remains and this remaining CVD-8in2
Using the film 15' and the SiO film no.f turn 14 as a mask, S
The i3N4 film 18 is etched away using the RIE method.
To form the 13N4 membrane turn 18', 5i5N
The distance between the 4 membrane R turns 18' and 1 B' was changed to the conventional (d
Compared to 2), the amount corresponding to the remaining CVD-S t 02 film 15' can be reduced by 2L=2X5000=10000X. Therefore, 513N4 film pattern 1 B',
When the element isolation region 19 is formed by heat treatment using the mask 18' as a mask, the difference in Tscutane conversion can be made smaller than in the conventional case.

In the above embodiment, the case where the CVD-S i O 2 film remains only on the side wall of the SiO 2 film pattern has been described, but the present invention is not limited to this. For example, CVD-S r 0
A slight amount of the 2 film may remain not only on the sidewalls of the 5iO7 film pattern but also on the nof turns. ] [Effects of the Invention] As detailed above, according to the present invention, high resistance of wiring,
It is possible to provide a method for manufacturing a highly reliable semiconductor device that can prevent disconnection and perform element isolation with little conversion difference.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are cross-sectional views showing a conventional method for manufacturing a semiconductor device in order of steps, and FIGS. 2(a) to (c) are cross-sectional views showing another conventional method for manufacturing a semiconductor device in order of steps. 3(a) to 3(d) are cross-sectional views showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention in order of steps, and FIG. 4(a) to 4(d)
2A and 2B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention in order of steps. 11... Si substrate (semiconductor substrate), 12... Thermal oxide film (insulating film), 13... Polycrystalline silicon layer (coating),
14...5102 membrane f turn (mask material), 15.
...CVD-8102 film (protection), 15'...Remaining CVD-8i02 film, 16...Wiring, J 8-81
．． N4 film, 1 B'・5t5N4 film pattern, 19...
・Element isolation area. Applicant's agent Patent attorney Takehiko Suzue 9-

Claims (2)

[Claims] (1) A process of forming a film on a semiconductor substrate via an insulating film, a process of forming a mask material on this film, a process of forming a protective film on the entire surface, and anisotropic etching of this protective film. A semiconductor device manufacturing apparatus comprising: a step of leaving a protective film on at least the side wall of the mask material; and a step of selectively etching and removing the film using the remaining protective film and the mask material. . (2) The method for manufacturing a semiconductor device according to claim 1, wherein the coating is a conductive material film.