JPH0478141A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain sufficient flatness even for a fine wiring pattern by etching back first and second resist layers which are substantially united to each other in one body and an interlayer insulating film below the first and second resist layers at an etching quantity at which a wiring layer is not exposed. CONSTITUTION:A first resist layer 4 is formed by performing exposure and development with the inverted pattern of wiring 2 after a resist is applied onto an interlayer insulating film 3. After the resist layer 4 is hardened by baking or UV irradiation, the insulating film 3 positioned to the opening section of the resist mask 4 is etched in a controlled state with an acidic diluted solution of HF, etc. Then a second resist layer 5 is applied and the entire surface is etched by RIE using Freon gas under a condition where the wiring layer 2 is not exposed. Thereafter, the resist layers 4 and 5 are removed with O2 plasma and, in order to improve the interlayer insulating property, an Al wiring layer 7 is formed by sputtering and etching using a chlorine gas after an interlayer insulating film 6 of a silicon oxide containing P is formed by CVD.

Description

[Detailed Description of the Invention] [Summary] Regarding a method of manufacturing a semiconductor device, particularly a method of manufacturing a semiconductor device with improved planarization processing, fine (Ajl!
The purpose is to provide a semiconductor device manufacturing method that can obtain sufficient flatness even with wiring patterns (pattern rule 2, um or less for wiring, 1 μm or less for poly-3i wiring), forming a first resist layer with an inverted pattern of the wiring pattern on the interlayer insulating film formed covering the wiring layer; using the first resist layer as a mask, exposing the wiring layer; a step of etching back the interlayer insulating film with an etching amount that does not expose the wiring layer; a step of forming a second resist layer while filling the opening of the mask in the first resist layer; and a step of etching back the interlayer insulation film with an etching amount that does not expose the wiring layer. The method includes a step of etching back the first and second resist layers and the interlayer insulating film thereunder by dry etching.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device with improved planarization processing.

[Conventional technology]

In the manufacturing of semiconductor devices, A! wiring or p.

The formation technology of multilayer wiring structure using 1y-5i wiring etc. is as follows.
As semiconductor devices become more highly integrated, it is required to simultaneously support miniaturization and multilayering. In particular, in order to reliably prevent poor coverage and disconnection of miniaturized wiring, it is necessary to improve the flatness of the interlayer insulating film.

Conventional planarization methods using interlayer insulating films include SOn cloth,
Bias spa γ-curing method, bias ECR method, selective CVD method, etch-back method, etc. are used.

Among these, the etch-back method is quite commonly adopted from the viewpoint of productivity, economy, etc. Etch-back methods include methods using resist and SOG (span-on-group) methods.
There is a method that uses a flattened glass (also referred to as "R-coated glass"), but the former is much more advantageous than the latter in terms of the cost of the flattening material and the number of manufacturing steps, so it is not practical as a flattening technique. is extremely useful.

Problems to be Solved by the Invention] However, in the conventional resist-based etchback method, when the pattern rule (wiring width, wiring spacing) becomes a fine pattern of, for example, 2 μm or less for AIl wiring and 1 μm or less for poly-5i wiring, However, there was a limitation in that it was not possible to obtain sufficient flatness.

Therefore, there is a problem in that an etch-back method using SOG or other planarization method must be used.

In the present invention, a pattern rule of 2 μm for fine wiring (l wiring) is achieved by flattening using an etch-back method using a resist.
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which sufficient flatness can be obtained even with the following wiring patterns.

[Means to solve the problem]

According to the present invention, the planarization process for forming a multilayer wiring structure is performed by applying a first resist layer with an inverted pattern of the wiring pattern on an interlayer insulating film formed covering the wiring layer. using the first resist layer as a mask, etching back the interlayer insulating film with an etching amount that does not expose the wiring layer; filling the opening of the mask in the first resist layer; forming a substantially integral resist layer consisting of the first and second resist layers by forming a second resist layer; This is achieved by a method for manufacturing a semiconductor device, which includes the step of etching back the first and second resist layers and the interlayer insulating film thereunder by dry etching.

[Effect]

The improvement in flatness by the interlayer insulating film depends on the leveling of the unevenness of the interlayer insulating film, that is, the degree to which relative depressions and relative protrusions in the interlayer insulating film are eliminated.

In the present invention, first, in the first etch noting step, the interlayer insulating film is etched back using a first resist layer formed with an inverted pattern of the wiring pattern as a mask to an etching amount that does not expose the wiring layer. As a result, the interlayer insulating film immediately above the wiring layer, that is, the relatively raised portion of the interlayer insulating film in the second stage, is selectively removed.

Next, by filling the opening of the mask formed by the second resist layer with a second resist layer, an integral resist layer consisting of the first and second resist layers is formed.

Next, in the second etch-back process, the integrated first and second resist layers and the interlayer insulating film (the remaining portion after the first-stage etch-back) are dry-etched with an etching amount that does not expose the wiring layer. Have sex back. This second
The stepwise etchback process mainly has the following two effects. That is, (1) due to the limit of coverage when forming an interlayer insulating film, small depressions are left in the interlayer insulating film in areas where the wiring spacing is particularly small. Since the protruding portion of the interlayer insulating film has been removed by the first stage etch hack,
Etching effectively works on even small depressions that remain in conventional etch-back, and the elimination of the depressions is promoted. (2) In the first stage etch bank, the protruding portion of the interlayer insulating film directly above the wiring is selectively removed, but in the band along the profile of the mask (first resist layer) and the area directly under the mask, the etching wraps around. Fine irregularities occur due to the non-uniformity of the surface. In the second stage etchback, such fine irregularities are also removed.

As described above, according to the present invention, the first and second stage etch packs can eliminate small irregularities in the interlayer insulating film that could not be eliminated with the conventional etch-back method, and can improve the pattern rule, which was considered to be the limit in the past. 2μ in case of Aβ wiring
Sufficient planarization can be achieved with m5poly-3i wiring even with a pattern rule finer than 1 μm.

In the following, the invention will be explained in more detail by means of examples with reference to the accompanying drawings.

〔Example〕

According to the present invention, planarization was performed by the procedure shown in FIGS. 1(a) to 1(g).

Step (a): On the Si substrate 1, an Aβ wiring layer 2 (thickness 1 μm 1
A minimum pattern rule of 1.5 μm) was formed.

Step (b): By CVD, an interlayer insulating film 3 of a P-containing silicon oxide film is formed covering the wiring layer 2 (with a thickness of 8000 mm at the flat part).
~10,000 people (=1 μm)) were formed.

Hereinafter, steps (C) to (f) are planarization processing steps.

Step (C): After applying a resist to a thickness of 1 μm on the interlayer insulating film 3, exposure and development were performed using an inverted pattern of the wiring 2 formed in step (a) to form a second resist layer 4. The resist layer 4 acts as a mask having openings in the raised portions of the interlayer insulating film 3 in the next etching step.

Step (d) After curing the resist layer 4 by beta or UV irradiation, etching was performed with an acid diluted solution such as HF, and the interlayer insulating film 3 located in the opening of the resist mask 4 was controlled by about 2000 people. . Etching in this step may be performed by wet etching as described above, or may be performed using Freon gas (CF, CF3, C
It may be performed by dry etching such as RIE using Fe, etc.).

Step (e): A second resist layer 5 was applied and the entire surface was etched by RIE using Freon gas. that time,
The amount of etching was approximately 6000, and the wiring layer 2 was not exposed.

Step (f): Resist layers 4 and 5 are removed by 0□ plasma.
was removed.

As a result of the above, it was possible to eliminate the minute depressions 8 in the interlayer insulating film 3 that existed between the wirings of the minimum pattern rule (1.5 μm) during the formation of the interlayer insulating film in step (b).

Step (g): In order to further improve the interlayer insulation, an interlayer insulation film 6 (5000 mm thick at the flat part) made of a P-containing silicon oxide film was formed on (the remaining part of) the interlayer insulation film 3 by CVD. Thereafter, an Aβ wiring layer 7 was formed by sputtering and etching with chlorine gas.

[Conventional example]

For comparison, a wiring pattern similar to that of the example was flattened using a conventional method according to the steps shown in FIGS. 2(a) to 2(e).

The step (a) of forming the wiring layer 2 and the step (b) of forming the interlayer insulating film 3 are the same as steps <a> and (b) of the embodiment.

Hereinafter, steps (c) to (d) are planarization processing steps.

Step (C): A resist was applied to a thickness of 1 μm on the interlayer insulating film 3.

Step (d): The entire surface was etched by RrE using Freon gas. At that time, the amount of etching was approximately 6000, and the wiring layer 2 was not exposed.

Although the above planarization was carried out, it was not possible to sufficiently eliminate the minute depressions 8 in the interlayer insulating film 3 that existed between the wirings of the minimum pattern rule (I, 5 μm) during the formation of the interlayer insulating film in step (b). There wasn't.

Step (e): As in the example, after further forming an interlayer insulating film 6 to improve interlayer insulation, an Aβ wiring layer A was formed.

Note that etchback (
The total etching amount in step (d)) of the example and the etch back after forming the second resist layer (step (e) of the example) is 1/2 to 1/3 of the thickness of the interlayer insulating film that had been formed
The degree is generally appropriate.

In the above example, the case of a multilayer wiring structure using A1 wiring was explained, but even when poly-5i wiring is used, multilayer wiring with a fine pattern with a pattern rule of 1 μm, which could not be sufficiently flattened with the conventional method. Regarding the structure, the same planarization as in the above example could be performed.

[Effects of the Invention] As explained above, according to the present invention, in a method for manufacturing a semiconductor device having a multilayer wiring structure, a pattern rule of 2 μm or less and a poly -5i wiring can achieve sufficient planarization even in a fine wiring pattern with a pattern rule of 1 μm or less.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device in which a multilayer wiring structure is formed by performing a planarization process according to the present invention, and FIG. FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor device to be formed. l...Substrate, 2,7...Wiring layer, 3.6...
- Interlayer insulating film, 4.5... Resist layer, 8... Recess in interlayer insulating film 6. Ll figure

Claims (1)

[Claims] 1. A planarization process for forming a multilayer wiring structure includes forming a first resist layer with an inverted pattern of the wiring pattern on an interlayer insulating film formed to cover the wiring layer. a step of etching back the interlayer insulating film using the first resist layer as a mask with an etching amount that does not expose the wiring layer; etching a second resist layer while filling the opening of the mask in the first resist layer; and a step of etching back the first and second resist layers and the interlayer insulating film thereunder by dry etching with an etching amount that does not expose the wiring layer. Method of manufacturing the device. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising forming an interlayer insulating film on the interlayer insulating film after the etch-back step after forming the second resist layer. 3. The total etching amount of the etch-back using the first resist layer as a mask and the etch-back after forming the second resist layer is equal to the amount of the interlayer insulation formed before forming the first resist layer. 1/2 to 1/ of the film thickness
3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein: