JPS6255701B2 - - Google Patents
Info
- Publication number
- JPS6255701B2 JPS6255701B2 JP55033648A JP3364880A JPS6255701B2 JP S6255701 B2 JPS6255701 B2 JP S6255701B2 JP 55033648 A JP55033648 A JP 55033648A JP 3364880 A JP3364880 A JP 3364880A JP S6255701 B2 JPS6255701 B2 JP S6255701B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- insulating film
- wiring body
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 5
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- 239000011737 fluorine Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 14
- 238000000034 method Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は多層配線を有する半導体装置を製造す
る方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having multilayer wiring.
従来、多層配線を形成する方法として、例えば
第１図に見られるように、第１層目配線１を絶縁
膜２で覆い、該絶縁膜２にコンタクト穴（viaホ
ール）２ａを形成し、その後、第２層目配線３を
形成するものが知られている。 Conventionally, as shown in FIG. 1, a conventional method for forming multilayer wiring includes covering a first layer wiring 1 with an insulating film 2, forming a contact hole (via hole) 2a in the insulating film 2, and then , which form the second layer wiring 3 are known.
しかしながら、これに依るとコンタクト穴２ａ
を配線１上に正確に位置合せして形成しなければ
ならないこと、またエツチング精度を出し難いこ
と、更にまた矢印で示したようなカバレイジの悪
さに依り配線３が断線し易いことなどの問題があ
る。 However, according to this, the contact hole 2a
There are other problems such as the need to form the wire 3 with precise alignment on the wiring 1, the difficulty in achieving high etching accuracy, and the fact that the wiring 3 is easily disconnected due to poor coverage as shown by the arrow. be.
本発明は多層配線を形成する際に、配線層間を
結ぶためのコンタクト穴を形成しなくて済むよう
に、また段差に起因する上層配線の断線が起らな
いようにすることを目的とするものであり、その
目的は本発明によれば、多層配線構造を有する半
導体装置の製造方法において、半導体基板上に配
線膜を形成し、前記配線膜とは弗素系の反応ガス
によるドライエツチングに対する被エツチングレ
ートの異なる導電材料よりなる導電体膜を形成す
る工程と、前記導電体膜及び配線膜を部分的に除
去して前記配線膜よりなる所定パターンの第１の
配線体を形成する工程と、前記第１の配線体が形
成されていない前記半導体基板上の部分に前記第
１の絶縁膜を前記配線膜と導電体膜の接続面より
表面がやや高くなるように被着形成する工程と、
弗素系反応ガスのドライエツチングにより前記第
１の配線体上の前記導電体膜を部分的に除去して
前記第１の配線体より狭い柱状突起体を形成する
と共に、記第１の絶縁膜をその表面が配線膜と導
電体膜の接続面の高さとほぼ同じになるよう除去
する工程と、前記柱状突起体の側周を囲み前記第
１の配線体及び前記第１の絶縁膜の上面を覆う第
２の絶縁膜を形成する工程と前記柱状突起体及び
前記第２の絶縁膜の上に第２の配線体を形成する
工程とを含むことを特徴とする半導体装置の製造
方法を提供することにより達成される。 The present invention aims to eliminate the need to form contact holes to connect wiring layers when forming multilayer wiring, and to prevent disconnection of upper layer wiring due to differences in level. According to the present invention, the purpose is to form a wiring film on a semiconductor substrate in a method of manufacturing a semiconductor device having a multilayer wiring structure, and to form a wiring film on a semiconductor substrate, the wiring film is a material to be etched by dry etching using a fluorine-based reactive gas. a step of forming a conductor film made of a conductive material having a different rate; a step of partially removing the conductor film and the wiring film to form a first wiring body having a predetermined pattern made of the wiring film; forming the first insulating film on a portion of the semiconductor substrate where the first wiring body is not formed so that the surface thereof is slightly higher than the connection surface between the wiring film and the conductive film;
Partially removing the conductive film on the first wiring body by dry etching with a fluorine-based reactive gas to form columnar protrusions narrower than the first wiring body, and removing the first insulating film. a step of removing the surface so that the height is almost the same as a connection surface between the wiring film and the conductive film; Provided is a method for manufacturing a semiconductor device, comprising the steps of forming a covering second insulating film and forming a second wiring body on the columnar protrusion and the second insulating film. This is achieved by
以下本発明の一実施例を図面に従つて詳細に説
明する。 An embodiment of the present invention will be described in detail below with reference to the drawings.
第２図は本発明の半導体装置の製造方法の一実
施例を工程の順に示す要部断面図である。 FIG. 2 is a cross-sectional view of a main part showing an embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps.
先ず、同図ａに示すように表面に絶縁層１１を
形成した半導体基板１０上に、例えばアルミニウ
ム（Al）よりなる第１層目の配線膜１２とその
上に、例えばモリブデン（Mo）のような導電材
料よりなる導電体膜１３を形成する。その方法は
蒸着法、スパツタリング法など適宜用いて良い。
また第１層目配線膜１２と導電体膜１３の材質は
同一エツチング剤に対して被エツチングレートが
大きく異なる組み合せを選べば良い。例えば第１
層目の配線膜１２にアルミニウムを用いた場合に
は導電体膜１３はモリブデン（Mo）のほか、
MoSr2，Ｗ，Cr.TiW，WSi2，Ta，Hf，Zr等を用
いることができる。 First, as shown in FIG. 1A, on a semiconductor substrate 10 with an insulating layer 11 formed on its surface, a first layer wiring film 12 made of aluminum (Al), for example, and a layer made of molybdenum (Mo), etc. A conductor film 13 made of a conductive material is formed. As the method, a vapor deposition method, a sputtering method, or the like may be used as appropriate.
Furthermore, the materials of the first layer wiring film 12 and the conductor film 13 may be selected from combinations having greatly different etching rates for the same etching agent. For example, the first
When aluminum is used for the wiring film 12 of the third layer, the conductor film 13 is made of molybdenum (Mo),
MoSr 2 , W, Cr.TiW, WSi 2 , Ta, Hf, Zr, etc. can be used.
次いで同図ｂに示すようにホトレジスト膜１４
をマスクとしてドライエツチング法を用いて導電
体膜１３及び第１層目の配線膜１２のパターニン
グを行なう。例えばまず四弗化炭素（CF4）等弗
素系ガスを用いたプラズマエツチング法により
Moよりなる導電体膜１３を選択的に除去し、次
に四塩化炭素（CCl4）等の塩素系ガスを用いたプ
ラズマエツチング法により第１層目の配線膜１２
を選択的に除去する。これにより先ず第１の配線
体１２が形成された。 Next, as shown in FIG.
The conductor film 13 and the first layer wiring film 12 are patterned using a dry etching method using the mask as a mask. For example, first, a plasma etching method using a fluorine gas such as carbon tetrafluoride (CF 4 ) is used.
The conductor film 13 made of Mo is selectively removed, and then the first wiring film 12 is removed by plasma etching using a chlorine gas such as carbon tetrachloride (CCl 4 ).
selectively remove. As a result, the first wiring body 12 was first formed.
次いで同図ｃに示すように一酸化シリコン，二
酸化シリコン等を蒸着する等の方法により被着せ
しめて第１の絶縁膜１５を前記第１の配線体１２
の厚さより稍厚く形成する。 Next, as shown in FIG. 3C, a first insulating film 15 is formed on the first wiring body 12 by depositing silicon monoxide, silicon dioxide, etc., by a method such as vapor deposition.
Form slightly thicker than the thickness of.
次いで同図ｄに示すように、前記ホトレジスト
膜１４を除去することによりその上に被着せる第
１の絶縁膜１５を同時に除去し、新たにホトレジ
スト膜１６を形成する。該ホトレジスト膜１６は
形成すべき柱状突起体のパターンを有するものと
する。そしてこのホトレジスト膜１６をマスクと
して前述のCF4を反応ガスとするプラズマエツチ
ング法により導電体膜１３をパターニングして第
１の配線体１２上に柱上突起体１３を形成する。
この場合Alよりなる第１の配線体１２はエツチ
ングされないが、第１の絶縁膜１５に用いた一酸
化シリコン，二酸化シリコンは若干エツチングさ
れる。例えば上記プラズマエツチングにおいて反
応圧力を0.7〔Torr〕，印加電力を200〔Ｗ〕とす
ると被エツチングレートはMoが約700〔Å／
分〕，二酸化シリコン（SiO2）は約150〔Å／分〕
となる。従つて導電体膜１３の厚さを約0.7〔μ
ｍ〕とすれば、これのパターニングに約10〔分〕
を要するので、第１の絶縁膜１５を予め第１の配
線体１２の厚さより約1500〔Å〕厚く形成してお
くことにより、柱状突起体１３の形成終了時に第
１の絶縁膜１５と第１の配線体１２とほぼ同一厚
さとすることができる。 Next, as shown in FIG. 4D, by removing the photoresist film 14, the first insulating film 15 deposited thereon is simultaneously removed, and a new photoresist film 16 is formed. The photoresist film 16 has a pattern of columnar protrusions to be formed. Then, using this photoresist film 16 as a mask, the conductive film 13 is patterned by the plasma etching method using CF 4 as a reactive gas, thereby forming pillar projections 13 on the first wiring body 12 .
In this case, the first wiring body 12 made of Al is not etched, but the silicon monoxide and silicon dioxide used for the first insulating film 15 are slightly etched. For example, in the above plasma etching, if the reaction pressure is 0.7 [Torr] and the applied power is 200 [W], the etching rate for Mo is about 700 [Å/
minute], silicon dioxide (SiO 2 ) approximately 150 [Å/min]
becomes. Therefore, the thickness of the conductor film 13 is set to about 0.7 [μ
m], it will take about 10 minutes to pattern this.
Therefore, by forming the first insulating film 15 to be about 1500 Å thicker than the first wiring body 12 in advance, the first insulating film 15 and the first The thickness can be approximately the same as that of the wiring body 12 of No. 1.
次いで同図ｅに示すように、再びSiO2を柱状
突起体１３とほぼ同じ厚さに蒸着して第２の絶縁
膜１７を形成し、更に前記ホトレジスト膜１６を
除去し、その上に被着せる第２の絶縁膜も同時に
除去する。このようにして同図ｆに示すように将
来形成する上層の配線体の下地を平担に形成する
ことができる。 Next, as shown in FIG. 5e, SiO 2 is again deposited to approximately the same thickness as the columnar projections 13 to form a second insulating film 17, and the photoresist film 16 is removed and a second insulating film 17 is deposited thereon. The second insulating film is also removed at the same time. In this way, the base of the upper layer wiring body to be formed in the future can be formed evenly, as shown in FIG.
このあとの工程は通常の方法に従つて進めて良
い。即ち同図ｇに示すようにAl等の金属を蒸着
し、これをパターニングすることにより、第２の
配線体１８を形成して多層配線構造が完成する。 The subsequent steps may be carried out in the usual manner. That is, as shown in FIG. 7G, a metal such as Al is deposited and patterned to form the second wiring body 18 and complete the multilayer wiring structure.
上述の説明で判るように本実施例で得られた多
層配線構造においては、下地表面が平担に形成さ
れるので、その上層の配線体に段差による断線を
生じることがなく、しかも層間絶縁膜にコンタク
ト穴の形成が不要になるので、その位置合せ不良
やエツチング精度不良の問題が除去された。 As can be seen from the above description, in the multilayer wiring structure obtained in this example, the underlying surface is formed flat, so there is no disconnection due to steps in the upper wiring layer, and moreover, the interlayer insulating film Since it is no longer necessary to form contact holes, the problems of poor alignment and poor etching accuracy are eliminated.
上記実施例においては、第１及び第２の絶縁膜
の最終厚さを夫々第１の配線体及び柱状突起体の
厚さと一致させたが、これは必ずしも厳密に一致
している必要はなく、80〜120〔％〕程度の範囲
で許容できる。 In the above embodiment, the final thickness of the first and second insulating films was made to match the thickness of the first wiring body and the columnar protrusion, respectively, but this does not necessarily have to be exactly the same. A range of about 80 to 120 [%] is acceptable.
更に本発明は上記実施例に示した二層配線のみ
でなく、三層以上の多層配線の形成に用いて良い
ことは容易に理解されよう。 Furthermore, it will be easily understood that the present invention can be used not only for the two-layer wiring shown in the above embodiments, but also for the formation of multilayer wiring of three or more layers.
以上説明したごとく、本発明によれば多層配線
を段差に起因する断線等を生じることなく、高精
度且つ容易に形成できる。 As described above, according to the present invention, multilayer wiring can be easily formed with high precision without causing disconnections or the like due to differences in level.
第１図は従来の多層配線の形成方法の説明に供
する要部断面図、第２図は本発明の半導体装置の
製造方法の一実施例を工程の順に示す要部断面図
である。
１０は半導体基板、１１は絶縁膜、１２は第１
の配線体（配線膜）、１３は柱状突起体（導電体
膜）、１５は第１の絶縁膜、１７は第２の絶縁
膜、１８は第２の配線体。
FIG. 1 is a cross-sectional view of a main part used to explain a conventional method for forming multilayer wiring, and FIG. 2 is a cross-sectional view of a main part showing an embodiment of a method for manufacturing a semiconductor device according to the present invention in the order of steps. 10 is a semiconductor substrate, 11 is an insulating film, 12 is a first
13 is a columnar protrusion (conductor film), 15 is a first insulating film, 17 is a second insulating film, and 18 is a second wiring body.
Claims (1)
において、半導体基板１０上に配線膜１２を形成
し、前記配線膜１２とは弗素系の反応ガスによる
ドライエツチングに対する被エツチングレートの
異なる導電材料よりなる導電体膜１３を形成する
工程と、 前記導電体膜１３及び配線膜１２を部分的に除
去して前記配線膜１２よりなる所定パターンの第
１の配線体１２を形成する工程と、 前記第１の配線体１２が形成されていない前記
半導体基板１０上の部分に前記第１の絶縁膜１５
を前記配線膜１２と導電体膜１３の接続面より表
面がやや高くなるように被着形成する工程と、 弗素系反応ガスのドライエツチングにより前記
第１の配線体１２上の前記導電体膜１３を部分的
に除去して前記第１の配線体より狭い柱状突起体
を形成すると共に、記第１の絶縁膜１５をその表
面が配線膜１２と導電体膜１３の接続面の高さと
ほぼ同じになるよう除去する工程と、 前記柱状突起体１３の側周を囲み前記第１の配
線体１２及び前記第１の絶縁膜１５の上面を覆う
第２の絶縁膜１７を形成する工程と、 前記柱状突起体１３及び前記第２の絶縁膜１７
の上に第２の配線体１８を形成する工程と、 を含むことを特徴とする半導体装置の製造方
法。[Scope of Claims] 1. In a method of manufacturing a semiconductor device having a multilayer wiring structure, a wiring film 12 is formed on a semiconductor substrate 10, and the wiring film 12 has a high etching rate when dry etching is performed using a fluorine-based reactive gas. a step of forming a conductor film 13 made of a different conductive material; and a step of partially removing the conductor film 13 and the wiring film 12 to form a first wiring body 12 with a predetermined pattern made of the wiring film 12. and the first insulating film 15 is formed on a portion of the semiconductor substrate 10 where the first wiring body 12 is not formed.
The conductive film 13 on the first wiring body 12 is formed by depositing the conductive film 13 on the first wiring body 12 so that the surface thereof is slightly higher than the connection surface between the wiring film 12 and the conductive film 13, and dry etching with a fluorine-based reactive gas. is partially removed to form a columnar protrusion narrower than the first wiring body, and the surface of the first insulating film 15 is approximately the same height as the connection surface between the wiring film 12 and the conductive film 13. a step of forming a second insulating film 17 surrounding the side periphery of the columnar protrusion 13 and covering the upper surface of the first wiring body 12 and the first insulating film 15; Columnar protrusion 13 and second insulating film 17
A method of manufacturing a semiconductor device, comprising: forming a second wiring body 18 on the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3364880A JPS56130951A (en) | 1980-03-17 | 1980-03-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3364880A JPS56130951A (en) | 1980-03-17 | 1980-03-17 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56130951A JPS56130951A (en) | 1981-10-14 |
| JPS6255701B2 true JPS6255701B2 (en) | 1987-11-20 |
Family
ID=12392261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3364880A Granted JPS56130951A (en) | 1980-03-17 | 1980-03-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56130951A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60261156A (en) * | 1984-06-08 | 1985-12-24 | Nippon Telegr & Teleph Corp <Ntt> | Method for forming multiple-layer wiring |
| EP0175604B1 (en) * | 1984-08-23 | 1989-07-19 | Fairchild Semiconductor Corporation | A process for forming vias on integrated circuits |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4835778A (en) * | 1971-09-09 | 1973-05-26 |
-
1980
- 1980-03-17 JP JP3364880A patent/JPS56130951A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4835778A (en) * | 1971-09-09 | 1973-05-26 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56130951A (en) | 1981-10-14 |
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