JP2515801B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure such as a semiconductor integrated circuit, and more particularly to a semiconductor device having a multilayer wiring structure having a wiring structure of two or more layers.

[Conventional technology]

In a conventional semiconductor integrated circuit, particularly a wiring structure, an insulating film 20 such as SiO ₂ is vapor-deposited on a silicon substrate 10 on which active elements (not shown) such as transistors are formed as shown in FIG. And the like, and then a portion (not shown) necessary for connection between the substrate 10 and the first-layer wiring body layer 30 formed on the first insulating film 20 thereon is formed by well-known photolithography and After removing with an etching technique, a conductor layer 30 of aluminum or the like is formed on the entire surface, and the unnecessary portion of the conductor film is removed with a photolithography and etching technique to obtain a desired first layer wiring 30 pattern. ing. Next, in order to obtain two or more wiring layers on the first wiring layer 30, the second insulating film 40 made of SiO ₂ or the like is deposited on the first wiring layer 30 by using the above method or the high frequency sputtering method. After that, the insulating film of the contact portion 50 necessary for connection with the second layer wiring 60 formed thereon is selectively removed, and then a conductor layer of aluminum or the like is coated on the entire surface by using a high frequency sputtering method or the like. Then, the desired second layer wiring 60 pattern was obtained by a known method. Before depositing the second-layer conductor film, a sputter cleaning process is usually performed to clean the surface of the first-layer wiring 30 exposed at the contact portion. This treatment is for removing the non-conductive layer such as an oxide film layer formed on the surface of the first layer wiring 30 and improving the electrical conduction characteristics between the first layer wiring 30 and the second layer wiring 60. .

Further, as a conventional method for producing a wiring structure that enables the formation of extremely fine wiring, there is a known example described in JP-A-61-141140. In this method, a resist processed into a predetermined size is provided on a substrate, and after a conductor layer is attached to the entire surface,
The conductor layer other than the side wall of the resist film is removed, and the resist film is also removed to obtain wiring with a desired spacing.

[Problems to be solved by the invention]

The above-mentioned conventional technique has a drawback that the following problems occur when an attempt is made to form a wiring pattern in a submicron region or finer than that. That is, when the width of the first-layer wiring is narrowed as described above, the adhesive surface between the wiring and the base insulating film is reduced, and the adhesive force is reduced, so that the wiring pattern is peeled off or falls. As mentioned above
The wiring forming method shown in the publicly known example of 61-141140 is to form wiring on the side wall of the resist and enables formation of a fine pattern, but the wiring may be peeled off after removing the resist. , No consideration is given to the problem of flapping. This problem becomes more remarkable as the height of the wiring becomes higher (the asperth ratio becomes larger). Therefore, in the above-mentioned method, it is difficult to increase the thickness even though the width of the wiring can be narrowed, and the resistance of the wiring is significantly increased. Also, the deposition of the wiring material film must be performed at a substrate temperature within the resist heat resistance range, which is also disadvantageous in terms of film quality adhesiveness.

Further, in the above-described conventional technique, when the mask alignment deviation occurs in the interlayer insulating film in the lithographic process for forming the contact hole, the contact hole is formed off the first layer wiring pattern. In the sputtering cleaning method, usually only the upper surface of the first layer wiring exposed in the contact hole is cleaned. In this case, therefore, only a contact area smaller than a desired area can be obtained, and the contact resistance increases. Will be done. In order to avoid this problem, conventionally, a mask has been designed with a sufficient alignment margin between the first layer wiring and the contact hole. However, this method of increasing the alignment margin hinders the reduction of the wiring pitch and poses a serious problem in improving the degree of integration of the integrated circuit. Particularly, in the case of the narrow and thick wiring as in the present invention, the area of the connecting portion with the upper layer wiring becomes extremely small, which is disadvantageous.

An object of the present invention is to provide a highly integrated semiconductor device having a small contact resistance at a connection portion with a wiring having a large aspect ratio and a small wiring pitch.

[Means for solving problems]

The above-mentioned object is to provide a semiconductor substrate on which an element is formed, a first insulating film formed on the semiconductor substrate, and a second insulating film formed on the first insulating film and having a predetermined shape. An upper surface of the first layer wiring, which is formed on a sidewall of the second insulating film and is formed on the semiconductor substrate having the first layer wiring having a height higher than the width and the first layer wiring. A third insulating film having an opening for exposing a part of the upper surface of the first-layer wiring and one sidewall surface so that the depth of exposure on the sidewall surface is larger than the width of exposure of This is achieved by a semiconductor device having a second wiring, which is electrically connected to the upper surface and the side wall surface of the first layer wiring exposed in the opening and is extended on the third insulating film.

The formation of a fine wiring pattern having a large aspect ratio is achieved by using, as a wiring pattern, a portion of the conductor layer formed on the underlying insulating film having a step, which is attached to the sidewall of the underlying step. Further, if the present technology is adopted, it is possible to arrange the wiring pattern by combining two or more kinds of conductor materials in a direction different from the main plane direction of the substrate, that is, in the side wall direction of the wiring. Therefore, by using this technology to realize a structure in which a material that can be selectively etched by gas etching in a gas plasma or a reactive gas is pre-deposited on the side wall of the lower layer wiring, the upper layer wiring is deposited on the contact hole. It is possible to clean the exposed upper surface and the side wall surface of the lower wiring with gas plasma before the contact, and a contact having good conduction characteristics is realized.

[Action]

With the above-described structure, in the interlayer connection portion of the multilayer wiring structure, it is possible to obtain a contact having good conduction characteristics between the upper surface and side wall surface of the first layer wiring and the second layer wiring. A shift between the hole and the first layer wiring can be allowed. Therefore, the design wiring pitch of the integrated circuit can be reduced, and the degree of integration can be improved.

Among the above-mentioned means, the wiring formed on the side wall portion of the underlying step and the underlying insulating film are mainly bonded to each other in the sidewall area of the wiring. Therefore, even if the width of the main wiring is made fine, the adhesiveness of the side wall portion is not deteriorated, and the wiring is not peeled or dropped. It should be noted that the higher the wiring height, that is, the larger the wiring aspest ratio, the more effectively this action works.

Further, the above means can achieve a combination of two or more kinds of conductors or compound materials in the direction of the side wall of the wiring. On the other hand, dry etching by neutral radicals in gas plasma or gas etching in a reactive gas atmosphere is also suitable for etching the side wall surface of a wiring pattern. Therefore, if a material that can remove the material forming the sidewall of the underlying wiring by etching in the vapor phase atmosphere is selected by the means described above, the upper surface and sidewall surface of the first layer wiring exposed in the contact hole can be selected. Will be easier to clean.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to Examples and Examples.

Reference Example FIGS. 1A to 1D are schematic sectional views showing one reference example of a wiring structure and a manufacturing process related to the present invention. As shown in FIG. 1A, on a silicon substrate 10 in which elements (not shown) such as transistors and resistors are formed, silicon dioxide which covers a portion other than the electrode lead-out portion and has a predetermined uneven step. A film 20 is formed, and then a first conductor layer 30 made of aluminum is applied to the entire surface. Here, the above-mentioned silicon dioxide film is N ₂ O, N ₂ + SiH at a temperature of 800 ° C.
It is a film deposited by the CVD method using ₄ (4%) as a reaction gas.
The steps were formed by the well-known photolithography technique and the dry etching method using CF ₄ as an etching gas, and the groove depth was set to about 2 μm. The aluminum film is LPCVD using triisobutylaluminum (TIBAL) as a raw material.
Formed by the method. TIBAL flow rate is 50 SCCM, substrate temperature is 250 ℃
And the pressure is 0.5 Torr. A of about 1 μm after 10 minutes of deposition
l formed a film. In addition, as a treatment before depositing the Al film, the present silicon substrate was treated with Ti at a substrate temperature of 250 ° C. and a pressure of 0.2 Torr.
Exposed to Cl ₄ atmosphere for about 1 minute.

Next, as shown in FIG. 3B, the first layer wiring 30 was formed by processing under the condition that only the Al film on the step side wall of the underlying insulating film remained. This processing was performed by anisotropic dry etching, and a mixture of BCl ₃ and 30% CCl ₄ was used as an etching gas at a pressure of 0.1 Torr.

Next, as shown in FIG. 3C, an interlayer insulating film 40 made of polyimide resin is formed to a thickness of about 3 μm, and then a predetermined portion to be a connecting portion between conductor layers is removed by etching. A contact hole 50 is provided in the polyimide resin. The polyimide resin used in this example is a commercially available resin, PIQ
(Manufactured by Hitachi Chemical Co., Ltd.). Incidentally, for the purpose of improving the adhesiveness between the polyimide resin and the base before forming the polyimide resin, the Al chelate solution is spin-coated on the substrate,
Then, heat treatment was performed to form a film of an Al chelate compound. Then, the above-mentioned polyimide was applied on the substrate by a spin coating method, and heat treatment was performed to evaporate the solvent and polymerize and cure the resin. Further, the well-known photolithography technique for forming the contact hole of the polyimide resin and the plasma etching technique using O ₂ gas were used. Next, as shown in FIG. 1D, the second layer wiring 60 was formed. This wiring is deposited by the well-known sputtering method and processed by well-known photolithography and etching technology. In this reference example, a well-known sputter cleaning process is used for cleaning the lower wiring surface.

In the present reference example, the bottom surface and the side wall surface of the first layer wiring 30 are always bonded to the underlying insulating film 20, and the adhesive force between the first layer wiring and the underlying layer has sufficient strength. Therefore, there is no problem that the first layer wiring is peeled off or dropped during manufacturing. Further, in this reference example, the first layer wiring having a width of about 1 μm and a height of about 2 μm was realized, but the same effect was obtained when the wiring having a larger aspect ratio was formed.

Note that this reference example is an example of a two-layer wiring structure, but it is needless to say that the present invention can be applied to arbitrary lower layer wiring and upper layer wiring even in the case of a multilayer wiring structure having more layers.

Example FIGS. 2A to 2D are schematic sectional views showing an example of the wiring structure and the manufacturing process of the present invention. The present embodiment is greatly different from the previous reference example in that the contact hole connecting the conductor layers is displaced from the first layer wiring. Further, the material of the base insulating film, the structure of the first layer wiring and the method of forming the second layer wiring, especially the cleaning process before deposition are different.
Other structures and manufacturing processes are similar to those of the reference example.

First, as shown in FIG. 2 (a), on the silicon substrate 10,
A silicon dioxide film 21 having a thickness of about 1 μm and a polyimide resin film 22 having a predetermined unevenness are formed. These films were formed by the same method as in the first embodiment, the silicon dioxide film was formed by the CVD method, and the polyimide film was formed by the spin coating method. The processing of the polyimide film is also performed by O ₂ plasma as in the case of the above-mentioned reference example, and the shape of the groove width is 2 μm.
m. Next is Silicon 31, Alnium 32, Silicon 33
The first conductor layer having a three-layer structure is deposited on the entire surface. The silicon films 31 and 33 were each formed to 200 nm by the plasma CVD method. At this time, for deposition, a mixed gas of SiH ₄ 30 SCCM and H _{2 1} SCCM was kept at a pressure of 0.3 Torr, a substrate temperature of 350 ° C., and a frequency
Plasma discharge was generated by high frequency power of 13.56MHz, 0.2W / cm ² . The aluminum film 32 was formed by the LPCVD method using TIBAL as a main raw material in the same manner as in the case of the reference example.
6 μm was deposited.

Next, as shown in FIG. 4B, the processing is performed under the condition that only the step side walls of the three-layer conductive layer remain, and the first layer wiring 3
1,32,33 were formed. Next, as shown in FIG. 6C, an interlayer insulating film 40 made of polyimide resin was formed to a thickness of about 3 μm as in the reference example, and then a predetermined contact hole 50 to be a connection portion between conductor layers was provided. .

In this embodiment, the contact hole is displaced from the first layer wiring pattern, and a part of the upper surface and a part of the side wall surface of the first layer Al wiring are exposed in the contact hole. Moreover, as shown in FIG. 2 (d), the depth of the exposed side wall surface is larger than the width of the exposed upper surface.

Next, as shown in FIG. 2D, a second layer wiring 60 was formed. The details will be described below. The substrate after opening the contact holes as shown in FIG. 7C is placed in a sputtering device having a plasma generating mechanism. First, SF ₆ gas was introduced to adjust the pressure to 0.1 Torr, and then the frequency of 13.56 MH was applied to the substrate.
A high frequency power of 0.4 W / cm ² was applied to etch and remove the silicon film 31 on the side wall of the first-layer Al wiring 32 in the contact hole 50. Then, immediately evacuate the inside of the vacuum container, introduce Ar gas, and if necessary, perform the same cleaning as in the case of SF ₆ gas above, and then use the normal sputter method.
An Al film of about 1 μm was deposited. After that, the Al film was patterned by using a normal photolithography technique and a dry etching method to form the second layer wiring 60.

According to the present embodiment, even when the contact hole is formed off the first layer wiring, the contact surface between the second layer wiring and the upper surface and side wall surface of the first layer wiring exposed in the contact hole is extremely small. It shows good conduction characteristics and has the effect of the contact resistance reduction ratio.

In this embodiment, silicon is used as the sidewall material of the first layer wiring, but other materials such as molybdenum and tungsten that can be removed by etching with neutral radicals in gas plasma are also used. However, the same effect is shown. Further, the side wall material formed on the lower layer wiring is not limited to a conductive material, and if it does not contain oxygen, that is, if it is a material that does not oxidize the surface of the wiring material, it has the same effect as this embodiment. Good results were obtained when the SiN film formed by the plasma CVD method was used as the sidewall material.

Further, in this embodiment, the first exposed portion in the contact hole 50
Although all the silicon film 31 on the surface of the layer wiring is removed by etching, it is not always necessary to remove all of the present silicon layer, and an etching amount may be sufficient to remove a part of the surface by performing a heat treatment step later.

In addition, in this embodiment, as the surface cleaning treatment of the lower wiring,
Silicon was removed by the plasma etching method of SF ₆ gas, but the same effect was obtained by the method of etching while irradiating the gas containing fluorine with ultraviolet rays.

Furthermore, a method using hydrogen plasma was also effective for etching silicon.

Furthermore, in this embodiment, a structure in which silicon layers are attached to both side walls of the first layer wiring is adopted. However, even when the silicon layer is provided only on one side wall of the first layer wiring, the margin of the layout design of the contact hole is somewhat limited, but the same effect can be obtained. In this embodiment, the two-layer wiring structure is taken as an example, but it is needless to say that the present invention can be applied to arbitrary lower layer wiring and upper layer wiring even when a multilayer wiring structure having more layers is formed.

〔The invention's effect〕

According to the present invention, it is possible to stably provide a fine wiring and a wiring having a large aspect ratio without the wiring being dented or peeled off when the wiring is formed. Further, in the interlayer connection portion of the multilayer wiring structure, it is possible to obtain a contact having good conduction characteristics between the upper surface of the upper layer wiring and the lower layer wiring and the side wall surface. can do. Therefore,
The present invention enables reduction of design wiring pitch of an integrated circuit,
Effective in improving the degree of integration.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing a reference example of a manufacturing process of a semiconductor device related to the present invention, FIG. 2 is a schematic sectional view showing an embodiment of a manufacturing process of a semiconductor device of the present invention, and FIG. 3 is a schematic cross-sectional view of the wiring structure of FIG. 10 …… Silicon substrate, 20,21,22 …… Base insulating film, 30,31,
32,33 …… First layer wiring, 40 …… Interlayer insulating film, 50 …… Contact hole, 60 …… Second layer wiring.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Eiichi Murakami 1-280 Higashi Koigakubo, Kokubunji City, Central Research Laboratory, Hitachi, Ltd. (72) Inventor Yoshio Honma 1-280 Higashi Koigakubo, Kokubunji City, Central Research Laboratory, Hitachi Ltd. (56) References JP 58-52849 (JP, A) JP 63-147347 (JP, A) JP 61-141140 (JP, A) JP 57-106051 (JP, A) JP-A-58-147133 (JP, A) JP-A-61-96734 (JP, A) JP-A-62-205647 (JP, A) JP-A-63-86451 (JP, A) JP-A-57-139940 ( JP, A) JP 61-172327 (JP, A) JP 63-133551 (JP, A)

Claims (1)

(57) [Claims] 1. A semiconductor base on which an element is formed, a first insulating film formed on the semiconductor base, and a second insulating film formed on the first insulating film and having a predetermined shape.
A first layer wiring formed on the side wall of the second insulating film and having a height higher than the width, and the first layer wiring formed on the semiconductor substrate having the first layer wiring. A third insulation having an opening through which a part of the upper surface of the first layer wiring and one side wall surface are exposed so that the depth of the exposure on the side wall surface is larger than the width of the upper surface of the wiring. And a second layer wiring electrically connected to the upper surface and side wall surface of the first layer wiring exposed in the opening and extending on the third insulating film. Characteristic semiconductor device.